CN108682673A - A kind of electrostatic discharge protective circuit applied to radio circuit - Google Patents
A kind of electrostatic discharge protective circuit applied to radio circuit Download PDFInfo
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- CN108682673A CN108682673A CN201810515808.1A CN201810515808A CN108682673A CN 108682673 A CN108682673 A CN 108682673A CN 201810515808 A CN201810515808 A CN 201810515808A CN 108682673 A CN108682673 A CN 108682673A
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- 230000001681 protective effect Effects 0.000 title claims abstract description 24
- 238000001514 detection method Methods 0.000 claims abstract description 21
- 230000005611 electricity Effects 0.000 claims abstract description 11
- 230000003068 static effect Effects 0.000 claims abstract description 9
- 239000000203 mixture Substances 0.000 claims abstract description 8
- 101150110971 CIN7 gene Proteins 0.000 claims description 16
- 101150110298 INV1 gene Proteins 0.000 claims description 16
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000004224 protection Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 101100508840 Daucus carota INV3 gene Proteins 0.000 description 1
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
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- 238000007689 inspection Methods 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
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- 238000012544 monitoring process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of electrostatic discharge protective circuits applied to radio circuit, including：One protective circuit of diode, a circuit for producing high voltage, a detection circuit, a buffer circuit, a delay circuit, a leadage circuit.The circuit for producing high voltage and delay circuit, are all composed of PMOS tube and NMOS.The buffer circuit, by a phase inverter, a metal-oxide-semiconductor, a resistance and a capacitance composition.When chip works normally, electrostatic discharge protective circuit does not work, and when electrostatic event occurs, the present invention can generate the electric current that higher voltage carrys out static electricity discharge generation, can also increase the time of static electricity discharge, so that chip can have better antistatic property.
Description
Technical field
The present invention relates to electrostatic protection fields, more particularly to a kind of power clamp electrostatic discharge protective circuit.
Background technology
In recent years with the fast development of integrated circuit technology, the line width of metal-oxide-semiconductor is more and more narrow, and junction depth is more and more shallow, grid
The thickness of oxygen layer is also more and more thinner, these all accelerate circuit design to electrostatic protection（ESD, Electro-Static
discharge）Demand.When line width is 1 μm, influence very little of the esd event to circuit, when entering 0.18 μm, 0.13 μm
Generation, especially 90 nanometer or less epoch, ESD become very urgent problem.In radio circuit and various interlock circuits
Always, it is required for corresponding electrostatic discharge protective circuit.
General ESD points are HBM（Human body model Human Body Models）Pattern, MM（Machine model machines
Pattern）Pattern and CDM（Charged device model band power modes）Pattern.HBM and MM patterns are external to chip progress
Electric discharge, the esd protection circuit for relying solely on input/output port is far from being enough, it is also necessary to add ESD between power supply and ground
Protect circuit（Power clamp ESD circuit）, so as to more quick leakage current, to ensure the ESD performances of entire chip.
It is shown in Figure 1, existing power clamp ESD circuit.
Detection circuit is made of resistance R1 and capacitance C1, and RC delay times decide the time of leakage current, when delay
Between it is bigger, the leakage current time is also more.The detection circuit is for detecting esd pulse, the correct esd pulse and normal distinguished
Power supply electrifying pulse.When power supply normally powers on, detection circuit will ensure that power clamp ESD circuit is not turned on, when generation ESD things
When part, detection circuit wants that esd pulse can be quickly detected, and power clamp ESD circuit is guided to work, thus leakage current,
Protect chip internal circuits.
Buffer circuit, the phase inverter INV1~INV3 being connected in series with by three are formed, and are used for the output of amplification detection circuit,
Driving capability is provided to leadage circuit, to drive bleeder pipe to work.
Leadage circuit is made of NMOS transistor NM1, for the ESD electric currents, when an esd event occurs, vent discharge of releasing
Road can normally open ESD electric currents of releasing；When circuit works normally, leadage circuit is to close.When since esd event occurs,
Electric current is all order of amps, and the NMOS transistor size of leadage circuit is all larger.
When esd event occurs at chip pin, ESD voltage or electric current are left to by D1 on VDD, are then passed through again
NM1 pipes are come ESD electric currents of releasing.Grid voltage on NM1 pipes is exactly vdd voltage, the voltage lower than the voltage at chip pin place one
A diode drop.
The time that power supply normally powers on is generally 1ms or so, and occur esd event time be tens nanosecond rank.Inspection
Slowdown monitoring circuit not only will correctly distinguish esd pulse and normal power supply electrifying pulse, also increase delay time as possible, to increase
It releases time of ESD electric currents.Detection circuit in Fig. 1 is designed with RC circuits into line delay, if the RC times are longer, leakage current
Effect can be more preferable.For structure in Fig. 1 when releasing ESD electric currents, the voltage of grid is exactly VDD on NM1 pipes, and the voltage is higher, lets out
Discharge stream also can be faster.
Invention content
The technical problem to be solved in the present invention is to provide a kind of electrostatic discharge protective circuits, when chip normally powers on, it is ensured that
ESD circuit is closed, will not the work of false triggering ESD circuit, it is when an esd event occurs, as far as possible again to release more
ESD electric currents, to protect the internal components of circuit without damage.
In order to solve the above technical problems, the present invention is achieved by the following technical solutions：
A kind of electrostatic discharge protective circuit applied to radio circuit, its main feature is that, including：
One protective circuit of diode is made of the first diode D1 and the second diode D2, for providing drain passageway；
One circuit for producing high voltage is made of the second NMOS tube NM2, the first PMOS tube PM1 and the second PMOS tube PM2, is let out for giving
The grid for putting pipe provides higher driving voltage；
One detection circuit is made of first resistor R1 and the first capacitance C1, for detecting whether electrostatic event occurs；
One buffer circuit, by the first phase inverter INV1, third NMOS tube NM3, second resistance R2 and the second capacitance C2 compositions are used for
Increase static electricity discharge current time and driving is provided；
One delay circuit is made of the 4th NMOS tube NM4 and third PMOS tube PM3, the time for increasing static electricity discharge；
One leadage circuit is made of the first NMOS transistor NM1, for main electrostatic induced current of releasing.
The protective circuit of diode, chip pin end, the drain electrode of PM1 pipes, the anode of diode D1, diode D2 it is negative
The input terminal of pole and internal circuit links together, which is labeled as VA points, and the cathode of diode D1 is connected with VDD, diode
The anode of D2 is connected with ground.
The drain electrode of the circuit for producing high voltage, PM1 pipes is connected with VA points, and the source electrode of PM1 pipes is connected simultaneously with the source electrode of PM2 pipes
Labeled as VDDH, the grid of the grid of PM1 pipes, the grid of PM2 pipes and NM2 pipes is connected together, which is labeled as VB, PM2
The drain electrode of pipe is connected with the drain electrode of NM2 pipes, the source electrode ground connection of NM2 pipes.
The detection circuit, the first capacitance C1 and first resistor R1 series connection, output of the concatenated point as detection circuit
End, the other end of capacitance C1 are connected with power vd D, and the other end and ground of resistance R1 connect.
The input terminal of the buffer circuit, the output end of detection circuit and the first phase inverter INV1 are connected together, INV1
Output end, NM3 pipes drain electrode, second resistance R2 and the second capacitance C2 be connected to VB points, the other end of capacitance C2, NM3 pipes
Source electrode and INV1 ground terminal ground connection, the other end of resistance R2 and the power end of INV1 are connected to power vd D.
The grid of the delay circuit, NM4 pipes meets VDD, and the drain electrode of NM4 pipes connects the drain electrode of PM2 pipes and the drain electrode of NM2 pipes,
The drain electrode of the source electrode, PM3 pipes of NM4 pipes is connected with the grid of NM1 pipes, which is labeled as VC points, and the source electrode of PM3 pipes meets VA points, PM3
The grid of pipe connects VB points.
The leadage circuit, the first NMOS tube NM1 source electrodes and ground connect, and the drain electrode of NM1 pipes is connected with VDD, the grid of NM1 pipes
Pole is connected to VC points.
The present invention has the following advantages compared with existing electrostatic discharge protective circuit：
When an esd event occurs, accelerate releasing for ESD electric currents by improving bleeder pipe grid voltage, the time same in this way
It is interior can be with the more ESD electric currents of aerial drainage, in addition delay circuit can allow bleeder pipe to have more times to carry out static electricity discharge electric current, allow
Electrostatic induced current is released more abundant, therefore can preferably protect internal components.
Description of the drawings
Fig. 1 is existing electrostatic discharge protective circuit schematic diagram；
Fig. 2 is the one embodiment schematic diagram of electrostatic discharge protective circuit of the present invention.
Specific implementation mode
The present invention is described in further detail with specific implementation mode below in conjunction with the accompanying drawings：
It is shown in Figure 2, in the following embodiments, electrostatic discharge protective circuit of the present invention, including：
One protective circuit of diode is made of the first diode D1 and the second diode D2；One circuit for producing high voltage, by second
NMOS tube NM2, the first PMOS tube PM1 and the second PMOS tube PM2 compositions；One detection circuit, by first resistor R1 and the first capacitance
C1 is formed；One buffer circuit, by the first phase inverter INV1, third NMOS tube NM3, second resistance R2 and the second capacitance C2 compositions；
One delay circuit is made of the 4th NMOS tube NM4 and third PMOS tube PM3；One leadage circuit, by the first NMOS transistor NM1
Composition.
The detection circuit of resistance R1 and capacitance C1 compositions, such as it is 150ns or so, general ESD to design its RC delay time
The time of origin of event is all tens ns ranks, and when an esd event occurs, detection circuit can be detected correctly, when
When chip fast powering-up, and will not false triggering.
When chip normally powers on, the output end of detection circuit is low level, and the output end of phase inverter INV1 is exactly high
Level, the cut-off of PM2 pipes, the at this time drain electrode of NM4 pipes are exactly low level, and NM4 pipes are conductings, are closed then bleeder pipe NM1 is in
State.Although the voltage of VA points can be transferred to VC by PM3 pipes, it can also be released to ground quickly, VC points are also maintained at low
On level.
It waits when an esd event occurs, the output end of detection circuit is high level, then the output end of phase inverter INV1 is exactly
Low level, conducting PM1 pipes and PM2 pipes, VDDH voltages are just transferred to VC points by NM4 pipes, and NM1 pipes start leakage current.VDDH
Voltage is exactly the ESD voltage introduced at chip pin, and a diode drop higher than vdd voltage, the grid voltage of NM1 pipes gets over
Height, leakage current can be faster.
It waits when an esd event occurs, since the grid of NM1 pipes is connected with NM3 tube grids, NM3 pipes are also switched on, by VB
Point is pulled in low level state, the conducting of PM3 pipes, and NM1 pipes can also be made to start aerial drainage, at the same VC points also more stablize it is steady in height
Level state, then NM1 pipes are also just in stable leakage current.When the output end of detection circuit slowly becomes low level, have
The delay circuit of R2 and C2 compositions can make the output end of INV1 in the low level of lasting one end time, then the output end of INV1
Become high level again, finally close NM1 pipes, to complete the whole process of ESD protections.Its advantage is exactly when esd event terminates
When, it still may also rely on RC and be delayed and carry out abundant leakage current for a period of time to NM1 pipes, preferably protect chip interior device.
The delay circuit being made of R2 and C2, time constant can be arranged longer, such as 200us.
When esd event occurs, PM3 pipes are also conducting, can also the voltage of VA points be directly transferred to VC points,
It is also possible that NM1 manages faster static electricity discharge electric current, the VB long periods maintain low level, have also given leak-off pipe more
It releases the time.Therefore the characteristics of circuit is existing high pressure to drive bleeder pipe, and can provide the process of releasing of longer time.
Analog simulation being carried out using smic 0.13um techniques, under equal conditions, it is assumed that the ESD voltage of moment is 20V,
The grid of the circuit of background technology, NM1 pipes releases high pressure as 17.8V, and the time of releasing is 230ns, and in the circuit of the present invention, it lets out
The high pressure for putting tube grid is 19.6V, and the time of releasing is 950ns, and from the point of view of simulation comparison result, the present invention has higher release
The time of voltage and longer static electricity discharge electric current.
Although the present invention is illustrated using specific embodiment, the present invention's is not intended to limit to the explanation of embodiment
Range.One skilled in the art is by reference to explanation of the invention, without departing substantially from the spirit and scope of the present invention
In the case of, it is easy to carry out various modifications or embodiment can be combined.
Claims (7)
1. a kind of electrostatic discharge protective circuit applied to radio circuit, which is characterized in that including：
One protective circuit of diode is made of the first diode D1 and the second diode D2, for providing drain passageway；
One circuit for producing high voltage is made of the second NMOS tube NM2, the first PMOS tube PM1 and the second PMOS tube PM2, is let out for giving
The grid for putting pipe provides higher driving voltage；
One detection circuit is made of first resistor R1 and the first capacitance C1, for detecting whether electrostatic event occurs；
One buffer circuit, by the first phase inverter INV1, third NMOS tube NM3, second resistance R2 and the second capacitance C2 compositions are used for
Increase static electricity discharge current time and driving is provided；
One delay circuit is made of the 4th NMOS tube NM4 and third PMOS tube PM3, the time for increasing static electricity discharge；
One leadage circuit is made of the first NMOS transistor NM1, for main electrostatic induced current of releasing.
2. a kind of electrostatic discharge protective circuit applied to radio circuit as described in claim 1, which is characterized in that the diode
Protect circuit, chip pin end, the drain electrode of PM1 pipes, the input of the anode of diode D1, the cathode of diode D2 and internal circuit
End links together, which is labeled as VA points, and the cathode of diode D1 is connected with VDD, and the anode of diode D2 is connected with ground.
3. a kind of electrostatic discharge protective circuit applied to radio circuit as described in claim 1, which is characterized in that the high pressure production
Raw circuit, the drain electrode of PM1 pipes are connected with VA points, and the source electrode of PM1 pipes is connected with the source electrode of PM2 pipes and is labeled as VDDH, PM1 pipes
The grid of grid, the grid of PM2 pipes and NM2 pipes is connected together, which is labeled as VB, the drain electrode of PM2 pipes and the leakage of NM2 pipes
Pole is connected, the source electrode ground connection of NM2 pipes.
4. a kind of electrostatic discharge protective circuit applied to radio circuit as described in claim 1, which is characterized in that the detection
Circuit, the first capacitance C1 and first resistor R1 series connection, output end of the concatenated point as detection circuit, the other end of capacitance C1
It is connected with power vd D, the other end and ground of resistance R1 connect.
5. a kind of electrostatic discharge protective circuit applied to radio circuit as described in claim 1, which is characterized in that the caching electricity
The input terminal of road, the output end of detection circuit and the first phase inverter INV1 are connected together, the leakage of the output end, NM3 pipes of INV1
Pole, second resistance R2 and the second capacitance C2 are connected to VB points, other end, the source electrode of NM3 pipes and the ground terminal of INV1 of capacitance C2
Ground connection, the other end of resistance R2 and the power end of INV1 are connected to power vd D.
6. a kind of electrostatic discharge protective circuit applied to radio circuit as described in claim 1, which is characterized in that the delay electricity
Road, the grids of NM4 pipes meet VDD, and the drain electrodes of NM4 pipes connects the drain electrode of PM2 pipes and the drain electrode of NM2 pipes, the source electrodes of NM4 pipes, PM3 pipes
Drain electrode is connected with the grid of NM1 pipes, which is labeled as VC points, and the source electrode of PM3 pipes connects VA points, and the grid of PM3 pipes connects VB points.
7. a kind of electrostatic discharge protective circuit applied to radio circuit as described in claim 1, which is characterized in that the vent discharge
Road, the first NMOS tube NM1 source electrodes and ground connect, and the drain electrode of NM1 pipes is connected with VDD, and the grid of NM1 pipes is connected to VC points.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810515808.1A CN108682673A (en) | 2018-05-26 | 2018-05-26 | A kind of electrostatic discharge protective circuit applied to radio circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810515808.1A CN108682673A (en) | 2018-05-26 | 2018-05-26 | A kind of electrostatic discharge protective circuit applied to radio circuit |
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| Publication Number | Publication Date |
|---|---|
| CN108682673A true CN108682673A (en) | 2018-10-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810515808.1A Withdrawn CN108682673A (en) | 2018-05-26 | 2018-05-26 | A kind of electrostatic discharge protective circuit applied to radio circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109450432A (en) * | 2018-12-18 | 2019-03-08 | 珠海泰芯半导体有限公司 | A kind of rf inputs mouth protection circuit |
| CN110444542A (en) * | 2019-08-09 | 2019-11-12 | 北京思比科微电子技术股份有限公司 | A kind of electrostatic discharge protection structure of power pin |
| WO2022095509A1 (en) * | 2020-11-05 | 2022-05-12 | 长鑫存储技术有限公司 | Electrostatic protection circuit, integrated circuit, and electrostatic discharge method |
| US11929610B2 (en) | 2020-11-05 | 2024-03-12 | Changxin Memory Technologies, Inc. | Electrostatic discharge (ESD) protection circuit, integrated circuit, and electrostatic discharge method |
-
2018
- 2018-05-26 CN CN201810515808.1A patent/CN108682673A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109450432A (en) * | 2018-12-18 | 2019-03-08 | 珠海泰芯半导体有限公司 | A kind of rf inputs mouth protection circuit |
| CN109450432B (en) * | 2018-12-18 | 2024-04-02 | 珠海泰芯半导体有限公司 | Radio frequency input port protection circuit |
| CN110444542A (en) * | 2019-08-09 | 2019-11-12 | 北京思比科微电子技术股份有限公司 | A kind of electrostatic discharge protection structure of power pin |
| WO2022095509A1 (en) * | 2020-11-05 | 2022-05-12 | 长鑫存储技术有限公司 | Electrostatic protection circuit, integrated circuit, and electrostatic discharge method |
| US11929610B2 (en) | 2020-11-05 | 2024-03-12 | Changxin Memory Technologies, Inc. | Electrostatic discharge (ESD) protection circuit, integrated circuit, and electrostatic discharge method |
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Application publication date: 20181019 |