CN108666323B

CN108666323B - Semiconductor memory device with a plurality of memory cells

Info

Publication number: CN108666323B
Application number: CN201711135070.8A
Authority: CN
Inventors: 二山拓也; 四方刚
Original assignee: Toshiba Memory Corp
Current assignee: Kioxia Corp
Priority date: 2017-03-27
Filing date: 2017-11-16
Publication date: 2022-01-11
Anticipated expiration: 2037-11-16
Also published as: TWI644399B; TWI771943B; JP2018164070A; CN108666323A; TW201836074A; TWI724338B; TW201929150A; TW202147525A

Abstract

Embodiments provide a semiconductor memory device capable of improving operation reliability. A semiconductor memory device according to one embodiment includes: a 1 st region (BLK) including a plurality of 1 st wires (SGD) arranged side by side along a 1 st direction (X direction), a 1 st insulating film (SLT2) separating adjacent 1 st wires (SGD), and a 1 st column (MP) provided so as to extend across the adjacent 1 st wires (SGD); and 2 nd and 3 rd regions (SLT1) including a 2 nd insulating film and positioned so as to sandwich the 1 st region (BLK) in the 2 nd direction (Y direction). The 1 st column (MP) includes a conductive layer, a gate insulating film, and a charge accumulating layer. The number of the 1 st wires (SGD) provided in the 1 st region (BLK) is odd.

Description

Semiconductor memory device with a plurality of memory cells

[ related applications ]

The application has the priority of taking Japanese patent application No. 2017 and 61208 (application date: 3 and 27 in 2017) and Japanese patent application No. 2017 and 168249 (application date: 9 and 1 in 2017) as basic applications. The present application incorporates the entire contents of the base application by reference thereto.

Technical Field

Embodiments relate to a semiconductor memory device.

Background

A semiconductor memory in which memory cells are three-dimensionally arranged is known.

Disclosure of Invention

Embodiments provide a semiconductor memory device capable of improving operation reliability.

A semiconductor memory device according to an embodiment includes: a 1 st region including a 1 st wiring provided above the semiconductor substrate and arranged in parallel along a 1 st direction which is an in-plane direction of the semiconductor substrate, a 1 st insulating film separating adjacent 1 st wirings, and a 1 st column provided so as to extend between the adjacent 1 st wirings; and 2 nd and 3 rd regions positioned so as to sandwich the 1 st region in a 2 nd direction different from the 1 st direction in an in-plane direction of the semiconductor substrate, and including a 2 nd insulating film provided from the semiconductor substrate to a height of the 1 st wiring. The 1 st column includes a conductive layer, a gate insulating film, and a charge accumulating layer. The number of 1 st wirings provided in the 1 st region is odd.

Drawings

Fig. 1 is a block diagram of a semiconductor memory device according to embodiment 1.

Fig. 2 is a circuit diagram of the memory cell array of embodiment 1.

Fig. 3 is a plan layout of the select gate lines of embodiment 1.

Fig. 4 is a plan layout of word lines of embodiment 1.

Fig. 5 is a sectional view of the block of embodiment 1.

Fig. 6 is a sectional view of the block of embodiment 1.

Fig. 7 is a cross-sectional view of the memory cell transistor of embodiment 1.

Fig. 8 is a cross-sectional view of the memory cell transistor of embodiment 1.

Fig. 9 is a cross-sectional view of the memory cell transistor of embodiment 1.

Fig. 10 is a cross-sectional view of the memory cell transistor of embodiment 1.

Fig. 11 is an equivalent circuit diagram of the memory column of embodiment 1.

Fig. 12 is a plan layout of the select gate lines of embodiment 1.

Fig. 13 is a plan layout of the select gate lines of embodiment 1.

Fig. 14 is a timing chart of various signals in the read operation according to embodiment 1.

Fig. 15 is a plan layout of the select gate lines of variation 1 of embodiment 1.

Fig. 16 is a timing chart of various signals in the write operation according to embodiment 2.

Fig. 17 is a timing chart of various signals in the write operation according to embodiment 2.

Fig. 18 is a plan layout of the select gate lines of embodiment 3.

Fig. 19 is a plan layout of the select gate lines of embodiment 3.

Fig. 20 is a plan layout of the select gate lines of embodiment 3.

Fig. 21 is a plan layout of the select gate lines of embodiment 3.

Fig. 22 is a plan layout of the select gate lines in variation 1 of embodiment 3.

Fig. 23 is a plan layout of select gate lines according to variation 2 of embodiment 3.

Fig. 24 is a plan layout of the select gate lines of embodiment 4.

Fig. 25 is a plan layout of the select gate lines of variation 1 of embodiment 4.

Fig. 26 is a plan layout of select gate lines according to variation 2 of embodiment 4.

Fig. 27 is a plan layout of word lines of a 1 st modification example of the 1 st to 4 th embodiments.

Fig. 28 is an equivalent circuit diagram of a memory column of modification 2 of embodiment 1 to embodiment 4.

Fig. 29 is a sectional view of a partial region of a storage column according to variation 3 of embodiment 1 to embodiment 4.

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same functions and configurations are denoted by common reference numerals.

1. Embodiment 1

A storage system according to embodiment 1 will be described. Hereinafter, a memory system including a NAND (Not AND) flash memory as a semiconductor memory device will be described as an example.

1.1 about the constitution

The configuration of the NAND flash memory of the present embodiment will be described.

1.1.1 regarding the monolithic construction

First, a general overall configuration of the NAND flash memory according to the present embodiment will be described with reference to fig. 1.

As shown in the figure, the NAND-type flash memory 1 includes a memory cell array 2, a row decoder 3, and a sense amplifier 4.

The memory cell array 2 includes a plurality of blocks BLK. In fig. 1, only 4 blocks BLK0 to BLK3 are shown, but the number thereof is not limited. The block BLK includes a plurality of memory cells which are associated in rows and columns and stacked three-dimensionally. Further, the blocks BLK are provided on the semiconductor substrate, and slits SLT1 are provided between adjacent blocks. The configuration of the memory cell array 2 will be described in detail below.

The row decoder 3 decodes a row address received from the outside. Then, the row decoder 3 selects the row direction of the memory cell array 2 based on the decoding result. More specifically, voltages are applied to various wirings for selecting a row direction.

The sense amplifier 4 reads out data read from any block BLK when reading data. In addition, when data is written, a voltage corresponding to the written data is applied to the memory cell array 2.

1.1.2 composition of memory cell array 2

Next, the structure of the memory cell array 2 of the present embodiment will be explained.

< about the Circuit configuration >

First, a circuit configuration of the memory cell array 2 will be described with reference to fig. 2. Fig. 2 is an equivalent circuit diagram of the block BLK. As shown, the block BLK includes a plurality of memory groups MG (MG0, MG1, MG2, …). In addition, each memory group MG includes a plurality of NAND strings 50. Hereinafter, the NAND string of the even-numbered memory group MGe (MG0, MG2, MG4, …) is referred to as a NAND string 50e, and the NAND string of the odd-numbered memory group MGo (MG1, MG3, MG5, …) is referred to as a NAND string 50 o.

Each NAND string 50 includes, for example, 8 memory cell transistors MT (MT0 to MT7) and select transistors ST1 and ST 2. The memory cell transistor MT includes a control gate and a charge accumulation layer, and stores data in a nonvolatile manner. Further, the memory cell transistor MT is connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST 2.

The gates of the select transistors ST1 in each memory group MGe are connected to a select gate line SGD (SGD0, SGD1, …), respectively. The select gate lines SGD are independently controlled by the row decoder 3. Further, the gates of the select transistors ST2 in the even-numbered memory groups MGe (MG0, MG2, …) are commonly connected to a select gate line SGSe, for example, and the gates of the select transistors ST2 in the odd-numbered memory groups MGo (MG1, MG3, …) are commonly connected to a select gate line SGSo, for example. The selection gate lines SGSe and SGSo may be connected in common or may be independently controllable.

The control gates of the memory cell transistors MT (MT0 to MT7) included in the memory group MGe in the same block BLK are commonly connected to the word lines WLe (WLe0 to WLe7), respectively. On the other hand, the control gates of the memory cell transistors MT (MT0 to MT7) included in the memory group MGo are commonly connected to the word line WLo (WLo0 to WLo7), respectively. The select gate lines WLe and WLo are independently controlled by the row decoder 3.

The block BLK is, for example, a deletion unit of data. That is, the data held by the memory cell transistors MT included in the same block BLK is erased at a time.

Further, the drains of the select transistors ST1 of the NAND strings 50 located in the same column in the memory cell array 2 are commonly connected to bit lines BL (BL0 to BL (L-1), where (L-1) is a natural number of 2 or more). That is, the bit line BL connects the NAND strings 50 in common among the plurality of memory groups MG. Further, sources of the plurality of selection transistors ST2 are commonly connected to a source line SL.

That is, the memory group MG includes a plurality of NAND strings 50 connected to different bit lines BL and connected to the same select gate line SGD. In addition, the block BLK includes a plurality of memory groups MG of a plurality of common word lines WL. Also, the memory cell array 2 includes a plurality of blocks BLK that share bit lines BL. Further, in the memory cell array 2, the memory cell transistors MT are three-dimensionally stacked by stacking the select gate lines SGS, the word lines WL, and the select gate lines SGD over a semiconductor substrate.

< planar layout of memory cell array >

Next, a planar structure of the memory cell array 2 will be explained. Fig. 3 shows a planar layout of the select gate lines SGD in a semiconductor substrate plane (referred to as an XY plane) of a certain block BLK. In this example, a case where 8 selection gate lines SGD are included in 1 block BLK will be described.

As shown in the figure, 9 wiring layers 10(10-0 to 10-7, wherein 10-0 includes 10-0a and 10-0b) extending in the X direction are arranged along the Y direction orthogonal to the X direction. Each wiring layer 10 functions as a select gate line SGD. In the example of fig. 3, 2 wiring layers 10-0a and 10-0b at both ends in the Y direction in the block BLK function as the selection gate line SGD 0. That is, the 2 wiring layers 10 located at both ends in the Y direction are commonly connected to each other or controlled in the same manner by the row decoder 3. The 7 wiring layers 10-1 to 10-7 located therebetween function as select gate lines SGD1 to SGD7, respectively. Therefore, when viewed in the XY plane in the block BLK, the memory groups MG1 to MG7 are arranged along the Y direction, and the memory group MG0 is disposed on both sides thereof.

The wiring layers 10 adjacent to each other in the Y direction in the block BLK are separated by an insulating film not shown. The region where the insulating film is provided is referred to as a slit SLT 2. In the slit SLT2, the insulating film is embedded in a region from the semiconductor substrate surface to at least the layer where the wiring layer 10 is provided. In the memory cell array 2, a plurality of blocks BLK shown in fig. 3 are arranged in the Y direction, for example. Further, blocks BLK adjacent to each other in the Y direction are also separated by an insulating film not shown. The region where the insulating film is provided is the slit SLT1 described in fig. 1. Slit SLT1 is also the same as SLT 2.

Further, a plurality of memory pillars MP (MP0 to MP15) are provided between the wiring layers 10 adjacent in the Y direction, respectively, along the Z direction. The Z direction is a direction orthogonal to the XY direction, that is, a direction perpendicular to the semiconductor substrate surface.

Specifically, memory pillars MP0 and MP8 are provided between the wiring layers 10-1 and 10-2, memory pillars MP1 and MP9 are provided between the wiring layers 10-3 and 10-4, memory pillars MP2 and MP10 are provided between the wiring layers 10-5 and 10-6, and memory pillars MP3 and MP11 are provided between the wiring layers 10-7 and 10-0 b. The memory pillar MP is a structure in which the selection transistors ST1 and ST2 and the memory cell transistor MT are formed, and the details thereof will be described later.

The storage pillars MP0 to MP3 are arranged along the Y direction. The banks MP8 to MP11 are arranged along the Y direction so as to be adjacent to the banks MP0 to MP3 in the X direction. That is, the storage pillars MP0 to MP3 are arranged side by side with the storage pillars MP8 to MP 11.

The bit line BL0 is provided above the wiring layer 10 so as to be commonly connected to the memory pillars MP0 to MP 3. The bit line BL2 is provided above the wiring layer 10 so as to be commonly connected to the memory pillars MP8 to MP 11. Hereinafter, the memory pillars MP0 to MP3, the memory pillars MP8 to MP11, and the bit lines BL0 and BL2 may be referred to as a group GR 1.

Further, memory pillars MP4 and MP12 are provided between the wiring layers 10-0a and 10-1, memory pillars MP5 and MP13 are provided between the wiring layers 10-2 and 10-3, memory pillars MP6 and MP14 are provided between the wiring layers 10-4 and 10-5, and memory pillars MP7 and MP15 are provided between the wiring layers 10-6 and 10-7.

The memory pillars MP4 to MP7 are arranged along the Y direction, and the memory pillars MP12 to MP15 are also arranged along the Y direction. The storage pillars MP4 to MP7 are located between the storage pillars MP0 to MP3 and the storage pillars MP8 to MP11 in the X direction. The storage columns MP12 to MP15 are positioned so as to sandwich the storage columns MP8 to MP11 together with the storage columns MP4 to MP7 in the X direction. That is, the storage pillars MP4 to MP7 are arranged side by side with the storage pillars MP12 to MP 15.

The bit line BL1 is provided above the wiring layer 10 so as to be commonly connected to the memory pillars MP4 to MP 7. The bit line BL3 is provided above the wiring layer 10 so as to be commonly connected to the memory pillars MP12 to MP 15. Hereinafter, the memory pillars MP4 to MP7, the memory pillars MP12 to MP15, and the bit lines BL1 and BL3 may be referred to as a group GR 2.

That is, the memory pillars MP are provided so as to extend across 2 wiring layers 10 in the Y direction and to be buried in a part of any one of the slits SLT2, and 1 slit SLT2 exists between the memory pillars MP adjacent in the Y direction. The slit SLT2 into which the storage pillars MP belonging to the group GR1 are embedded is located between 2 storage pillars MP belonging to the group GR2, and the slit SLT2 into which the storage pillars MP belonging to the group GR2 are embedded is located between 2 storage pillars MP belonging to the group GR 1.

Further, the memory pillars MP are not provided between the wiring layers 10-0a and 10-0b adjacent to each other with the slit SLT1 interposed therebetween.

Fig. 4 shows a plan layout of word lines WL in the XY plane, similarly to fig. 3. Fig. 4 is a layout of the wiring layer 11 provided in a lower layer than the wiring layer 10 described in fig. 3, corresponding to the 1-block size region in fig. 3.

As shown in the figure, 9 wiring layers 11(11-0 to 11-7, wherein 11-0 includes 11-0a and 11-0b) extending in the X direction are arranged along the Y direction. Each wiring layer 11-0 to 11-7 is provided directly below the wiring layers 10-0 to 10-7 via an insulating film.

Each wiring layer 11 functions as a word line WL 7. The other word lines WL 0-WL 6 are also the same. If the example of FIG. 4, the wiring layers 11-0a, 11-2, 11-4, 11-6, and 11-0b function as word lines WLo 7. These wiring layers 11-0a, 11-2, 11-4, 11-6, and 11-0b are drawn out to the end portions along the X direction (the end portions are referred to as "1 st connection portions") and are commonly connected to each other. Further, at the 1 st connection portion, wiring layers 11-0a, 11-2, 11-4, 11-6, and 11-0b are connected to the row decoder 3.

The wiring layers 11-1, 11-3, 11-5, and 11-7 function as word lines WLe 7. These wiring layers 11-1, 11-3, 11-5, and 11-7 are drawn out to the 2 nd connection portion located on the opposite side of the 1 st connection portion in the X direction, and are connected in common with each other. Further, at the 2 nd connection portion, wiring layers 11-1, 11-3, 11-5, and 11-7 are connected to the row decoder 3.

Further, a memory cell unit is provided between the 1 st connection unit and the 2 nd connection unit. In the memory cell portion, the wiring layers 11 adjacent in the Y direction are separated by the slit SLT2 illustrated in fig. 3. Similarly, the wiring layers 11 between the blocks BLK adjacent in the Y direction are separated by the slits SLT 1. In addition, in the memory cell portion, the memory pillars MP0 to MP15 are provided in the same manner as in fig. 3.

The above configuration is also the same for other layers forming the word lines WL and the select gate lines SGS.

< Cross-sectional Structure of memory cell array >

Next, a cross-sectional structure of the memory cell array 2 will be explained. Fig. 5 is a cross-sectional view of the block BLK along the Y direction, and shows, as an example, a cross-sectional structure of a region along the bit line BL0 in fig. 3.

As shown in the drawing, a wiring layer 12 functioning as a selection gate line SGS is provided above a semiconductor substrate (e.g., a p-type well region) 13. Above the wiring layer 12, 8 wiring layers 11 functioning as word lines WL0 to WL7 are laminated along the Z direction. The planar layout of these

wirings

11 and 12 is shown in fig. 4. A wiring layer 10 functioning as a select gate line SGD is provided above the wiring layer 11. The planar layout of the wiring layer 10 is as illustrated in fig. 3.

Further, the slits SLT2 and the memory pillars MP are alternately arranged along the Y direction so as to reach the semiconductor substrate 13 from the wiring layer 10. As described above, the slit SLT2 is substantially an insulating film. However, a contact plug or the like for applying a voltage to a region provided in the semiconductor substrate 13 may be provided in the slit SLT 2. For example, a contact plug for connecting the source of the selection transistor ST2 to the source line may be provided.

The wiring layer 12 alternately functions as the selection gate line SGSo or SGSe with the slit SLT2 or the memory pillar MP interposed therebetween. Similarly, the wiring layer 11 alternately functions as the word line WLo or WLe with the slit SLT2 or the memory pillar MP interposed therebetween.

In addition, slits SLT1 are provided between blocks BLK adjacent in the Y direction. As described above, the entity of the slit SLT1 is also an insulating film. However, a contact plug or the like for applying a voltage to a region provided in the semiconductor substrate 13 may be provided in the slit SLT 1. For example, a contact plug or a groove-shaped conductor for connecting the source of the selection transistor ST2 to the source line may be provided. Further, the width of slit SLT1 in the Y direction is larger than the width of slit SLT2 in the Y direction.

Contact plugs 16 are provided on the memory pillars MP, and the wiring layer 15 functioning as the bit line BL is provided along the Y direction so as to be commonly connected to these contact plugs 16.

Fig. 6 is a cross-sectional view of the block BLK along the X direction, and shows, as an example, a cross-sectional structure of a region passing through the memory pillars MP5 and MP13 along the select gate line SGD3 in fig. 3. As illustrated in fig. 5, wiring layers 12, 11, and 10 are provided in this order above a semiconductor substrate 13. The memory cell unit is as described with reference to fig. 5.

In the 1 st connection part, the wiring layers 10 to 12 are drawn out in a step shape, for example. That is, when viewed in the XY plane, the end upper surfaces of the 7-layer wiring layer 10 and the wiring layer 12 are exposed at the 1 st connection portion. Then, a contact plug 17 is provided on the exposed region, and the contact plug 17 is connected to the metal wiring layer 18. The metal wiring layers 18 electrically connect wiring layers 10 to 12 functioning as even-numbered select gate lines SGD0, SGD2, SGD4, and SGD6, even-numbered word lines WLo, and even-numbered select gate lines SGSo to the row decoder 3.

On the other hand, in the 2 nd connection portion, the wiring layers 11 and 12 are drawn out in the same manner, for example, in a step shape. Further, contact plugs 19 are provided on the exposed regions of the wiring layers 11 and 12, and the contact plugs 19 are connected to the metal wiring layer 20. The metal wiring layers 20 electrically connect

wiring layers

11 and 12 functioning as odd-numbered select gate lines SGD1, SGD3, SGD5, and SGD7, odd-numbered word lines WLe, and odd-numbered select gate lines SGSe to the row decoder 3. The wiring layer 10 may be electrically connected to the row decoder 3 via the 2 nd connection unit instead of the 1 st connection unit, or may be connected via both the 1 st connection unit and the 2 nd connection unit.

< constructions of memory pillars and memory cell transistors >

Next, the structures of the memory cell transistor MT and the memory pillar MP will be described.

Example 1

First, example 1 will be described with reference to fig. 7 and 8. Fig. 7 is a cross-sectional view in the XY plane of the memory pillar MP, and fig. 8 is a cross-sectional view in the YZ plane, particularly illustrating a region where 2 memory cell transistors MT are provided. In example 1, an insulating film is used for the charge accumulation layer of the memory cell transistor MT.

As shown, the memory pillar MP includes an insulating layer 30, a semiconductor layer 31, and insulating layers 32 to 34 disposed along the Z direction. The insulating layer 30 is, for example, a silicon oxide film. The semiconductor layer 31 is provided so as to surround the insulating layer 30, and functions as a region where a channel of the memory cell transistor MT is formed. The semiconductor layer 31 is, for example, a polysilicon layer. The insulating layer 32 is provided so as to surround the periphery of the semiconductor layer 31, and functions as a gate insulating film of the memory cell transistor MT. The insulating layer 32 has a laminated structure of a silicon oxide film and a silicon nitride film, for example. The insulating layer 33 is provided so as to surround the semiconductor layer 31, and functions as a charge accumulating layer of the memory cell transistor MT. The insulating layer 33 is, for example, a silicon nitride film. The insulating layer 34 is provided so as to surround the periphery of the insulating layer 33, and functions as a barrier insulating film of the memory cell transistor MT. The insulating layer 34 is, for example, a silicon oxide film. The insulating layer 37 is embedded in the slit SLT2 except for the memory pillar MP portion. The insulating layer 37 is, for example, a silicon oxide film.

Further, for example, an AlO layer 35 is provided around the memory pillars MP having the above-described configuration. A shield metal layer (TiN film or the like) 36 is formed around the AlO layer 35, for example. The wiring layer 11 functioning as a word line WL is provided around the shield metal layer 36. The wiring layer 11 is made of, for example, tungsten.

According to the above configuration, 2 memory cell transistors MT are arranged along the Y direction in 1 memory column MP. The selection transistors ST1 and ST2 also have the same configuration.

Example 2

Next, example 2 will be described with reference to fig. 9 and 10. Fig. 9 is a cross-sectional view in the XY plane of the memory pillar MP, and fig. 10 is a cross-sectional view in the YZ plane, particularly illustrating a region where 2 memory cell transistors MT are provided. In example 2, a conductive film is used for a charge accumulation layer of the memory cell transistor MT.

As shown, the memory pillar MP includes insulating

layers

48 and 43, a semiconductor layer 40, an insulating layer 41, a conductive layer 42, and insulating layers 46a to 46c, which are provided along the Z direction. The insulating layer 48 is, for example, a silicon oxide film. The semiconductor layer 40 is provided so as to surround the periphery of the insulating layer 43-1. The semiconductor layer 40 is, for example, a polysilicon layer, functions as a region for forming a channel of the memory cell transistor MT, and is not separated between the memory cell transistors MT located in the same memory pillar MP as in the example of fig. 7. The insulating layer 41 is provided around the conductive layer 40 and functions as a gate insulating film of each memory cell transistor MT. That is, the insulating layer 41 is divided into 2 regions in the XY plane shown in fig. 9, and each of the regions functions as a gate insulating film of 2 memory cell transistors MT in the same memory pillar MP. The insulating layer 41 has a laminated structure of a silicon oxide film and a silicon nitride film, for example. The conductive layer 42 is provided around the insulating layer 41, and is separated into 2 regions along the Y direction by the insulating layer 43. The conductive layer 42 is, for example, a polysilicon layer, and the separated 2 regions function as charge accumulation layers of the 2 memory cell transistors MT, respectively. The insulating layer 43 is, for example, a silicon oxide film. Insulating

layers

46a, 46b, and 46c are sequentially provided around the conductive layer 42. The insulating

layers

46a and 46c are, for example, silicon oxide films, and the insulating layer 46b is, for example, a silicon nitride film, and these layers function as a barrier insulating film of the memory cell transistor MT. These insulating layers 46a to 46b are also separated into 2 regions along the Y direction, and the insulating layer 43 is provided therebetween. Further, the insulating layer 43 is buried in the slit SLT 2. The insulating layer 43 is, for example, a silicon oxide film.

Further, for example, an AlO layer 45 is provided around the memory pillars MP having the above-described configuration. Further, a shield metal layer (TiN film or the like) 47 is formed around the AlO layer 45, for example. The wiring layer 11 functioning as the word line WL is provided around the shield metal layer 47.

According to the above configuration, 2 memory cell transistors MT are arranged along the Y direction in 1 memory column MP. The selection transistors ST1 and ST2 also have the same configuration. Further, an insulating layer, not shown, is provided between memory cell transistors adjacent in the Z direction, and the charge accumulating layer 42 is insulated from each of the memory cell transistors by the insulating layer and the insulating layers 43 and 46.

About the equivalent circuit

Fig. 11 is an equivalent circuit diagram of the memory column MP having the above-described configuration. As shown, 2 NAND strings 50o and 50e are formed in 1 memory pillar MP. That is, the select transistor ST1 provided on the same memory pillar MP is connected to different select gate lines SGD, the memory cell transistor MT is connected to different word lines WLo and WLe, and the select transistor ST2 is also connected to different select gate lines SGSo and SGSe. The 2 NAND strings 50o and 50e in the same memory column MP are connected to the same bit line BL and the same source line SL. However, the current paths are electrically separated from each other.

1.2 read operation

Next, a method of reading data in the NAND flash memory having the above configuration will be described.

First, a state in which the select gate line SGD is selected will be described with reference to fig. 12 and 13. Fig. 12 and 13 are plan layout views of the selection gate lines SGD in the XY plane corresponding to fig. 3, which have been described above, and the wiring layers 10 corresponding to the selected selection gate lines SGD are indicated by oblique lines.

As shown in fig. 12, when any one of the selection gate lines SGD1 to SGD7 is selected, any one of the corresponding 1 wiring layers 10-1 to 10-7 is selected. Fig. 12 shows a case where the select gate line SGD1 is selected. By selecting the wiring layer 10-1, 4 memory cell transistors MT provided in the memory pillars MP0, MP4, MP8, and MP12 are selected. That is, 1 page is formed by 4 memory cell transistors MT belonging to the wiring layer 11-1 corresponding to any word line WL provided immediately below the wiring layer 10-1. The same applies to the case where the select gate lines SGD2 to SGD7 are selected.

In contrast, both wiring layers 10-0a and 10-0b at both ends within the block BLK are selected at the same time. This case corresponds to the case where the select gate line SGD0 is selected. This state is shown in fig. 13.

As shown, when the selection gate line SGD0 is selected, 2 memory cell transistors MT located right under the wiring layer 10-0a and disposed at the memory pillars MP4 and MP12 and 2 memory cell transistors MT located right under the wiring layer 10-0b and disposed at the memory pillars MP3 and MP11 are selected. That is, 1 page is formed by the 4 memory cell transistors MT.

Fig. 14 is a timing chart showing voltage changes of various wirings when the odd-numbered selection gate lines SGDo (that is, the odd-numbered memory groups MG) and the word lines WLo0 are selected.

As shown in the drawing, first, at time t1, a voltage VSG is applied to all the select gate lines SGD in the select block BLK, and the select transistor ST1 is turned on. Further, the voltage VREAD is applied to all word lines, and the memory cell transistor MT is turned on regardless of the stored data. Further, the voltage VSG is applied to all the selection gate lines SGS, and the selection transistor ST2 is turned on. Thus, in the select block BLK, all the NAND strings 50 are brought into an on state, and VSS (e.g., 0V) is transmitted to the channel.

Next, at time t3, the sense amplifier 4 precharges the bit line BL. At this time, the even bit lines BL0 and BL2 belonging to the group GR1 are precharged to the voltage VBL2, and the odd bit lines BL1 and BL3 belonging to the group GR2 are precharged to the voltage VBL1 larger than the voltage VBL 2.

Then, at time t4, a voltage VSG is applied to the selected select gate lines SGD and SGSo, a read voltage VCGRV is applied to the selected word line WLo0, a voltage VNEG is applied to the unselected word line WLe0, and the other unselected word lines WL1 to WL7 are applied. The voltage VCGRV is a voltage corresponding to the read level and is used to determine whether the stored data of the selected memory cell transistor MT is "0" or "1". The voltage VNEG is, for example, a negative voltage or 0V, and is a voltage for turning off the memory cell transistor MT.

As a result of the above, if the selected memory cell transistor MT is turned on, a current flows from the bit line BL to the source line SL, and if the selected memory cell transistor MT is turned off, no current flows. This makes it possible to determine the stored data of the selected memory cell transistor MT.

1.3 effects of the present embodiment

According to the present embodiment, variations in memory cell characteristics among the memory groups MG can be corrected, and the operational reliability of the semiconductor memory device can be improved. The present effect will be explained below.

In the semiconductor memory device according to this embodiment, as described with reference to fig. 3 and 4, 1 memory cell MP is provided so as to cross 2 select gate lines SGD and 2 word lines WL arranged in the XY plane. In addition, 2 memory cell transistors MT are disposed in the memory pillar MP and controlled by the 2 select gate lines SGD and the word lines WL.

In addition, in the present configuration, the positional relationship between the memory pillars MP and the corresponding 2 word lines WL (and the select gate lines SGD) may be deviated. More specifically, in fig. 3 and 4, when a certain memory pillar MP is focused, it is preferable that the center portion in the Y direction of the memory pillar MP be located at the center of the corresponding 2 word lines. This is because by configuring the memory pillars MP in this manner, the sizes of the 2 memory cell transistors MT controlled by the corresponding 2 word lines WL become equal.

However, if the position of the memory pillar MP is shifted, the sizes of the corresponding 2 memory cell transistors MT are different. For example, in the case of the examples of fig. 3 and 4, the memory pillars MP are shifted toward the wiring layer 10-0a side along the Y direction. As a result, when looking at the wiring layers 10-1 and 11-1 and the memory pillars MP0 and MP4, the memory pillar MP0 overlaps the wiring layers 10-1 and 11-1 by a distance d1, the memory pillar MP4 overlaps the wiring layers 10-1 and 11-1 by a distance d2, and there is a relationship of d1 > d 2. The same relationship also exists between the columns MP8 and MP 12.

That is, focusing on memory group MG1, the cell size of memory cell transistor MT connected to even bit line BLe is large, and the cell size of memory cell transistor MT connected to odd bit line BLo is small. The size of the cell size can also be said to be the size of the current driving capability of the memory cell transistor MT.

That is, as is clear from fig. 3, when the even-numbered select gate line SGDe is selected, the size of the memory cell transistor MT connected to the bit lines BL0 and BL2, that is, the memory cell transistor MT belonging to the group GR1 is small. On the other hand, the memory cell transistors MT connected to the bit lines BL1 and BL3, that is, the memory cell transistors belonging to the group GR2, are large in size.

In contrast, when the odd-numbered select gate line SGDo is selected, the size of the memory cell transistor MT connected to the bit lines BL0 and BL2, that is, the memory cell transistor MT belonging to the group GR1 is large. On the other hand, the memory cell transistors MT connected to the bit lines BL1 and BL3, that is, the memory cell transistors belonging to the group GR2, are small in size.

As described above, when the memory pillars MP are shifted in position, the memory cell transistors MT having different sizes are alternately arranged in the same page. Therefore, in the present embodiment, the sense amplifier 4 controls the precharge potential in the read operation in accordance with the size of the selected memory cell transistor MT.

More specifically, when the even-numbered select gate line SGDe, that is, the even-numbered memory group MGe is selected, the sense amplifier 4 applies a large precharge potential VBL1 to the bit line BL of the group GR1, and applies a small precharge potential VBL2 to the bit line BL of the group GR 2. On the other hand, when the odd-numbered select gate line SGDo, that is, the odd-numbered memory group MGo is selected, the sense amplifier 4 applies a small precharge potential VBL2 to the bit line BL of the group GR1, and applies a large precharge potential VBL1 to the bit line BL of the group GR 2.

As a result, the difference in current driving force due to the cell size of the memory cell transistor MT can be cancelled by the precharge potential, and the difference in cell current flowing to the bit line BL between bit lines during the read operation can be reduced. That is, a condition for sufficiently passing a large cell current is given to the memory cell transistor MT through which a cell current is less likely to flow, and a condition for suppressing a cell current is given to the memory cell transistor MT through which a cell current is more likely to flow. This can suppress the occurrence of misreading from the memory cell transistor MT through which a cell current is not easily passed, and can improve the operation reliability of the semiconductor memory device.

In the configuration of the present embodiment, as shown in fig. 3, the wiring layers 10-0a and 10-0b located at both ends of the block BLK are simultaneously selected and both function as the select gate line SGD 0. This is because 4 memory pillars MP (memory cell transistors MT) are formed in the other wiring layers 10-1 to 10-7, respectively, and only 2 memory pillars MP (memory cell transistors MT) are formed in the wiring layers 10-0a and 10-0b, respectively. Therefore, in both end portions of the block BLK, the 2 wiring layers 10-0a and 10-0b electrically function as 1 select gate line SGD, and thus even when the select gate line SGD0 is selected, the size of page 1 can be made the same as that when the other select gate lines SGD1 to SGD7 are selected.

As a result of matching the page sizes as described above, the number of wiring layers 10 functioning as the select gate lines SGD in the 1 block BLK becomes an odd number in the XY plane as shown in fig. 3. This case is also the same for the wiring layer 11 functioning as the word line WL as shown in fig. 4. In other words, the number of wiring layers located between the slits SLT1 becomes an odd number when viewed in the XY plane.

Note that the offset method of the memory column MP may be the reverse of that shown in fig. 3 and 4. Fig. 15 shows a state in this case. Fig. 15 shows a plan layout of the select gate lines SGD according to a variation of the present embodiment. As shown in the figure, in this example, the position of the memory pillars MP is shifted toward the wiring layer 10-0b side along the Y direction, contrary to the case of fig. 3. As a result, when the wiring layers 10-1 and 11-1 and the memory pillars MP0 and MP4 are looked at, the memory pillar MP0 overlaps the wiring layers 10-1 and 11-1 by a distance d2, and the memory pillar MP4 overlaps the wiring layers 10-1 and 11-1 by a distance d 1. In this case, the voltage applied to the bit line BL at the time of readout is opposite to that of the embodiment.

That is, when the even-numbered select gate line SGDe, that is, the even-numbered memory group MGe is selected, the sense amplifier 4 applies a small precharge potential VBL2 to the bit line BL of the group GR1, and applies a large precharge potential VBL1 to the bit line BL of the group GR 2. On the other hand, when the odd-numbered select gate line SGDo, that is, the odd-numbered memory group MGo is selected, the sense amplifier 4 applies a large precharge potential VBL1 to the bit line BL of the group GR1, and applies a small precharge potential VBL2 to the bit line BL of the group GR 2.

2. Embodiment 2

Next, the semiconductor memory device according to embodiment 2 will be described. The present embodiment relates to the write operation in embodiment 1. Hereinafter, only the differences from embodiment 1 will be described.

2.1 example 1

First, example 1 will be explained. The data writing action comprises: a programming operation of injecting electrons into the charge accumulating layer to change a threshold value; and a program verifying operation for verifying whether the threshold value, which is the result of the program operation, reaches a predetermined value. In example 1, in the program operation, the voltages applied to the bit line BL are different in the groups GR1 and GR 2.

Fig. 16 is a timing chart showing voltage changes of the various wirings when the odd-numbered selection gate lines SGDo (that is, the odd-numbered memory groups MG) and the word lines WLo0 are selected at the time of data writing.

As shown in fig. 12 and 13, when the odd-numbered select gate line SGDo is selected, the size of the memory cell transistor MT belonging to the group GR1(BL0, BL2) is large, and the size of the memory cell transistor MT belonging to the group GR2(BL1, BL3) is small. Since the larger the overlapping area of the word line WL and the memory pillar MP, the larger the coupling ratio, the faster the writing speed of the memory cell transistor MT. That is, the group GR1 writes faster, and the group GR2 writes slower.

Therefore, at time t2, the sense amplifier 4 applies a relatively high voltage VCH2 to the bit lines BL0 and BL2 belonging to the group GR1, and applies a low voltage VCH1 to the bit lines BL1 and BL3 belonging to the group GR 2. Of course, VCH2 > VCH 1.

Next, at time t3, the row decoder 3 applies the voltage VPASS to all the word lines WL0 to WL7, and further raises the voltage of the selected word line WLo0 from VPASS to VPGM at time t 5. The voltage VPASS is a voltage that turns on the memory cell transistor MT regardless of the held data and enables the channel potential to rise sufficiently by coupling in the non-selected NAND string 50. In addition, the voltage VPGM is a high voltage for injecting electrons into the charge accumulation layer by FN (Fowler-Nordheim ) tunneling, and VPGM > VPASS.

According to this method, the writing speed can be reduced by increasing the bit line voltage corresponding to the memory cell transistor MT having a high writing speed. This can reduce the difference in write speed between groups GR1 and GR 2.

2.2 example 2

Next, example 2 will be explained. In the example 2, the value of the voltage VPGM applied to the selected word line WL is changed in the groups GR1 and GR2 during the program operation.

Fig. 17 is a timing chart showing potential changes of the selected word line WL and the bit line BL in this example, and shows a case where the even-numbered memory group MG, that is, the even-numbered selected gate line SGDe is selected.

As described above, the write operations include a program operation and a program verify operation. This combination is called a programming cycle. In the write operation, the program loop is repeated a plurality of times to write 1 page worth of data.

In this example, 2 kinds of program voltages VPGM1 and VPGM2 are applied to the selected word line WL in the program operation, and VPGM2 > VPGM1 are in the relationship. When the even-numbered memory group MG is selected, the writing speed of the memory cell transistor MT belonging to the group GR1(BL0, BL2) is slow, and the writing speed of the memory cell transistor MT belonging to the group GR2(BL1, BL3) is fast. Thus, voltage VPGM1 is used as the programming voltage for group GR2 and voltage VPGM2 is used as the programming voltage for group GR 1.

Specifically, while the voltage VPGM1 is applied, the write inhibit voltage VBL is applied to the bit lines BL0 and BL2 of the group GR1, and the write voltage (for example, 0V, a voltage smaller than VBL) is applied to the bit lines BL1 and BL3 of the group GR 2. As a result, data is programmed to the memory cell transistor MT connected to the bit lines BL1 and BL 3.

On the other hand, while the voltage VPGM2 is applied, the write inhibit voltage VBL is applied to the bit lines BL1 and BL3 of the group GR2, and the write voltage VBL is applied to the bit lines BL0 and BL2 of the group GR 1. As a result, data is programmed to the memory cell transistor MT connected to the bit lines BL0 and BL 2.

According to the method, a high programming voltage is used for the memory cell transistor MT whose writing speed is slow, and a low programming voltage is used for the memory cell transistor MT whose writing speed is fast. This can reduce the difference in write speed between groups GR1 and GR 2. In addition, the boosting width Δ VPGM of the program voltage VPGM may also be changed in the groups GR1 and GR 2. Of course, Δ VPGM is set to be large in a group with a slow write speed.

2.3 example 3

Next, example 3 will be explained. In example 3, in the program verify operation, the cell current is relatively reduced by lowering the precharge potential to the group having a slow write speed. That is, the method of applying a voltage to the bit line BL is the same as that of fig. 14 described in embodiment 1.

According to this method, in a memory cell transistor with a low write speed, as a program cycle is repeated a plurality of times, the threshold value of the cell increases, and the cell current becomes less likely to flow, so that program verification is likely to pass. As a result, the difference in write speed between the groups GR1 and GR2 can be reduced.

2.4 effects of the present embodiment

According to the present embodiment, even in the case where the writing speeds are different among the memory cell transistors belonging to the same page, the number of programming cycles required for them to pass the program verification can be made the same. Therefore, the number of programming cycles can be reduced, and the purchase speed can be increased. Further, it is possible to suppress the memory cell transistor with a high write speed from rapidly passing the program verification and thereafter being subjected to disturbance or the like caused by the write operation to the memory cell transistor with a low write speed for a long time, and it is also possible to improve the reliability of the write operation.

3. Embodiment 3

Next, the semiconductor memory device according to embodiment 3 will be described. In this embodiment, 2 bit lines are provided in 1 memory column as an example, in a different plane layout from the above-described 1 st and 2 nd embodiments. Hereinafter, only the differences from

embodiments

1 and 2 will be described.

3.1 about the layout in plan

Fig. 18 and 19 show the plane layout of the select gate lines SGD in the XY plane of a certain block BLK. Fig. 18 corresponds to fig. 3 described in embodiment 1, and also shows the state of the bit line BL. In fig. 19, the illustration of the memory cell unit is simplified, and attention is particularly paid to the structures of the 1 st connection unit and the 2 nd connection unit. In this example, a case where 4 selection gate lines SGD are included in 1 block BLK will be described.

As shown in the drawing, in this example, 9 wiring layers 10 extending in the X direction are also included, similarly to the configuration described in fig. 3. However, in this example, the wiring layers 10-1 to 10-7 and 10-0b described in FIG. 3 are referred to as wiring layers 10-1a, 10-2a, 10-3a, 10-0b, 10-1b, 10-2b, 10-3b and 10-0c, respectively. The slit SLT2 is provided between the wiring layers 10 similarly to embodiment 1.

In block BLK, 2 wiring layers 10-0a and 10-0c located at both ends along the Y direction and wiring layer 10-0b located at the center function as select gate line SGD 0. As shown in fig. 19, the 3 wiring layers 10-0 are commonly connected to each other via, for example, a contact plug 49 and a metal wiring layer 51 in the 1 st connection portion, and further connected to the row decoder 3. The wiring layers 10-1a and 10-2b are connected in common to the 2 nd connection portion via the contact plug 52 and the metal wiring layer 53, and further connected to the row decoder 3. Further, the wiring layers 10-2a and 10-2b are connected in common via the contact plug 52 and the metal wiring layer 53 at the 2 nd connection portion, and further connected to the row decoder 3. The wiring layers 10-3a and 10-3b are connected in common to each other via the contact plug 49 and the metal wiring layer 51 at the 1 st connection portion, and further connected to the row decoder 3.

In addition, as shown in fig. 18, 2 bit lines BL pass over 1 memory pillar MP. Among the 2 bit lines BL, only one of the bit lines connected to the memory pillar MP is used.

That is, 2 bit lines BL0 and BL1 are provided above the memory pillars MP0 to MP 3. The bit line BL0 is commonly connected to the memory pillars MP1 and MP2, and the bit line BL1 is commonly connected to the memory pillars MP0 and MP 3. Further, 2 bit lines BL2 and BL3 are provided above the memory pillars MP4 to MP 7. The bit line BL2 is commonly connected to the memory pillars MP4 and MP5, and the bit line BL3 is commonly connected to the memory pillars MP6 and MP 7. Further, 2 bit lines BL4 and BL5 are provided above the memory pillars MP8 to MP 11. The bit line BL4 is commonly connected to the memory pillars MP9 and MP10, and the bit line BL5 is commonly connected to the memory pillars MP8 and MP 11. Further, 2 bit lines BL6 and BL7 are provided above the memory pillars MP12 to MP 15. The bit line BL6 is commonly connected to the memory pillars MP12 and MP13, and the bit line BL7 is commonly connected to the memory pillars MP14 and MP 15. Therefore, in this example, the bit lines BL0, BL1, BL4, and BL5, the memory pillars MP0 to MP3, and MP8 to MP11 belong to the group GR1, and the bit lines BL2, BL3, BL6, and BL7, the memory pillars MP4 to MP7, and MP12 to MP15 belong to the group GR 2.

The other structure is as described in embodiment 1.

3.2 Page selection method

Next, a method of selecting a page when reading and writing data will be described.

As described in the above 3.1, in this example, 2 or 3 wiring layers 10 are connected in common. Therefore, a plurality of wiring layers 10 commonly connected are simultaneously selected. Fig. 20 and 21 are plan layout views of the selection gate lines SGD in the XY plane corresponding to fig. 18 described above, and the wiring layers 10 corresponding to the selected selection gate lines SGD are indicated by hatching.

As shown in fig. 20, when any one of the selection gate lines SGD1 to SGD3 is selected, the corresponding 2 wiring layers 10 are selected. Fig. 20 shows a case where the select gate line SGD1 is selected. In this case, 8 memory cell transistors MT provided in the memory pillars MP0, MP4, MP8, and MP12 and the memory pillars MP2, MP6, MP10, and MP14 are selected by selecting 2 wiring layers 10-1a and 10-1 b. That is, 1 page is formed by 8 memory cell transistors MT belonging to the wiring layers 11-1a and 11-1b provided immediately below the wiring layers 10-1a and 10-1b corresponding to any one word line WL. This is the same for the case where the select gate lines SGD2 and SGD3 are selected.

On the other hand, when the select gate line SGD0 is selected, 3 wiring layers 10, i.e., the wiring layer 10-0b located at the center of the block BLK, are simultaneously selected in addition to the wiring layers 10-0a and 10-0c located at both ends in the block BLK, as shown in fig. 21. Thus, 2 memory cell transistors MT located right under the wiring layer 10-0a and provided in the memory pillars MP4 and MP12, 2 memory cell transistors MT located right under the wiring layer 10-0c and provided in the memory pillars MP3 and MP11, and 4 memory cell transistors MT located right under the wiring layer 10-0b and provided in the memory pillars MP1, MP6, MP9, and MP14 are selected. That is, 1 page is formed by the 8 memory cell transistors MT.

The data reading method and the data writing method are as described in

embodiments

1 and 2.

3.3 effects of the present embodiment

According to this embodiment, the size of 1 page can be increased by causing 2 or more wiring layers 10 to function as 1 selection gate line SGD. In addition, if the method of connecting the selection gate line SGD of this example is used, when a plurality of wiring layers 10 are selected, the effect of the inter-cell interference (including the influence of capacitance or resistance) on the memory cell transistors MT associated with each wiring layer can be made almost equal between the wiring layers.

For example, in FIG. 19, when the select gate line SGD2 is selected, the driving wiring layers 10-2a and 10-2b are driven. The wiring layers 10 adjacent to the wiring layer 10-2a in the Y direction are 10-1a and 10-3a functioning as the wiring layer SGD1 and the wiring layer SGD 3. The wiring layers 10 adjacent to the other wiring layer 10-2b selected at the same time in the Y direction are also wiring layers 10-1b and 10-3b functioning as the selection gate lines SGD1 and SGD 3. In this way, 1 select gate line SGD is separated into 2 lines in the memory cell unit, and the combination of select gate lines adjacent in the Y direction is common between the 2 lines thus separated. That is, the influence of the 2 wires obtained by separation from the adjacent wires is almost the same. This case is the same when any of the select gate lines SGD is selected. Therefore, variations in characteristics between the select gate lines SGD can be suppressed, and operation reliability can be improved.

Fig. 22 is a plan view of the selection gate line SGD in the XY plane according to a modification of the present embodiment. As shown in the figure, this example shows a case where the number of lines 10 in the 1 block BLK is set to 17. As shown in the figure, wiring layers 10-0a, 10-1a, 10-2a, 10-3a, 10-4a, 10-5a, 10-6a, 10-7a, 10-0b, 10-1b, 10-2b, 10-3b, 10-4b, 10-5b, 10-6b, 10-7b, and 10-0c are arranged in this order along the Y direction, for example. The wiring layers 10-0a and 10-0c located at both ends and the wiring layer 10-b located at the center function as a select gate line SGD 0. The wiring layers 10-1a and 10-1b function as a select gate line SGD1, and the wiring layers 10-2a and 10-2b function as a select gate line SGD2, which will be described below. Thus, the number of wiring layers 10 can be increased appropriately.

If the expression is generalized, it can be explained as in fig. 23. Fig. 23 is also a plan layout of the select gate lines SGD. As shown in the figure, (2n +1) wiring layers 10-1 to 10- (2n +1) are arranged along the Y direction. Wherein n is a natural number of 2 or more. The 1 st wiring layer 10-1, the central wiring layer 10- (n +1), and the last wiring layer 10- (2n +1) are connected in common. The i-th layer and the (i + n) -th layer are commonly connected to the remaining wiring layers 10. Wherein i is a natural number of 2 to n.

4. Embodiment 4

Next, the semiconductor memory device according to embodiment 4 will be described. The present embodiment is an example in which the wiring method of the wiring layer 10 functioning as the select gate line SGD is different from that of embodiment 3. Hereinafter, only the differences from embodiments 1 to 3 will be described.

4.1 about the planar layout

Fig. 24 is a plan layout of the select gate lines SGD in the XY plane of a certain block BLK, corresponding to fig. 19 described in embodiment 3. The bit line BL is not shown, but is the same as in embodiment 3.

As shown in the figure, in the layout of this example, 2 wiring layers 10-0a and 10-0c along the Y direction and 1 wiring layer 10-0b adjacent to the wiring layer 10-0a or 10-0c at both ends along the Y direction with 1 wiring layer 10 interposed therebetween are drawn out to the 1 st connection section and connected in common. The 3 wiring layers 10-0a, 10-0b, and 10-0c function as a select gate line SGD 0. The remaining wiring layers 10 are connected in common to each other at the connection portions by 2 adjacent in the Y direction with 1 wiring layer 10 interposed therebetween. That is, as shown in fig. 24, the wiring layers 10-1a and 10-1b are drawn to the 2 nd connection portion and commonly connected, and function as the selection gate line SGD 1. The wiring layers 10-2a and 10-2b are drawn out to the 1 st connection portion and commonly connected to each other, and function as the selection gate line SGD 2. The wiring layers 10-3a and 10-3b are drawn out to the 2 nd connection portion and commonly connected, and function as the selection gate line SGD 3.

In reading and writing, 2 or 3 wiring layers 10 commonly connected to the 1 st connection portion or the 2 nd connection portion are simultaneously driven.

4.2 Effect of the present embodiment

As described above, the method of connecting the select gate line SGD described in embodiment 3 may be the same as that of the present embodiment. Further, according to the present embodiment, since the plurality of wiring layers 10 do not intersect with each other, the plurality of wiring layers 10 can be commonly connected in the layers of the wiring layers 10. That is, it is not necessary to utilize other layers by contacting the plug and the metal wiring layer as in fig. 19. This can simplify the manufacturing method.

Fig. 25 is a plan layout of the selection gate lines SGD according to the variation of the present embodiment, and shows a case where the number of wiring layers 10 in the 1 block BLK is set to 17, as in fig. 22. As shown in the drawing, the 2 wiring layers 10 at both ends in the Y direction and the wiring layer 10 at the 3 rd layer counted from the end in the Y direction are drawn out to the 1 st connection portion and function as the selection gate line SGD 0. The other wiring layers are connected in common to the 1 st connection part or the 2 nd connection part in the 2 wiring layers 10 adjacent in the Y direction with one wiring layer 10 interposed therebetween, as in fig. 24.

FIG. 26 shows a state in which (2n +1) wiring layers 10-1 to 10- (2n +1) are arranged in the Y direction. Wherein n is a natural number of 2 or more. The 1 st wiring layer 10-1, the 3 rd wiring layer 10-3, and the last wiring layer 10- (2n +1) are connected in common. The remaining wiring layer 10 is connected in common to the (k +2) th layer. Wherein k is 2, 5, 6, 7, 10, … 10- (2 n-3) or 10- (2 n-2).

5. Examples of variations and the like

As described above, the semiconductor memory device according to the embodiment includes: a 1 st region (BLK in fig. 3) including a plurality of 1 st wires (SGD in fig. 3) arranged side by side along a 1 st direction (X direction in fig. 3) which is an in-plane direction of the semiconductor substrate, a 1 st insulating film (SLT2 in fig. 3) separating adjacent 1 st wires (SGD in fig. 3), and a 1 st column (MP in fig. 3) arranged so as to extend between the adjacent 1 st wires (SGD in fig. 3); and 2 nd and 3 rd regions (SLT1 in fig. 3) which are positioned so as to sandwich the 1 st region (BLK) in the 2 nd direction (Y direction in fig. 3) different from the 1 st direction in the in-plane direction of the semiconductor substrate, and which include the 2 nd insulating film provided from the semiconductor substrate up to the height of the 1 st wiring (SGD in fig. 3). The 1 st column (MP) includes a conductive layer, a gate insulating film, and a charge accumulating layer (fig. 7 to 10). The number of 1 st wirings (SGD) provided in the 1 st region (BLK in fig. 3) is an odd number (fig. 3).

According to the structure, the operation reliability of the semiconductor memory device can be improved. The embodiment described above is merely an example, and various changes can be made.

For example, although the above embodiment has been described with the case where 1 or 2 bit lines BL pass through the memory pillars MP, the number of bit lines BL may be 3 or 4, or 4 or more. The number of the select gate lines SGD is not limited to 9 or 17. Further, the configuration in which 2 NAND strings are provided in the memory column MP is not limited to the configuration described in embodiment 1. Such a structure is described, FOR example, in U.S. patent application No. 14/819,706 filed on 8/6/2015 under THE name "SEMICONDUCTOR MEMORY device DEVICE AND METHOD FOR MANUFACTURING THE SAME", which is incorporated herein by reference in its entirety.

In the above embodiment, the plane layout of the word lines WL is described with reference to fig. 4. However, the number of word lines WL included in the 1 block BLK can be appropriately selected, and the connection method of the word lines WL can also be appropriately selected. For example, as shown in fig. 27, the structure shown in fig. 4 may be configured such that 2 stages are arranged in the Y direction. In the present configuration, the slit SLT1 is provided not only at both ends of the 1 block BLK in the Y direction but also at the center of the block BLK. In the example of fig. 27, 4 word lines WL are commonly connected at the 1 st connection portion and the remaining 3 word lines WL are commonly connected at the 2 nd connection portion on the side across the slit SLT 1. On the other hand, 4 word lines WL are commonly connected at the 2 nd connection portion and the remaining 3 word lines WL are commonly connected at the 1 st connection portion on the other side across the slit SLT 1. The 2 groups of word lines WL with the slit SLT1 interposed therebetween are connected by the wiring layers 60 and 61. With this configuration, the number of word lines WL driven from the 1 st connection portion side (9 in fig. 27) can be made equal to the number of word lines WL driven from the 2 nd connection portion side.

Further, the selection transistor ST2 may have a 2-transistor structure, for example. Fig. 28 is an equivalent circuit diagram corresponding to 1 memory column MP. As shown, the selection transistor ST2 may also include 2 transistors ST2-1 and ST2-2 commonly connected. Fig. 29 is a sectional view of the selection transistor ST 2. As shown, the selection transistor ST2-1 is formed on the memory pillar MP, but the selection transistor 2-2 is formed on the p-type well region 13. That is, the gate insulating film 70 is formed on the well region 13, and the gate electrode 12 is provided on the gate insulating film 70. Further, an n-type impurity diffusion layer 71 functioning as a source region is provided in the well region 13. According to this configuration, a potential can be applied to the back gate of the transistor ST2-2 by the diffusion layer 71 or the like, for example.

In addition, in the embodiments related to the present invention,

(1) for example, the memory cell transistor MT can store 2-bit data, and has a threshold voltage of "Er", "a", "B", and "C" levels in order from low to high, and when the "Er" level is in an erase state, the voltage applied to the word line selected in the read operation of the "a" level is, for example, between 0V and 0.55V. The voltage is not limited to this, and may be in the range of 0.1V to 0.24V, 0.21V to 0.31V, 0.31V to 0.4V, 0.4V to 0.5V, or 0.5V to 0.55V.

The voltage applied to the selected word line in the "B" level read operation is, for example, 1.5V to 2.3V. The voltage is not limited to this, and may be in any range of 1.65V to 1.8V, 1.8V to 1.95V, 1.95V to 2.1V, and 2.1V to 2.3V.

The voltage applied to the selected word line in the "C" level read operation is, for example, 3.0V to 4.0V. The voltage is not limited to this, and may be set to any one of the ranges of 3.0V to 3.2V, 3.2V to 3.4V, 3.4V to 3.5V, 3.5V to 3.6V, and 3.6V to 4.0V.

The time (tR) for the read operation may be, for example, 25 μ s to 38 μ s, 38 μ s to 70 μ s, or 70 μ s to 80 μ s.

(2) The write operation includes a program operation and a verify operation. In the case of a write operation, the write operation,

the voltage initially applied to the selected word line in the programming operation is, for example, between 13.7V and 14.3V. The voltage is not limited to this, and may be set to any one of the ranges of 13.7V to 14.0V and 14.0V to 14.6V, for example.

The voltage initially applied to the selected word line when writing the odd-numbered word line and the voltage initially applied to the selected word line when writing the even-numbered word line may also be changed.

When the programming operation is an ISPP (Incremental Step Pulse programming) method, the boosted voltage may be, for example, about 0.5V.

The voltage applied to the unselected word line may be, for example, 6.0V to 7.3V. The voltage is not limited to this case, and may be, for example, 7.3V to 8.4V, or 6.0V or less.

The pass voltage to be applied may also be changed according to whether the non-selected word line is the odd-numbered word line or the even-numbered word line.

The time (tPROG) for the writing operation may be, for example, 1700. mu.s to 1800. mu.s, 1800. mu.s to 1900. mu.s, or 1900. mu.s to 2000. mu.s.

(3) In the deletion action, the deletion of the file is performed,

the voltage to be initially applied to the well formed above the semiconductor substrate and over which the memory cell is disposed is, for example, 12V to 13.6V. The voltage is not limited to this case, and may be, for example, 13.6V to 14.8V, 14.8V to 19.0V, 19.0 to 19.8V, or 19.8V to 21V.

The time for the erasing operation (tErase) may be, for example, 3000. mu.s to 4000. mu.s, 4000. mu.s to 5000. mu.s, or 4000. mu.s to 9000. mu.s.

(4) The memory cell is constructed by

Has a charge accumulation layer disposed on a semiconductor substrate (silicon substrate) with a tunnel insulating film having a thickness of 4 to 10nm interposed therebetween. The charge accumulation layer can be a laminated structure of an insulating film of SiN or SiON with a film thickness of 2-3 nm and a polysilicon with a film thickness of 3-8 nm. Further, a metal such as Ru may be added to the polycrystalline silicon. An insulating film is provided over the charge accumulating layer. The insulating film has, for example, a silicon oxide film having a thickness of 4 to 10nm sandwiched between a lower High-k film having a thickness of 3 to 10nm and an upper High-k film having a thickness of 3 to 10 nm. As the High-k film, HfO and the like can be mentioned. The silicon oxide film may have a thickness larger than that of the High-k film. A control electrode having a film thickness of 30 to 70nm is formed on an insulating film with a work function adjusting material having a film thickness of 3 to 10nm interposed therebetween. Here, the work function adjusting material is a metal oxide film such as TaO or a metal nitride film such as TaN. W or the like can be used as the control electrode.

In addition, an air gap can be formed between the memory cells.

Further, although the NAND flash memory is described as an example of the semiconductor memory device in the above embodiment, the present invention is not limited to the NAND flash memory, and can be applied to all other semiconductor memories, and can be applied to various memory devices other than the semiconductor memory.

Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

[ description of symbols ]

1 NAND type flash memory

2 memory cell array

3-line decoder

4 sense amplifier

10 to 12, 15, 18, 19 wiring layers

16. 17, 19 contact plug

30. 32-35, 41, 43, 45, 46 a-46 c insulation layer

31. 36, 40, 42, 47 conductive layer

50 NAND string

Claims

1. A semiconductor memory device is characterized by comprising:

a 1 st region including a plurality of 1 st wires provided over a semiconductor substrate and extending in a 1 st direction which is an in-plane direction of the semiconductor substrate, a 1 st insulating film separating adjacent 1 st wires, and a 1 st column provided so as to extend across adjacent 1 st wires; and

2 nd and 3 rd regions positioned so as to sandwich the 1 st region in a 2 nd direction different from the 1 st direction in an in-plane direction of the semiconductor substrate, and including a 2 nd insulating film provided from the semiconductor substrate to a height of the 1 st wiring; and is

The 1 st column includes a conductive layer, a gate insulating film, and a charge accumulating layer,

the number of the 1 st wires arranged in the 1 st region is odd;

21 st wirings located at both ends in the 2 nd direction among the 1 st wirings are electrically connected to each other.

2. The semiconductor memory device according to claim 1, wherein:

the 21 st wirings at the both ends are further electrically connected to each other with the 1 st wiring located at the center in the 2 nd direction among the odd-numbered 1 st wirings.

3. The semiconductor memory device according to claim 1, wherein:

the 21 st wirings at both ends are further electrically connected to the 1 st wiring located at the 2 nd direction from the 1 st wiring at one end to the 2 nd wiring.

4. The semiconductor memory device according to any one of claims 1 to 3, wherein:

in the 1 st column, a 1 st selection transistor and a 2 nd selection transistor using the adjacent 1 st wiring as respective gate electrodes are provided in a region spanning the adjacent 1 st wiring,

an area of the 1 st wiring facing the charge accumulating layer in the 1 st selection transistor and an area of the 1 st wiring facing the charge accumulating layer in the 2 nd selection transistor are different.

5. The semiconductor memory device according to claim 4, wherein:

the 1 st region further includes:

a 2 nd wiring line arranged in a plurality of lines in the 1 st direction above the semiconductor substrate and below the 1 st wiring line; and 1 st insulating film, separate the adjacent 2 nd interconnection; and is

The 1 st column is provided along a stacking direction of the 1 st wiring and the 2 nd wiring, and is provided so as to straddle the adjacent 2 nd wiring.

6. The semiconductor memory device according to claim 5, wherein:

in the 1 st pillar, a 1 st memory cell transistor and a 2 nd memory cell transistor using the adjacent 2 nd wiring as respective gate electrodes are provided in a region spanning the adjacent 2 nd wiring,

an area of the 2 nd wiring facing the charge accumulating layer in the 1 st memory cell transistor and an area of the 2 nd wiring facing the charge accumulating layer in the 2 nd memory cell transistor are different.

7. The semiconductor memory device according to claim 6, wherein:

the 2 nd area further includes a 2 nd column, the 2 nd column is arranged to cross between the adjacent 1 st wirings,

the semiconductor memory device further includes:

a 1 st bit line electrically connected to the 1 st column; and

a 2 nd bit line connected to the 2 nd pillar; and is

One of 2 adjacent 1 st wirings crossed by the 1 st column and one of 2 adjacent 1 st wirings crossed by the 2 nd column are common wirings, and the other is different wirings,

the precharge potentials of the 1 st bit line and the 2 nd bit line in the read operation are different.

8. The semiconductor memory device according to claim 7, wherein:

in the 2 nd column, a 3 rd selection transistor and a 4 th selection transistor using the adjacent 1 st wiring as respective gate electrodes are provided in a region spanning the adjacent 1 st wiring,

the 1 st select transistor and the 3 rd select transistor share a gate electrode,

an area of the 1 st wiring facing the charge accumulating layer in the 1 st selection transistor is larger than an area of the 1 st wiring facing the charge accumulating layer in the 2 nd selection transistor,

the precharge potential of the 1 st bit line is less than a precharge potential of the 2 nd bit line.