CN108666314A - Quasi- nonvolatile memory and preparation method thereof based on the controllable PN junction of two-dimensional material - Google Patents
Quasi- nonvolatile memory and preparation method thereof based on the controllable PN junction of two-dimensional material Download PDFInfo
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- CN108666314A CN108666314A CN201810310576.6A CN201810310576A CN108666314A CN 108666314 A CN108666314 A CN 108666314A CN 201810310576 A CN201810310576 A CN 201810310576A CN 108666314 A CN108666314 A CN 108666314A
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Abstract
The invention belongs to micro-nano electronic technology fields, the quasi- nonvolatile memory and preparation method thereof specially based on the controllable PN junction of two-dimensional material.It includes：One layer of two-dimensional material on an insulating substrate is as electric charge capture layer, the other two class two-dimensionals material shifted on capture layer, respectively as the areas N of PN junction and the tunnel layer of flash memory, in a kind of two-dimensional material of stacked on top, as the areas P of PN junction and the channel layer of flash memory.The present invention by energy band design enable device nanosecond rank be written and controllable charge retention time；The unlatching and closing of PN junction are controlled by applying grid voltage so that device can carry out ultrafast write-in when PN junction is opened；By the thickness and type and PN junction area and insulating layer area ratio of change composition two kinds of materials of PN junction, the regulatable ultrafast non-volatile novel memory devices part of standard of a kind of retention time can be obtained.Preparation process of the present invention is simple, can be prepared on a large scale by the material of CVD growth.
Description
Technical field
The invention belongs to micro-nano electronic technology fields, and in particular to a kind of standard based on the controllable PN junction of two-dimensional material is non-easily
The property lost memory and preparation method thereof.
Background technology
MOSFET is unit component most basic in integrated circuit, and the progress of technique makes the size of MOSFTE transistors continuous
It reduces simultaneously, power density is also constantly increasing；And another common device of integrated circuit is floating transistor, and floating boom is brilliant
It needs to be written and wiped in high pressure when body pipe works, leads to serious power problems.In order to reduce the power consumption of device and carry
The concept of the performance of high device, half floating boom memory technology is put forward for the first time 2013 by Fudan University.Half floating transistor is exactly will
One tunneling field-effect transistor and floating-gate device are combined together, and constitute a kind of completely new " half floating boom " structure devices.As
A kind of novel elemental device, it can be applied to different integrated circuits, such as replacement SRAM（Static RAM）When,
The SRAM that half floating transistor is constituted has the advantage of high density and low-power consumption；When applied to DRAM（Dynamic RAM）Neck
When domain, the DRAM that half floating transistor is constituted can realize traditional DRAM repertoires without capacitor, reduce the same of cost
When, integrated level higher, read or write speed is faster.
On the other hand, with the discovery of graphene, two-dimensional material causes the extensive attention of people.The surface of two-dimensional material without
Dangling bonds, can be stacked between any two class two-dimensionals material and the problem of without worrying lattice mismatch；Two-dimensional material thickness
Excellent electrology characteristic is still remain when two-dimensional material film thickness reduces to single layer when part in nanosecond rank, it can be effective
Improve electronic device integrated level；Two-dimensional material material category is extensive, including the property such as insulating properties, semiconductive, metallicity, superconductivity
Material, and different materials have opposed polarity.
So, compared to traditional half floating transistor of silicon substrate, how to be designed by regulating and controlling the band structure of two-dimensional material
Going out controllable novel quasi- nonvolatile memory just becomes a challenge.
Invention content
The content of present invention is designed to provide that a kind of standard based on the controllable PN junction of two-dimensional material is non-volatile novel to deposit
Reservoir and preparation method thereof.
Quasi- nonvolatile memory provided by the invention based on the controllable PN junction of two-dimensional material, including：
One insulator substrate；
First layer two-dimensional material film on insulator substrate, the first layer two-dimensional material film are semi-conducting material, as
Electric charge capture layer；
In the upper left second layer two-dimensional material film of first layer two-dimensional material film, which is N
Type semi-conducting material；
Third layer two-dimensional material film in the upper right side of first layer two-dimensional material film；The third layer two-dimensional material film is exhausted
Edge body material, as tunnel layer；
The 4th layer of two-dimensional material film on the second layer material and third layer two-dimensional material film, the 4th layer of two-dimensional material are thin
Film is p-type semiconductor material, as channel layer；The 4th layer of two-dimensional material and second layer two-dimensional material formation commutating ratio are excellent
PN junction；The 4th layer of two-dimensional material forms excellent flash memory with third layer two-dimensional material；
The metal electrode of certain figure on the 4th layer of two-dimensional material film.
In the present invention, insulator substrate is the highly doped substrate with oxide layer；The insulating layer material is selected from aluminium oxide
(Al2O3), hafnium oxide (HfO2) etc..The thickness of insulating layer is 20 nm-50 nm.
In the present invention, the first layer two-dimensional material film is vulcanization hafnium (HfS2), thickness 5-15nm.
In the present invention, the second layer two-dimensional material is selected from molybdenum sulfide (MoS2), artificial gold (SnS2), thickness is 5 nm-15
nm。
In the present invention, the third layer two-dimensional material selection boron nitride (hBN), thickness 10-20nm.
In the present invention, the 4th layer of two-dimensional material is selected from tungsten selenide (WSe2), black phosphorus (BP), thickness be 5 nm-15
nm。
The preparation method of the above-mentioned quasi- nonvolatile memory based on the controllable PN junction of two-dimensional material provided by the invention, tool
Steps are as follows for body：
（1）First layer two-dimensional material film is shifted on insulator substrate；
Preferably, the insulating layer material is selected from aluminium oxide (Al2O3), hafnium oxide (HfO2) etc.；
Preferably, the insulating layer material thickness is 20 nm-50 nm；
Preferably, the first layer two-dimensional material film is by mechanically pulling off or CVD growth obtains；
Preferably, the first layer two-dimensional material film generally vulcanizes hafnium (HfS2), thickness 5-15nm, for example, 10 nm,
Or its left and right.
（2）Second layer two-dimensional material film is shifted displaced one layer of two-dimensional material film upper left side；
Preferably, the second layer two-dimensional material selection molybdenum sulfide (MoS2), artificial gold (SnS2), thickness is 5 nm-15 nm.
（3）Third layer two-dimensional material film is shifted displaced one layer of two-dimensional material film upper right side；Third layer two dimension material
Material film has overlapping with second layer two-dimensional material film；
Preferably, the third layer two-dimensional material selection boron nitride (hBN), thickness 10-20nm, for example, 15 nm or its left side
It is right；
Preferably, the second layer two-dimensional material and the overlapping place of third layer two-dimensional material are no more than 1 um.
（4）On the second layer material and third layer two-dimensional material film that displaced, the 4th layer of two-dimensional material is finally shifted
Film；The 4th layer of two-dimensional material forms the excellent PN junction of commutating ratio with second layer two-dimensional material；Described 4th layer two-dimentional material
Material forms excellent flash memory with third layer two-dimensional material, first layer two-dimensional material；
Preferably, the 4th layer of two-dimensional material is selected from tungsten selenide (WSe2), black phosphorus (BP), thickness be 5 nm-15 nm.
（5）The metal electrode of certain figure is formed on sample on the 4th layer of two-dimensional material film；
Preferably, photoetching process, or deposit metal process can be used in the formation metal electrode method；
Preferably, the photoetching process uses e-beam lithography；
Preferably, the deposit metal process can use physical vapour deposition (PVD) or electron beam evaporation；
Preferably, the metal electrode material is selected from chromium, gold.
Effect of the present invention：
Regulatable PN junction is used based on the accurate non-volatile novel memory devices of two-dimensional material, instead of in traditional half floating transistor
Tunneling field-effect transistor part, the opening and closing of PN junction are regulated and controled to transporting to electronics by grid voltage,
The ultrafast write time of 15 nanoseconds and the charge retention time up to 10 s can be obtained.Two kind two of PN junction is constituted by change
Tieing up the thickness of material and the ratio of PN junction area and flash memory area, the charge retention time of memory can also be adjusted accordingly
Control, the device property demand of different field is met with this.It is doped compared to the local ion injection in traditional handicraft, base
It only needs the corresponding polar two-dimensional material of selection to be stacked in the accurate non-volatile novel memory devices of two-dimensional material, device is met with this
The energy band design requirement of part, simple for process, structure is changeable, and applicability is more extensive.
Description of the drawings
Fig. 1 is the schematic diagram shifted after first layer two-dimensional material.
Fig. 2 is the schematic diagram shifted after second layer two-dimensional material.
Fig. 3 is the schematic diagram shifted after third layer two-dimensional material.
Fig. 4 is the schematic diagram shifted after the 4th layer of two-dimensional material.
Fig. 5 is the schematic diagram deposited after metal electrode.
Fig. 6 is the schematic diagram for regulating and controlling PN junction approach (1).
Fig. 7 is the schematic diagram for regulating and controlling PN junction approach (2).
Fig. 8 is to prepare the flow chart based on controllable half floating transistor of PN junction of two-dimensional material.
Specific implementation mode
Above attached drawing only when some embodiments of the present invention do not paying for those of ordinary skill in the art
Under the premise of creative labor, other drawings may also be obtained based on these drawings.
It is detailed description of the present invention embodiment below.Examples of the embodiments are shown in the accompanying drawings, wherein from beginning extremely
Same or similar label indicates same or similar material or method with the same or similar functions eventually.Below with reference to
The embodiment of attached drawing description is exemplary, and is only used for explaining the present invention, and is not construed as limiting the claims.For letter
Change disclosure of the invention, hereinafter the material of specific examples and method are described.Certainly, they are merely examples, and
It is not intended to limit the present invention.In addition, the present invention provides various specific techniques and material example, but this field
Those of ordinary skill can be appreciated that the applicable property of other techniques and/or the use of other materials.
Hereinafter, the preparation method according to appended attached drawing for two-dimensional material film according to the present invention is illustrated
It is bright.
In fig. 1 it is shown that transfer first layer two-dimensional semiconductor material structure, including dielectric substrate 1001, as prisoner
Obtain the two-dimensional semiconductor material 1002 of layer；
In fig. 2 it is shown that the structure of transfer second layer two-dimensional semiconductor material, including dielectric substrate 1001, capture layer film
1002, the two-dimensional semiconductor material 1003 positioned at 1002 upper left side of film as the areas N in PN junction；
In fig. 3 it is shown that the structure of transfer third layer two-dimensional semiconductor material, including dielectric substrate 1001, capture layer film
1002, as the areas N film 1003 in PN junction, positioned at 1002 upper right side of film as the tunnel layer insulating layer of thin-film in flash memory
1004；
In fig. 4 it is shown that the structure of the 4th layer of two-dimensional semiconductor material of transfer, including dielectric substrate 1001, capture layer film
1002, as the areas N film 1003 in PN junction, as in flash memory insulating layer of thin-film 1004, positioned at the top be used as channel layer
Two-dimensional semiconductor material 1005；
In fig. 5 it is shown that the structural schematic diagram after metal has been deposited, including dielectric substrate 1001, the prisoner positioned at substrate
Obtain layer film 1002, as the areas N film 1003 in PN junction, the insulating layer of thin-film 1004 as in flash memory, channel layer thin film 1005,
Electrode 1006；
In fig. 6 it is shown that controllable PN junction approach 1；
In fig. 7 it is shown that controllable PN junction approach 2；
In fig. 8 it is shown that the flow diagram of material for transfer, deposit metal electrode, PN junction regulatory pathway.
The step of below according to manufacture based on two-dimensional material controllable half floating transistor of PN junction, in conjunction with Fig. 1 to 7, for
Specific an example is analyzed.
First, in step s 11, it will be by mechanically pulling off or the two-dimensional material film of CVD growth be transferred to insulation lining
Electric charge capture layer is used as on bottom.Dielectric substrate can be selected as aluminium oxide or hafnium oxide as insulating layer.As specific one
Example, as shown in Figure 1, selecting 23 nm aluminium oxide as dielectric substrate 1001 in the present embodiment, shifts a thickness on an insulating substrate
The vulcanization hafnium film 1002 that degree is 10 nm is used as electric charge capture layer.But the present invention is not limited thereto, can also use other linings
Bottom.
Then, in step s 12, the two-dimensional semiconductor material film of one floor N of transfer is as the areas N in PN junction to film
1002 upper left side.N thin-film materials can select molybdenum sulfide, artificial gold etc..As specific an example, as shown in Fig. 2, this reality
It applies and shifts one layer of 6 nm vulcanization molybdenum film 1003 in example on 1002 upper left side of capture layer film.
Then, in step s 13, one layer insulating two-dimensional material of transfer is in 1002 upper right side of capture layer film.As tool
An example of body, as shown in figure 3, shifting one layer of 14 nm boron nitride pellicle 1004 in the present embodiment in capture 1002 upper right of layer film
Side.And film 1003 and film 1004 overlap width should be within 1 um.
And then, in step S14, the two-dimensional semiconductor material film of one layer of P is shifted as channel layer to the top.
P material films can select tungsten selenide, black phosphorus etc..As specific an example, as shown in figure 4, shifting one layer in the present embodiment
10 nm selenizings W films 1005 are in the top.Transfer method based on two-dimensional material includes many kinds, and used herein is wet
Method shifts.
In step S15, by lithographic definition electrode pattern, and one layer of metal is deposited.In this example, pass through electron beam light
Then lithography is exposed, is developed, the photoresist containing electrode pattern is obtained on sample, is finally grown using electron beam evaporation
The metal of metal 1006, growth is 10 nm Cr and 70 nm Au, and complete device is obtained by stripping.In the design of electrode
Cheng Zhong, electrode are drawn in channel layer thin film 1005, can be passed through insulating layer 1004, but cannot be connect with film 1002,1003
It touches.
Finally in step s 16, regulation and control two kinds of different approaches of PN junction are shown.One is the materials constituted by adjusting PN junction
Expect type and thickness, such as molybdenum sulfide/tungsten selenide, molybdenum sulfide/black phosphorus, artificial gold/tungsten selenide etc., thickness between the two also may be used
To change successively from 5/5 nm to 4/6 nm, different compositions can form the PN junction of different performance, to regulate and control the holding of charge
Time；Another is to adjust PN junction area and insulating layer area ratio, from 0：10、5：5、10：0 changes successively, can be from pure
Flash memory changes to half FGS floating gate structure and pure PN junction, and in three's device is excessive, the charge retention time of memory can also obtain
To corresponding regulation and control.This is also based on the embodiment of controllable half floating transistor of PN junction of two-dimensional material.
Quasi- nonvolatile memory provided by the invention based on the controllable PN junction of two-dimensional material, utilizes two-dimensional material PN junction
The tunneling transistor in traditional half floating transistor is substituted, transporting for electronics is controlled.It is floating based on made of two-dimensional material stacking half
Grid structure advantage is that device can also obtain controllable charge storage time while ultrafast write-in.It can be constituted by adjusting
The type and thickness and PN junction area and insulating layer area ratio of the two-dimensional material of PN junction, the charge storage time of device also can
Different degrees of regulation and control are obtained, it is from several seconds to tens second or even longer.Compared to traditional half floating transistor, it is based on two-dimensional material
The preparation process of half floating transistor of controllable PN junction is simpler, and storage performance more easy-regulating, meets different necks with this
Domain demand, such as information security field.
Although present invention preferred embodiment discloses as above, however, it is not intended to limit the invention.So and it is familiar with this field
Technical staff, without departing from the scope of the technical proposal of the invention, all using the methods and technical content of the disclosure above
Many possible changes and modifications are made to technical solution of the present invention, or are revised as the equivalent embodiment of equivalent variations.Therefore, all
Be without departing from technical solution of the present invention content, it is made to the above embodiment according to the technical essence of the invention any simply to repair
Change, equivalent variations and modification, belongs in the range of technical solution of the present invention protection.
Claims (10)
1. a kind of quasi- nonvolatile memory based on the controllable PN junction of two-dimensional material, which is characterized in that including：
One insulator substrate；
First layer two-dimensional material film on insulator substrate, the first layer two-dimensional material film are semi-conducting material, as
Electric charge capture layer；
In the upper left second layer two-dimensional material film of first layer two-dimensional material film, which is N
Type semi-conducting material；
Third layer two-dimensional material film in the upper right side of first layer two-dimensional material film；The third layer two-dimensional material film is exhausted
Edge body material, as tunnel layer；
The 4th layer of two-dimensional material film on the second layer material and third layer two-dimensional material film, the 4th layer of two-dimensional material are thin
Film is p-type semiconductor material, as channel layer；The 4th layer of two-dimensional material and second layer two-dimensional material formation commutating ratio are excellent
PN junction；The 4th layer of two-dimensional material forms excellent flash memory with third layer two-dimensional material；
The metal electrode of certain figure on the 4th layer of two-dimensional material film.
2. quasi- nonvolatile memory according to claim 1, which is characterized in that the insulator substrate is with oxidation
The highly doped substrate of layer；Insulating layer material is selected from aluminium oxide, hafnium oxide；The thickness of insulating layer is 20 nm-50 nm.
3. quasi- nonvolatile memory according to claim 1 or 2, which is characterized in that the first layer two-dimensional material is thin
Film is vulcanization hafnium, thickness 5-15nm.
4. quasi- nonvolatile memory according to claim 3, which is characterized in that the second layer two-dimensional material is selected from sulphur
Change molybdenum, artificial gold, thickness is 5nm-15 nm.
5. quasi- nonvolatile memory according to claim 1,2 or 4, which is characterized in that the third layer two-dimensional material
Select boron nitride, thickness 10-20nm.
6. quasi- nonvolatile memory according to claim 5, which is characterized in that the 4th layer of two-dimensional material is selected from selenium
Change tungsten, black phosphorus, thickness is 5 nm-15 nm.
7. a kind of quasi- nonvolatile memory as described in one of claim 1-6, which is characterized in that be as follows：
（1）First layer two-dimensional material film is shifted on insulator substrate；
（2）Second layer two-dimensional material film is shifted displaced one layer of two-dimensional material film upper left side；
（3）Third layer two-dimensional material film is shifted displaced one layer of two-dimensional material film upper right side；Third layer two-dimensional material is thin
Film has overlapping with second layer two-dimensional material film；
（4）On the second layer material and third layer two-dimensional material film that displaced, the 4th layer of two-dimensional material film is finally shifted；
The 4th layer of two-dimensional material forms PN junction with second layer two-dimensional material；The 4th layer of two-dimensional material and third layer two dimension material
Material, first layer two-dimensional material form flash memory；
（5）The metal electrode of certain figure is formed on sample on the 4th layer of two-dimensional material film.
8. preparation method according to claim 7, which is characterized in that the first layer two-dimensional material film is shelled by machinery
From or CVD growth obtain.
9. preparation method according to claim 7, which is characterized in that the second layer two-dimensional material and third layer two dimension material
The overlapping place of material is no more than 1um.
10. preparation method according to claim 7, which is characterized in that the metal electrode material is selected from chromium, gold.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109887921A (en) * | 2019-01-16 | 2019-06-14 | 复旦大学 | It is a kind of that grid memory and preparation method thereof is enclosed based on two-dimensional semiconductor material |
| CN111446254A (en) * | 2020-03-12 | 2020-07-24 | 复旦大学 | Semi-floating gate memory based on metal oxide semiconductor and preparation method thereof |
| CN111463212A (en) * | 2020-03-12 | 2020-07-28 | 复旦大学 | Quick erasable floating gate memory and preparation method thereof |
| CN111540745A (en) * | 2020-05-13 | 2020-08-14 | 复旦大学 | Low-power-consumption two-dimensional material semi-floating gate memory and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103972238A (en) * | 2014-03-31 | 2014-08-06 | 上海新储集成电路有限公司 | Memory unit structure |
| CN104167450A (en) * | 2014-08-17 | 2014-11-26 | 复旦大学 | Semi-floating-gate power device |
| CN106952921A (en) * | 2017-03-10 | 2017-07-14 | 同济大学 | A kind of method for designing of Nonvolatile programmable optoelectronic memory |
| CN107665894A (en) * | 2017-09-12 | 2018-02-06 | 复旦大学 | Half floating-gate memory based on two-dimensional semiconductor material and preparation method thereof |
-
2018
- 2018-04-09 CN CN201810310576.6A patent/CN108666314A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103972238A (en) * | 2014-03-31 | 2014-08-06 | 上海新储集成电路有限公司 | Memory unit structure |
| CN104167450A (en) * | 2014-08-17 | 2014-11-26 | 复旦大学 | Semi-floating-gate power device |
| CN106952921A (en) * | 2017-03-10 | 2017-07-14 | 同济大学 | A kind of method for designing of Nonvolatile programmable optoelectronic memory |
| CN107665894A (en) * | 2017-09-12 | 2018-02-06 | 复旦大学 | Half floating-gate memory based on two-dimensional semiconductor material and preparation method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109887921A (en) * | 2019-01-16 | 2019-06-14 | 复旦大学 | It is a kind of that grid memory and preparation method thereof is enclosed based on two-dimensional semiconductor material |
| CN111446254A (en) * | 2020-03-12 | 2020-07-24 | 复旦大学 | Semi-floating gate memory based on metal oxide semiconductor and preparation method thereof |
| CN111463212A (en) * | 2020-03-12 | 2020-07-28 | 复旦大学 | Quick erasable floating gate memory and preparation method thereof |
| CN111463212B (en) * | 2020-03-12 | 2022-06-21 | 复旦大学 | Quick erasable floating gate memory and preparation method thereof |
| CN111540745A (en) * | 2020-05-13 | 2020-08-14 | 复旦大学 | Low-power-consumption two-dimensional material semi-floating gate memory and preparation method thereof |
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Application publication date: 20181016 |