CN108649939B - Power supply detection circuit and method - Google Patents
Power supply detection circuit and method Download PDFInfo
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- CN108649939B CN108649939B CN201810339445.0A CN201810339445A CN108649939B CN 108649939 B CN108649939 B CN 108649939B CN 201810339445 A CN201810339445 A CN 201810339445A CN 108649939 B CN108649939 B CN 108649939B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract
The invention provides a power supply detection circuit and a method, comprising the following steps: the power switch module is switched on or off according to the power-on or power-off condition; a voltage division sampling module for sampling the power supply voltage; a voltage comparison module for performing power-on detection; a power failure detection module for performing power failure detection; and the pulse latch module latches the rising edge of the voltage transmitted by the voltage comparison module and the low level transmitted by the power failure detection module. Switching on the power supply voltage, carrying out voltage division sampling on the power supply voltage, and carrying out power-on detection on the basis of a signal obtained by the voltage division sampling; performing power failure detection on the power supply voltage; if the power-on is finished, outputting a first logic level, and performing delay output to ensure that the system works stably; and if the power is down, outputting a second logic level. The invention has the power failure detection function, has zero power consumption after power-on, and has detection precision far higher than that of the prior art.
Description
Technical Field
The invention relates to the field of analog integrated circuits, in particular to a power supply detection circuit and a power supply detection method.
Background
In an integrated circuit system, digital circuits, such as a control unit and a register, located on a chip are in an uncertain state when undergoing a power-on process. Therefore, a circuit is needed to perform initialization reset on the uncertain states, so as to ensure that the whole system of the chip can work normally. Typically, we use a Power-on-Reset (POR) circuit to accomplish this function: before the power supply voltage is at a voltage threshold value for the digital circuit to normally work, the setting signal of the POR enables the digital circuit to be in a fixed initialization state; after the power supply voltage rises to the threshold voltage, the set signal of the POR is released, and the digital circuit can work normally.
A reliable power-on-reset (POR) circuit needs to meet the following requirements: 1) the function of POR generating reset signal should not be limited by the power-on rate of normal power supply; 2) POR should not generate any power consumption after the set function is finished to meet the application requirements of low power consumption mode of some systems (e.g. low power consumption mode in portable, battery-powered IC chips); 3) when the POR (process, voltage and temperature) changes, the detected threshold voltage still needs to keep high precision, so that the occurrence of the situation that the POR is reset by mistake or cannot be reset under some conditions is avoided; 4) the POR can release the reset signal after waiting for the power supply to be powered on to a proper range (for example, a clock oscillator needs to wait for a period of time before outputting a stable clock signal for the system to normally work), namely the POR needs to have a certain delay function after reaching the threshold voltage of the power supply; 5) when the power voltage drops below a certain threshold, the POR should Reset the chip in time to avoid the system runaway, i.e. should have a BOR (Brown-out-Reset) function.
As shown in fig. 1, a conventional POR circuit 1 integrated on a chip is composed of a charge and discharge circuit 11 and a hysteresis circuit 12, wherein the charge and discharge circuit 11 includes a resistor R 'and a capacitor C' connected in series, and a connection node of the resistor R 'and the capacitor C' is used as an output terminal; the hysteresis circuit 12 includes PMOS transistors PM1 ', PM 2', PM3 ', NMOS transistors NM 1', NM2 ', NM 3' connected as a schmitt trigger structure. Although the static power consumption of the circuit is very small after the power supply voltage VDD is stabilized, the detection voltage is affected by the threshold voltages of PMOS and NMOS in the hysteresis circuit, and considerable deviation is generated due to the process and the temperature; in addition, the detection voltage varies with different power-up rates of the power supply voltage VDD. This can be understood from the circuit principle: the RC charge-discharge circuit generates time delay, so that the power supply voltage VDD is delayed to rise to a certain fixed moment, the output voltage of the RC circuit, namely the input voltage of the hysteresis circuit, and the power supply voltage VDD generate a difference value delta V, the pull-down capacity and the pull-up capacity of an NMOS (N-channel metal oxide semiconductor) and a PMOS (P-channel metal oxide semiconductor) in the hysteresis circuit are respectively influenced, finally, the turnover threshold value of the hysteresis circuit is reached, and the circuit outputs a reset signal. From this, it can be seen that: different RC charge-discharge circuit delay time is generated at different rising rates of the power supply voltage VDD, so that different difference values delta V between the input voltage of the hysteresis circuit and the power supply voltage VDD are generated, and different turnover threshold values are finally generated. Moreover, the POR circuit of this structure cannot detect the power down voltage.
As shown in fig. 2, another mainstream POR circuit 2 is composed of a bandgap reference circuit 21 and a voltage comparator 22, where the bandgap reference circuit 21 is connected between a power supply VDD and a ground GND and outputs a bandgap reference voltage Vref; the non-inverting input terminal of the voltage comparator 22 receives the bandgap reference voltage Vref, and the inverting input terminal receives the divided voltage Vdiv of the resistors R1 'and R2', and outputs a comparison result after comparison. The detection voltage is very accurate and is slightly influenced by the process and the temperature, but the circuit structure is more complex, the power consumption is larger, and the method is not suitable for the application requirement of low power consumption.
As shown in fig. 3, there is also a POR circuit 3 with power down detection (BOR) (reference: s.k.wadhwa, g.k.siddhartha, a.gaura.zero step state current power-on-reset circuit with browse-out detector [ C ]. proceedings of the 19th International Conference on VLSI Design, jan.2006: 1-6). The power-down reset circuit mainly comprises a PMOS transistor PM1 used as a MOS switch, a voltage division circuit consisting of two resistors R1 'and R2', two logic inverters INV1 'and INV 2', a pulse latch circuit 31 and a power-down reset detection circuit 32. The resistors R1 ″ and R2 ″ are used for dividing the sampled power voltage VDD, inputting the sampled voltage into the logic inverter INV1 ", determining the power-on detection threshold voltage of POR by using the inversion threshold of the inverter, once the power is powered on to the power-on detection threshold, pulling down the output of the logic inverter INV 1", and outputting a high level to the pulse latch circuit 31 after inverting through the logic inverter INV2 ". The pulse latch circuit 31 latches the high level signal and outputs the high level signal, and one is used for controlling the PMOS transistor PM1 ' which is used for manufacturing the MOS switch to be switched off, so that the voltage division circuit formed by the two resistors R1 ' and R2 ' does not consume static power consumption; and the second time is used as an output signal of the POR circuit, and represents the end of power-on reset of the POR. The power-down reset detection circuit 32 detects a power-down threshold value when the power supply is powered down, and after the power supply voltage is lower than the power-down threshold value voltage, the power-down reset detection circuit 32 outputs a low level to the pulse latch circuit 31, and the pulse latch circuit 31 latches a low level signal and outputs the low level to the output end of the POR circuit. The power down reset detect circuit 32 consumes no static power after the power supply voltage is powered up to a stable level. Although the static power consumption of the circuit with the structure is extremely low, the structure has a remarkable defect that: the power supply voltage VDD is divided by the resistors R1 ″ and R2 ″ to obtain a voltage, which is input to the logic inverter, and the rising detection voltage is further determined by the inversion point of the inverter, so that the detection voltage is very susceptible to the power supply voltage, the process, and the temperature.
Therefore, it is imperative to overcome the disadvantages of the conventional POR circuit and provide a high-precision power supply detection circuit with low power consumption, even static zero power consumption, and power down detection function.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a power detection circuit and method for solving the problems of low detection accuracy, no power failure detection function, large power consumption, etc. of a power-on reset circuit in the prior art.
To achieve the above and other related objects, the present invention provides a power detection circuit, comprising:
the power supply circuit comprises a power switch module, a partial pressure sampling module, a voltage comparison module, a power failure detection module, a time delay module and a pulse latch module;
the power switch module is connected with a power voltage, the partial pressure sampling module and the voltage comparison module, is controlled by the output signal of the pulse latch module, and is switched on when the power voltage is powered on or after the power failure; when the power supply voltage is electrified, the power supply switch module is turned off;
the voltage division sampling module is connected with the output end of the power switch module and is used for carrying out voltage division sampling on the voltage output by the power switch module;
The voltage comparison module is connected with the output ends of the power switch module and the partial pressure sampling module and is used for comparing the power voltage with a power-on detection threshold voltage so as to judge whether the power voltage is powered on;
the power failure detection module compares the power supply voltage with a power failure detection threshold voltage to judge whether the power supply voltage has power failure;
the pulse latch module is connected with the output ends of the voltage comparison module and the power failure detection module, and latches the high level of the output signal of the voltage comparison module after the power supply voltage is electrified; and when the power supply voltage is powered down, latching the low level output by the power down detection module.
Preferably, the voltage comparison module includes a comparator, a buffer unit and a transmission gate, and the comparator receives the output signal of the voltage division sampling module and determines whether the power supply voltage is powered up; the buffer unit is connected with the output end of the comparator and used for amplifying and shaping the output signal of the comparator into a corresponding logic high level or logic low level; the transmission gate is connected with the output end of the buffer unit and is used for outputting the output signal of the buffer unit.
More preferably, the comparator includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first resistor, and a second resistor;
the source electrodes of the first PMOS transistor and the second PMOS transistor are connected with the output end of the power switch module; the grid and the drain of the first PMOS transistor are connected with the grid of the second PMOS transistor; the drain electrode of the first NMOS transistor is connected with the drain electrode of the first PMOS transistor, the grid electrode of the first NMOS transistor is connected with the grid electrode of the second NMOS transistor, and the source electrode of the first NMOS transistor is connected with the first end of the second resistor; the drain electrode of the second NMOS transistor is connected with the drain electrode of the second PMOS transistor, and the source electrode of the second NMOS transistor is connected with the first end of the second resistor after passing through the first resistor; and the second end of the second resistor is grounded.
More preferably, a power terminal of the buffer unit is connected to the output signal of the power switch module.
Preferably, the power failure detection module includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a first charge-discharge capacitor;
the source electrode of the third PMOS transistor is connected with the power supply voltage; the grid electrode of the third PMOS transistor is connected with the drain electrode of the third PMOS transistor, and is connected with the source electrode of the fourth PMOS transistor, the source electrode of the fifth PMOS transistor and the first charge-discharge capacitor; the grid electrode of the fifth PMOS transistor and the grid electrode of the third NMOS transistor are connected with the power supply voltage; the drain electrode of the fifth PMOS transistor is connected with the drain electrode of the third NMOS transistor and is connected with the grid electrode of the fourth NMOS transistor and the grid electrode of the fifth NMOS transistor; the drain electrode of the fourth NMOS transistor is used as a first pull-down output end; the drain electrode of the fifth NMOS transistor is used as a second pull-down output end; and the drain electrode of the fourth PMOS transistor is used as a pull-up output end.
More preferably, the first charge-discharge capacitor is a sixth NMOS transistor, a gate of the sixth NMOS transistor is connected to a drain of the fourth NMOS transistor, and a source and a drain of the sixth NMOS transistor are grounded.
Preferably, the pulse latch module comprises a sixth PMOS transistor, a seventh NMOS transistor, a first capacitor, a first inverter, a second inverter, a third inverter, a fourth inverter, and a latch loop;
the source electrode of the sixth PMOS transistor is connected with the output end of the voltage comparison module, and the grid electrode of the sixth PMOS transistor is connected with the output end of the third inverter; the drain electrode of the sixth PMOS transistor is connected with the input end of the fourth inverter and the source electrode of the seventh NMOS transistor; the output end of the fourth inverter is connected with the input end of the first inverter, the input end of the latch loop and the second end of the first capacitor; the first end of the first capacitor is connected with the power supply voltage; the output end of the first phase inverter is connected with the input end of the second phase inverter; the output end of the second inverter is connected with the input end of the third inverter; the grid electrode of the seventh NMOS transistor is connected with the output end of the latch loop circuit, and the drain electrode of the seventh NMOS transistor is connected with the power supply voltage; and the output end of the latch loop is used as the output end of the pulse latch module.
More preferably, the pulse latch module further includes a second capacitor, a first end of the second capacitor is connected to the drain of the sixth PMOS transistor, and a second end of the second capacitor is grounded.
More preferably, the substrate of the sixth PMOS transistor is connected to the source.
More preferably, a power supply terminal of the fourth inverter is connected to the output signal of the power switching module.
Preferably, the power detection circuit further comprises a first output stage buffer module connected to the output end of the pulse latch module.
Preferably, the power detection circuit further includes a delay module, where the delay module receives the output signal of the pulse latch module, and delays the signal output by the pulse latch module after power-on is completed, so as to ensure stable operation of the system.
Preferably, the delay module includes an SR latch, an RC delay unit, a comparison unit, a fifth inverter, a sixth inverter, an and gate, and a seventh inverter;
the reset end of the SR latch and the first output end of the AND gate receive the output signal of the pulse latch module; the second input end of the AND gate is connected with the inverted output end of the SR latch and the input end of the sixth inverter; the output end of the sixth inverter is used as the output end of the delay module; the output end of the AND gate is connected with the input end of the seventh inverter and outputs a first delay control signal; the output end of the seventh inverter outputs a second delay control signal; the RC time delay unit receives the first time delay control signal and the second time delay control signal and carries out charging and discharging according to the first time delay control signal and the second time delay control signal; the comparison unit is connected to the output end of the RC delay unit and used for comparing the charging voltage with the discharging voltage so as to determine the delay time; the fifth inverter receives the output signal of the comparison unit, and the output end of the fifth inverter is connected with the set end of the SR latch and is used for adjusting the output signal of the SR latch according to the delay time.
More preferably, the RC delay unit includes a voltage-dividing subunit and a charge-discharge subunit, and the voltage-dividing subunit receives the output signal of the seventh inverter and provides a bias voltage for the charge-discharge subunit; the charge-discharge electronic unit receives an output signal of the AND gate and is used for determining delay time through discharging; the voltage divider subunit comprises a seventh PMOS transistor, a third resistor and an eighth NMOS transistor, wherein the source electrode of the seventh PMOS transistor is connected with the power supply voltage, the grid electrode of the seventh PMOS transistor receives the output signal of the seventh inverter, the drain electrode of the seventh PMOS transistor is connected with the first end of the third resistor, the second end of the third resistor is connected with the drain electrode and the grid electrode of the eighth NMOS transistor and serves as the first output end of the RC delay unit, and the source electrode of the eighth NMOS transistor is grounded; the charge and discharge electronic unit comprises an eighth PMOS transistor, a ninth NMOS transistor and a second charge and discharge capacitor, wherein the source electrode of the eighth PMOS transistor is connected with the power voltage, the drain electrode of the eighth PMOS transistor is connected with one end of the second charge and discharge capacitor and serves as a second output end of the RC delay unit, the other end of the second charge and discharge capacitor is grounded, the drain electrode of the ninth NMOS transistor is connected with the drain electrode of the eighth PMOS transistor, the grid electrode of the ninth NMOS transistor is connected with the grid electrode of the eighth NMOS transistor, and the source electrode of the ninth NMOS transistor is grounded.
Preferably, the comparison unit includes a tenth NMOS transistor, an eleventh NMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor, where the tenth NMOS transistor and the eleventh NMOS transistor are used as input pair transistors, and the ninth PMOS transistor and the tenth PMOS transistor are used as current mirrors; the grid electrode of the tenth NMOS transistor is connected with the second output end of the RC delay unit, the drain electrode of the tenth NMOS transistor is connected with the drain electrode of the ninth PMOS transistor and serves as the output end of the comparison unit, and the source electrode of the tenth NMOS transistor is grounded; the grid electrode of the ninth PMOS transistor is connected with the grid electrode and the drain electrode of the tenth PMOS transistor and is connected with the drain electrode of the eleventh NMOS transistor, and the source electrode of the ninth PMOS transistor is connected with the power supply voltage; the source electrode of the tenth PMOS transistor is connected with the power supply voltage; the grid electrode of the eleventh NMOS transistor is connected with the first output end of the RC delay unit, and the source electrode of the eleventh NMOS transistor is grounded; the comparison unit compares the output result of the RC delay unit, and when the level of a second output end of the RC delay unit is higher than the level of a first output end, the output of the comparison unit is low level; when the level of the second output end of the RC delay unit is lower than that of the first output end, the output of the comparison unit is high level.
In order to achieve the above and other related objects, the present invention further provides a power detection method, which at least includes:
switching on a power supply voltage, carrying out partial pressure sampling on the power supply voltage, and carrying out power-on detection on the power supply voltage based on a signal obtained by the partial pressure sampling; performing power failure detection on the power supply voltage;
if the power supply voltage is greater than the power-on detection threshold voltage, outputting a first logic level, and performing delay output on the first logic level to ensure that the system works stably;
if the power supply voltage is less than the power failure detection threshold voltage, outputting a second logic level, and not performing delay output on the second logic level;
wherein the power-up detection threshold voltage is greater than the power-down detection threshold voltage.
Preferably, the method for detecting power-on of the power supply voltage includes:
the input geminate transistors convert signals obtained by partial pressure sampling and the source electrode voltage difference of the input geminate transistors into first current and second current respectively based on the source electrode voltage difference of the input geminate transistors, the first current and the second current are compared through a current mirror, corresponding voltage is output, and logic level is output after the corresponding voltage is amplified and shaped.
More preferably, the power-on detection threshold voltage is set to be a zero temperature coefficient voltage by adjusting the ratio between the input pair of transistors and the ratio between the resistors respectively connected to the source electrodes of the input pair of transistors.
More preferably, the value of the power-on detection threshold voltage is determined by adjusting the size of the input pair transistor, the ratio between the resistances respectively connected to the source electrodes of the input pair transistor, the size of the current mirror, and the size of the power supply voltage sampling resistance.
Preferably, after the power supply voltage is greater than the power-on detection threshold voltage, the power-on detection is not performed any more, so as to reduce static power consumption.
Preferably, after the power supply voltage is smaller than the power failure detection threshold voltage, the power supply is powered on again and power on detection is performed.
Preferably, the delay time of the first logic level is determined by controlling the discharge time, and the following relation is satisfied:
wherein C is the size of the charge-discharge capacitor, Q is the ratio of the width to the length of the current mirror in the charge-discharge subunit and the voltage divider subunit,
R 3 is the resistance value, V, of the resistor in the branch of the voltage-dividing subunit 1 For the power supply voltage being lower than the power-on detection threshold voltage
Voltage value at time of pressing, V 2 For the voltage value, V, after the power supply voltage is higher than the power-on detection threshold voltage GSN8 Is composed of
And the gate source voltage value of the transistor in the branch of the voltage divider subunit.
As described above, the power detection circuit and method of the present invention have the following advantages:
1. the power supply detection circuit and the method effectively control the power supply switch module through the pulse latch module, so that the voltage division sampling module and the voltage comparison module do not consume quiescent current after the power-on detection process is finished.
2. The power supply detection circuit and the method effectively latch the rising edge generated by the voltage comparison module after the power-on detection is finished through the pulse latch module, and output the result to the delay module for delay processing, thereby ensuring the stable operation of the system.
3. The power supply detection circuit and the method do not generate any static power consumption when the power supply voltage rises to the highest level and is stabilized at the highest level value through the pulse latch module and the delay module.
4. The power supply detection circuit and the method only delay the input rising edge through the delay module, in other words, only delay the power-on detection result of the power supply voltage, do not process the power-off detection result of the power supply voltage, and timely react after the power-off.
5. The power failure detection module in the power supply detection circuit and the method only judges the power supply voltage, and does not generate any static power consumption when the power supply voltage is electrified to the highest level and is stabilized at the highest level value.
6. According to the power supply detection circuit and method, when the power supply voltage is equal to the power supply voltage and the power-on detection threshold voltage is obtained, the NMOS transistor works in the sub-threshold region, the switching threshold voltage is obtained by utilizing the sub-threshold working characteristic of the MOS transistor, and compared with other traditional implementation methods, the power-on detection threshold voltage is small in change along with temperature, and the power supply detection circuit and method have the characteristics of high precision and low temperature coefficient; meanwhile, under the condition that the advantage that the power-on detection threshold voltage has an approximately zero temperature coefficient is ensured, the power supply voltage power-on detection threshold can achieve the advantage of flexibility and adjustability by adjusting the ratio of two resistances in the voltage division sampling circuit.
Drawings
Fig. 1 is a schematic diagram of a power-on reset circuit in the prior art.
Fig. 2 is a schematic diagram of another power-on reset circuit in the prior art.
Fig. 3 is a schematic diagram of a power-on reset circuit in the prior art.
Fig. 4 is a schematic structural diagram of the power detection circuit of the present invention.
Fig. 5 is a schematic diagram of the comparator according to the present invention.
FIG. 6 is a diagram showing simulation results of the power-on detection threshold voltage varying with temperature according to the present invention.
Fig. 7 is a schematic structural diagram of the RC delay cell of the present invention.
FIG. 8 is a schematic diagram of a comparison unit according to the present invention.
FIG. 9 is a flow chart illustrating a power detection method according to the present invention.
Description of the element reference numerals
1 Integrated POR Circuit
11 charge and discharge circuit
12 hysteresis circuit
2 mainstream POR circuit
21-bandgap reference circuit
22 voltage comparator
POR circuit with power failure detection
31 pulse latch circuit
32 power-down reset detection circuit
4 power supply detection circuit
41 power switch module
42 partial pressure sampling module
43 Voltage comparison Module
431 comparator
432 buffer unit
433 transmission gate
44 power down detection module
441 first charging and discharging capacitor
45 pulse latch module
451 latching loop
46 first output stage buffer module
47 time delay module
471 SR latch
472 RC delay unit 4
473 comparison unit
48 second output stage buffer module
S1-S8
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 4 to fig. 9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 4, the present invention provides a power detection circuit 4, where the power detection circuit 4 includes:
The circuit comprises a power switch module 41, a partial pressure sampling module 42, a voltage comparison module 43, a power failure detection module 44, a pulse latch module 45, a first output stage buffer module 46, a delay module 47 and a second output stage buffer module 48.
As shown in fig. 4, the power switch module 41 is connected to a power voltage VDD, the divided voltage sampling module 42 and the voltage comparison module 43, and is configured to turn on or off a path between the power voltage VDD and the divided voltage sampling module 42 and a path between the power voltage VDD and the voltage comparison module 43.
Specifically, in this embodiment, the power switch module 41 is an eleventh PMOS transistor PM11, the source of the eleventh PMOS transistor PM11 is connected to the power voltage VDD, the drain (output terminal) is connected to the divided voltage sampling module 42 and the voltage comparing module 43, and the gate (control terminal) is connected to the first output stage buffer module 46. When the power supply voltage VDD is powered on or powered off, the power switch module 41 is turned on; when the power supply voltage VDD is powered up, the power switch module 41 is turned off.
As shown in fig. 4, the divided-voltage sampling module 42 is connected to the output end of the power switch module 41, and is configured to divide and sample the voltage output by the power switch module 41.
Specifically, in this embodiment, the voltage division sampling module 42 includes a fourth resistor R4 and a fifth resistor R5 (power voltage sampling resistor), one end of the fourth resistor R4 is connected to the output end of the power switch module 41, the other end of the fourth resistor R4 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is grounded to GND, and a connection node between the fourth resistor R4 and the fifth resistor R5 serves as the output end of the voltage division sampling module 42. The voltage division sampling module 42 divides the voltage by the ratio of the fourth resistor R4 to the fifth resistor R5 to obtain a power supply detection voltage VN, and the value of the power supply detection voltage VN satisfies the following conditions:
wherein, V N Detecting the voltage value, R, of the voltage VN for the power supply 4 Is the resistance value of the fourth resistor R4, R 5 Is the resistance value, V, of the fifth resistor R5 D And outputting the voltage value of the voltage VD to the power switch module 41.
As shown in fig. 4, the voltage comparing module 43 is connected to the output terminals of the power switch module 41 and the divided voltage sampling module 42, and is configured to compare the power voltage VDD with a power-on detection threshold voltage V DD，thr And judging whether the power supply voltage VDD is electrified or not.
Specifically, the voltage comparing module 43 includes a comparator 431, a buffer 432 and a transmission gate 433, and the comparator 431 receives the power supply detection voltage VN and accordingly determines whether the power supply voltage VDD is powered up; the buffer unit 432 is connected to the output terminal of the comparator 431, and is configured to amplify and shape the output signal of the comparator 431 into a corresponding logic high level or logic low level; the transmission gate 433 is connected to the output end of the buffer unit 432, and is configured to output the output signal of the buffer unit 432.
More specifically, as shown in fig. 5, in the present embodiment, the comparator 431 includes a first NMOS transistor NM1, a second NMOS transistor NM2, a first PMOS transistor PM1, a second PMOS transistor PM2, a first resistor R1, and a second resistor R2. The first NMOS transistor NM1 and the second NMOS transistor NM2 are coupled as a pair of input transistors, and the first PMOS transistor PM1 and the second PMOS transistor PM2 are current mirrors. The gates of the first and second NMOS transistors NM2 and NM1 are connected to each other and to the power supply detection voltage VN; the drain of the first NMOS transistor NM1 is connected with the gate and drain of the first PMOS transistor PM 1; a source of the first NMOS transistor NM1 is connected to a first end of the second resistor R2; the drain of the second NMOS transistor NM2 is connected to the drain of the second PMOS transistor PM2 as the output terminal of the comparator 431; a source of the second NMOS transistor NM2 is connected to a first end of the first resistor R1; the second end of the first resistor R1 is connected with the first end of the second resistor R2; a second end of the second resistor R2 is grounded GND; the source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are both connected to the output voltage of the power switch module 41; the gate of the second PMOS transistor PM2 is connected with the gate and drain of the first PMOS transistor PM 1. The first resistor R1 is used for forming a source-end voltage difference Δ Vs between the first NMOS transistor NM1 and the second NMOS transistor NM 2; the first and second NMOS transistors NM1 and NM2 convert the difference Δ Vs between the power supply detection voltage VN and the source voltages of the input pair transistors into a first current and a second current, respectively, and then compare the first current after being mirrored with the second current by a current mirror circuit.
In this embodiment, the comparator 431 converts the power supply detection voltage VN into a first current through the first NMOS transistor NM1, and converts the power supply detection voltage VN into a second current through the second NMOS transistor NM2 and the first resistor R1; the first and second PMOS transistors PM1 and PM2 mirror the first current and compare the second current. The second resistor R2 converts the sum of the first current and the second current into a voltage Vs, and the voltage Vs across the second resistor R2 satisfies the following relation:
V S ＝(I DN1 +I DN2 )R 2 ，
wherein, I DN1 Is the current value of the first current, I DN2 Is the current value of the second current. A width-to-length ratio (W/L) of the second NMOS transistor NM2 N2 Width to length ratio (W/L) of the first NMOS transistor NM1 N1 1, the width-to-length ratio (W/L) of the first PMOS transistor PM1 P1 Width to length ratio (W/L) of the second PMOS transistor PM2 P2 The ratio of (1 to 1), and the resistance value R of the second resistor R2 2 And the resistance value R of the first resistor R1 1 The ratio of (A) to (B) is M:1, wherein N and M are natural numbers larger than 1.
When the power supply voltage VDD is equal to the power-on detection threshold voltage V DD ， thr When the second NMOS transistor NM2 and the first NMOS transistor NM1 are operated in the sub-threshold region, the second current and the first current are both sub-threshold currents, so that the first current is equal to the current flowing through the first PMOS transistor PM1, and the second current flowing through the second NMOS transistor NM2 is equal to the current flowing through the second PMOS transistor PM2, that is, the second current flows through the second NMOS transistor NM2 
Wherein, I DP1 For the value of the current flowing through the first PMOS transistor PM1, I DP2 For the value of the current flowing through the second PMOS transistor PM2, n is the sub-threshold slope factor, V T Is the thermodynamic potential, K is a constant, q is the electron charge, and T is the thermodynamic temperature. The power-up detection threshold voltage V DD，thr The following relationship is satisfied:
wherein, V gs,N1 Is a gate-source voltage (negative temperature coefficient voltage), I, of the first NMOS transistor NM1 D0 Is a process-related parameter, V th,N1 Is a threshold voltage of the first NMOS transistor NM 1. (2nV T ln N) M is positive temperature coefficient voltage, and the power-on detection threshold voltage V of zero temperature coefficient can be obtained by adjusting the value of N, M DD，thr By regulating
The power-up detection threshold voltage V may be determined DD，thr The numerical value of (c). At this time, the drain voltage of the second PMOS transistor PM2 is equal to the drain voltage of the first PMOS transistor PM1, i.e., V DP2 ＝V DP1 Wherein V is DP1 Is the value of the drain voltage, V, of the first PMOS transistor PM1 DP2 Is the value of the drain voltage of the second PMOS transistor PM 2.
When the power supply voltage VDD is higher than the power-on detection threshold voltage V DD，thr Then, the following relation is satisfied:
I DP1 ＝I DN1 >I DN2 ＝I DP2 ，
at this time, the drain voltage of the second PMOS transistor PM2 is greater than the drain voltage of the first PMOS transistor PM1, i.e., V DP2 >V DP1 。
When the power supply voltage VDD is lower than the power-on detection threshold voltage V DD，thr Then, the following relation is satisfied:
I DP1 ＝I DN1 <I DN2 ＝I DP2 ，
at this time, the drain voltage of the second PMOS transistor PM2 is less than the drain voltage of the first PMOS transistor PM1, i.e., V DP2 <V DP1 。
It should be noted that the comparator 431 may be implemented by any circuit structure for implementing comparison between two values, and is not limited to this embodiment.
More specifically, in the present embodiment, the buffer unit 432 includes an eighth inverter INV8 and a ninth inverter INV 9. An input end of the eighth inverter INV8 is connected to the output signal of the comparator 431, an output end of the eighth inverter INV8 is connected to an input end of the ninth inverter INV9, and an output end of the ninth inverter INV9 serves as an output end of the buffer unit 432.
In this embodiment, the power supply terminals of the eighth inverter INV8 and the ninth inverter INV9 are both connected to the output voltage of the power switch module 41, and compared to the situation that the power supply terminals of the eighth inverter INV8 and the ninth inverter INV9 are connected to the power supply voltage VDD, this embodiment can increase the time for the PMOS transistors of the eighth inverter INV8 and the ninth inverter INV9 to be turned on simultaneously, and increase the time for the NMOS transistors of the eighth inverter INV8 and the ninth inverter INV9 to be turned on simultaneously, thereby effectively amplifying the waveform of the output signal of the comparator 431.
In this embodiment, the buffer unit 432 performs amplification and shaping on the output signal of the comparator 431. When the power supply voltage VDD is equal to or greater than the power-on detection threshold voltage V DD ， thr The output signal V of the buffer unit 432 C Satisfies the following relation: v C →V D Wherein V is D Is the drain voltage value of the eleventh PMOS transistor PM 11; when the power supply voltage VDD is less than the power-on detection threshold voltage V DD ， thr The output signal V of the buffer unit 432 C Satisfies the following relation: v C →0。
It should be noted that the buffer unit 432 may include any even-numbered inverter, and is not limited to this embodiment.
More specifically, in the present embodiment, the transmission gate 433 includes a twelfth NMOS transistor NM12 and a twelfth PMOS transistor PM 12. The gate of the twelfth NMOS transistor NM12 is connected to the output voltage of the power switch module 41, and the source thereof is connected to the output terminal of the ninth inverter INV9 and the source of the twelfth PMOS transistor PM 12; the drain of the twelfth NMOS transistor NM12 is connected to the drain of the twelfth PMOS transistor PM12, and is used as the output terminal of the transmission gate 433 to output a comparison result det _ out, where the comparison result det _ out is a logic level; the gate of the twelfth PMOS transistor PM12 is grounded GND.
In the present embodiment, the width-to-length ratio (W/L) of the second NMOS transistor NM2 is set N2 Width to length ratio (W/L) of the first NMOS transistor NM1 N1 Set the resistance R of the second resistor R2 to 8 2 And the resistance value R of the first resistor R1 1 11/15, when the power-up detection threshold voltage V is greater than the threshold voltage V DD ， thr The simulation results with temperature change are shown in fig. 6. As can be seen from fig. 6, the power-up detection threshold voltage V DD ， thr Maintaining a zero temperature coefficient around a temperature of 35 ℃, and detecting the threshold voltage V of the electrification detection in a temperature range of-40 ℃ to 125 DEG C DD ， thr The variation is less than 7 mV; as can be seen, the power-up detection threshold voltage V DD ， thr Small change with temperature, high precision and low temperature coefficient.
As shown in FIG. 4, the power down detection module 44 couples the power supply voltage VDD to a power down detection threshold voltage V DD ， thf And comparing to judge whether the power supply voltage VDD is powered down.
Specifically, in this embodiment, the power down detection module 44 includes a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, and a first charging/discharging capacitor 441. In this embodiment, the first charge/discharge capacitor 441 is implemented by a sixth NMOS transistor NM 6. A source of the third PMOS transistor PM3 is connected to the supply voltage VDD; the gate and the drain of the third PMOS transistor PM3 are connected, and are connected to the gate of the sixth NMOS transistor NM6, the source of the fourth PMOS transistor PM4, and the source of the fifth PMOS transistor PM 5; the drain and source of the sixth NMOS transistor NM6 are grounded GND; the gate of the fifth PMOS transistor PM5 and the gate of the third NMOS transistor NM3 are connected to the power supply voltage VDD; a drain of the fifth PMOS transistor PM5 is connected with a drain of the third NMOS transistor NM3, and is connected with a gate of the fourth NMOS transistor NM4 and a gate of the fifth NMOS transistor NM 5; the drain of the fourth NMOS transistor NM4 is used as a first pull-down output terminal (connected to the input terminal of the fourth inverter INV4 in the pulse latch module 45); the drain of the fifth NMOS transistor NM5 is used as a second pull-down output terminal (connected to the output terminal of the pulse latch module 45); the drain of the fourth PMOS transistor PM4 serves as a pull-up output terminal (connected to the input terminal of the tenth inverter INV10 in the pulse latch module 25). The first charge-discharge capacitor 441 is charged when the power supply voltage VDD is powered on, and is discharged when the power supply voltage VDD is powered off; the output end of the power failure detection module 44 is connected to the pulse latch module 45, and in the power-on process of the power supply voltage VDD, the power failure detection module 44 does not affect the working state of the pulse latch module 45, and only changes the output state of the pulse latch module 45 when the power supply voltage VDD is powered down.
Specifically, in the present embodiment, during the power-on process of the power supply voltage VDD, the power supply voltage VDD is charged to the gate of the sixth NMOS transistor NM6 through the third PMOS transistor PM3 connected in a diode form, and the gate voltage VG of the sixth NMOS transistor NM6 is charged up to the level V DD -V th,P3 Wherein, V th,P3 Is the threshold voltage value of the third PMOS transistor PM 3; at this time, the difference between the source level and the gate level of the fourth PMOS transistor PM4 is smaller than zero, the fourth PMOS transistor PM4 is turned off, the drain output of the fourth PMOS transistor PM4 does not affect the working state of the pulse latch module 45, and the branch where the fifth PMOS transistor PM5 and the third NMOS transistor NM3 are located does not have any static current; the third NMOS transistor NM3 is turned on, the drain thereof is pulled low, the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 are both turned off, and the drain outputs of the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 do not affect the working state of the pulse latch module 45; thus, during power-up, the power-down testTest module 44 does not consume any static power consumption.
Specifically, the power supply voltage VDD begins to drop when the power supply voltage VDD drops to V DD -V th,P3 When the third PMOS transistor PM3 is in an off state, the fourth PMOS transistor PM4 is turned on because the difference between the source voltage and the gate voltage of the fourth PMOS transistor PM4 is greater than zero, and similarly, the third NMOS transistor NM3 is always in an on state because the difference between the source voltage and the gate voltage of the fifth PMOS transistor PM5 is greater than zero, so that a leakage path exists; at this time, the gate of the sixth NMOS transistor NM6 starts to discharge, and the discharge speed of the gate thereof is very slow due to the MOS capacitance of the sixth NMOS transistor NM 6.
Specifically, the power supply voltage VDD continuously drops when V is lower than the source of the fifth PMOS transistor PM5 th,P5 (V th,P5 A threshold voltage value of the fifth PMOS transistor PM 5), the fifth PMOS transistor PM5 is turned on, at this time, a current path is formed by the branch where the fifth PMOS transistor PM5 and the third NMOS transistor NM3 are located, as the power supply voltage VDD decreases, the turn-on capability of the third NMOS transistor NM3 is gradually smaller than the turn-on capability of the fifth PMOS transistor PM5, the drain level of the third NMOS transistor NM3 is gradually charged, and the charge level is close to the source level of the fifth PMOS transistor PM 5; the drains of the fourth and fifth NMOS transistors NM4 and NM5 are pulled down, and the drain level of the fourth PMOS transistor PM4 is pulled up and approaches the source level of the fourth PMOS transistor PM 4.
In this embodiment, the power-down of the power supply voltage VDD does not cause a delay, and once the input level of the delay module 47 changes from high to low, the output thereof will jump to low. The power failure detection threshold voltage V DD，thf The power-down speed depending on the power supply voltage VDD voltage also depends on the sizes of the fifth PMOS transistor PM5, the third NMOS transistor NM3, and the sixth NMOS transistor NM 6.
As shown in fig. 4, the pulse latch module 45 is connected to the output ends of the voltage comparison module 43 and the power failure detection module 44, and latches a high level of an output signal of the voltage comparison module 43 after the power supply voltage VDD is powered on; and after the power supply voltage VDD is powered down, latching the low level output by the power down detection module 44.
Specifically, the pulse latch module 45 includes a sixth PMOS transistor PM6, a seventh NMOS transistor NM7, a first capacitor C1, a second capacitor C2, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, and a latch loop 451. In the present embodiment, the latch loop 451 includes a tenth inverter INV10 and an eleventh inverter INV 11. The source of the sixth PMOS transistor PM6 is connected to the output terminal of the voltage comparing module 43, and the gate thereof is connected to the output terminal of the third inverter INV 3; a drain of the sixth PMOS transistor PM6 is connected to an input terminal of the fourth inverter INV4, a source of the seventh NMOS transistor NM7, and a first end of the second capacitor C2; the second end of the second capacitor C2 is grounded GND; an output end of the fourth inverter INV4 is connected to an input end of the first inverter INV1, an input end of the tenth inverter INV10, an output end of the eleventh inverter INV11 and a second end of the first capacitor C1; a first end of the first capacitor C1 is connected to the supply voltage VDD; an output end of the first inverter INV1 is connected to an input end of the second inverter INV2, and an output end of the second inverter INV2 is connected to an input end of the third inverter INV 3; an output end of the tenth inverter INV10 is connected to an input end of the eleventh inverter INV11, and serves as an output end of the pulse latch module 45; the gate of the seventh NMOS transistor NM7 is connected to the output terminal of the pulse latch module 45, and the drain is connected to the power supply voltage VDD.
Specifically, in the present embodiment, during the power-up process of the power supply voltage VDD, when the power supply voltage VDD is equal to the power-up detection threshold voltage V DD，thr Then, the pulse latch module 45 latches the rising edge of the output logic level of the voltage comparison module 43. In this embodiment, the capacitance value of the first capacitor C1 is about 200fF, and is used for supplying power to the power supplyWhen the voltage VDD is powered up, the inputs of the first inverter INV1 and the tenth inverter INV10 are changed along with the power supply voltage VDD, and the inversion threshold voltages of the first inverter INV1 and the tenth inverter INV10 are low, so the output levels of the first inverter INV1 and the tenth inverter INV10 are easily pulled low, and the output end of the third inverter INV3 (i.e., the gate of the sixth PMOS transistor PM 6) is pulled low, thereby providing a condition for the sixth PMOS transistor PM6 to be turned on; once the output logic level of the voltage comparison module 43 goes high and the difference between the output logic level of the voltage comparison module 43 and the gate level of the sixth PMOS transistor PM6 is greater than the threshold voltage of the sixth PMOS transistor PM6, the sixth PMOS transistor PM6 transmits the output logic high level of the voltage comparison module 43 to the input terminal of the fourth inverter INV 4; before the output logic level of the voltage comparison module 43 is not transmitted to the input end of the fourth inverter INV4 through the sixth PMOS transistor PM6, the output end of the tenth inverter INV10 is still pulled low, and the output end of the eleventh inverter INV11 is high, so as to form stable high-level latch; after the output logic high level of the voltage comparing module 43 is transmitted to the input terminal of the fourth inverter INV4 through the sixth PMOS transistor PM6, the input terminals of the first inverter INV1 and the tenth inverter INV10 are inverted through the fourth inverter INV4, so that the output terminal of the third inverter INV3 (i.e. the gate of the sixth PMOS transistor PM 6) is pulled high, and thus, the sixth PMOS transistor PM6 is turned off, and at the same time, the output terminal of the eleventh inverter INV11 is pulled low, forming a stable low level latch; the pulse latch module 45 outputs a high level.
Specifically, in this embodiment, in the power-down process of the power supply voltage VDD, the power supply voltage VDD is lower than the power-down detection threshold voltage V DD，thf Then, an input end of the fourth inverter INV4 is pulled down to a low level, an output end of the fourth inverter INV4 is pulled up to a high level, an output end of the latch loop 451 is pulled down to a low level, and the tenth inverter INV10 and the eleventh inverter INV11 form a stable voltage lockAnd then, the output of the pulse latch module 45 is fixed to a low level.
It should be noted that, after the sixth PMOS transistor PM6 is turned off, the level of the input end of the fourth inverter INV4 is floating, and discharges slowly, and once the power is down to a level that is lower than the inversion threshold of the fourth inverter INV4, the output of the fourth inverter INV4 jumps high, so that the output end of the tenth inverter INV10 is pulled low by mistake (at this time, the correct output of the tenth inverter INV10 should be high level). In this embodiment, the seventh NMOS transistor NM7 is added, so that the input level of the fourth inverter INV4 is maintained at a high level after the sixth PMOS transistor PM6 is turned off, and the input level is V DD -V th,N7 Wherein V is th,N7 Is a threshold voltage of the seventh NMOS transistor NM 7.
It should be noted that, if the power supply end of the fourth inverter INV4 is connected to the drain of the eleventh PMOS transistor PM11, and the power supply end of the fourth inverter INV4 is connected to the power supply voltage VDD, after the sixth PMOS transistor PM6 is turned off, the PMOS transistor and the NMOS transistor in the fourth inverter INV4 are turned on simultaneously, that is, the fourth inverter INV4 has a current path from the power supply voltage VDD to the ground GND, which consumes static power consumption. After the power source terminal of the fourth inverter INV4 is connected to the drain of the eleventh PMOS transistor PM11, the level of the input terminal of the fourth inverter INV4 will pull the drain level of the NMOS transistor in the inverter low, i.e. the output terminal of the fourth inverter INV4 is maintained at low level, and at this time, the output of the tenth inverter INV10 still maintains correct high level.
It should be noted that, in this embodiment, the substrate of the sixth PMOS transistor PM6 is connected to the power supply voltage VDD, and the second capacitor C2 is added to the drain of the sixth PMOS transistor PM6, and the value of the second capacitor C2 is about 2pF, so that a phenomenon that a level jitter occurs on the drain of the sixth PMOS transistor PM6 due to a change in threshold voltage caused by a transistor body effect when the power supply voltage VDD is powered on is effectively avoided. If the jittered level is near the inversion threshold of the fourth inverter INV4, the output end of the fourth inverter INV4 will be erroneously inverted, and the output result of the power detection circuit 4 will be affected.
Specifically, in this embodiment, during the power-on process of the power supply voltage VDD, when the power supply voltage VDD is equal to the power-on detection threshold voltage V DD，thr Then, the pulse latch module 45 latches the rising edge of the logic level output by the voltage comparison module 43, and turns off the power switch module 41, so that no current path exists between the voltage comparison module 43 and the divided voltage sampling module 42 and the power voltage VDD, that is, when the power voltage VDD is maintained at a high level, the voltage comparison module 43 and the divided voltage sampling module 42 do not consume static power consumption. In the power-down process of the power supply voltage VDD, when the power supply voltage VDD is lower than the power-down detection threshold voltage V DD，thf Then, the pulse latch module 45 latches the logic low level output by the power-down detection module 44, and the pulse latch module 45 does not consume any static power consumption when the power supply voltage VDD is maintained at a high level.
As shown in fig. 4, the first output stage buffer module 46 is connected to the output end of the pulse latch module 45 for enhancing the driving capability.
Specifically, in this embodiment, the first output stage buffer module 46 includes a first buffer BUF1 and a second buffer BUF2, an input end of the first buffer BUF1 is connected to the output of the pulse latch module 45, an output end of the first buffer BUF1 is connected to an input end of the second buffer BUF2, and an output end of the second buffer BUF2 is used as an output end of the first output stage buffer module 46; the first buffer BUF1 and the second buffer BUF2 are both used for enhancing the driving capability of the previous stage signal. The first output stage buffer module 46 can be implemented by using a schmitt trigger, and is not limited in this embodiment.
Specifically, the first buffer BUF1 latches the pulse latch module45, the output logic level enhances the driving capability and is then output to the power switch module 41. In the power-on process of the power supply voltage VDD, when the power supply voltage VDD is equal to the power-on detection threshold voltage V DD，thr Then, the output signal of the first buffer BUF1 is high, turning off the power switch module 41. In the power-down process of the power supply voltage VDD, when the power supply voltage VDD is lower than the power-down detection threshold voltage V DD，thf Then, the output signal of the first buffer BUF1 is low, and the power switch module 41 is turned on again, so that the process of detecting the secondary power-on of the power voltage VDD is not affected. The second buffer BUF2 enhances the driving capability of the input signal of the first buffer BUF1 to drive the next stage circuit.
It should be noted that, in this embodiment, the power switch module 41 is controlled by the output end of the first buffer BUF1, so as to turn off the power switch module 41 after the power supply voltage VDD is powered up, and turn on the power switch module 41 after the power supply voltage VDD is powered down; in practical use, the power switch module 41 can be controlled by the output signal of the pulse latch module 45 or the same phase signal obtained by further transmitting the output signal of the pulse latch module 45, which is not limited in this embodiment.
As shown in fig. 4, the delay module 47 is connected to the output end of the first output stage buffer module 46, and is configured to delay the signal output by the pulse latch module 45 after the power-on is finished, so as to ensure that the system stably operates; and when the power is down, the signal output by the pulse latch module 45 is not delayed.
Specifically, the delay module 47 includes an SR latch 471, an RC delay unit 472, a comparison unit 473, a fifth inverter INV5, a third buffer BUF3, a sixth inverter INV6, an AND gate AND, a seventh inverter INV7, AND a fourth buffer BUF 4. The input end of the third buffer BUF3 is connected with the output end of the first output stage buffer module 46; an output terminal of the third buffer BUF3 is connected to a reset terminal (R input terminal) of the SR latch 471 AND a first input terminal of the AND gate AND; the above-mentionedA second input end of the AND gate AND is connected to the inverted output end q' of the SR latch 471 AND the input end of the sixth inverter INV 6; an output end of the sixth inverter INV6 is used as an output end of the delay module 47; the output end of the AND gate AND is connected with the input end of the seventh inverter INV7, AND is used as the output end of the first delay control signal e; an output end of the seventh inverter INV7 as a second delay control signal 
An output terminal of (a); the RC delay unit 472 receives the first delay control signal e and the second delay control signal
According to the first delay control signal e and the second delay control signal
Carrying out charge and discharge; the comparing unit 473 is connected to the output end of the RC delay unit 472, and is configured to compare the charging voltage and the discharging voltage, so as to determine the delay time; an input end of the fourth buffer BUF4 is connected to an output end of the comparison unit 473, and an output end of the fourth buffer BUF4 is connected to an input end of the fifth inverter INV 5; an output end of the fifth inverter INV5 is connected to a set end (S input end) of the SR latch 471, and is configured to adjust an output signal of the SR latch 471 according to the delay time.
More specifically, the SR latch 471 includes a first NAND gate NAND1 and a second NAND gate NAND2, a first input terminal of the first NAND gate NAND1 is used as a set terminal S of the SR latch 471 D (ii) a A second input of the first NAND gate NAND1 is connected to the output of the second NAND gate NAND2 and to the inverting output of the SR latch 471; the output end of the first NAND gate NAND1 is connected to the first input end of the second NAND gate NAND2 and serves as the non-inverting output end of the SR latch 471; a second input terminal of the second NAND gate NAND2 is used as a reset terminal r of the SR latch 471 D 。
More specifically, as shown in fig. 7, the RC delay unit 472 includes a voltage dividing subunit and a charge and discharge subunit, and the voltage dividing subunit receives an output signal of the seventh inverter INV7 and provides an offset voltage for the charge and discharge subunit; the charge-discharge electronic unit receives the output signal of the NAND gate AND AND is used for determining delay time through discharging; the voltage divider unit comprises a seventh PMOS transistor PM7, a third resistor R3 and an eighth NMOS transistor NM8, wherein the source of the seventh PMOS transistor PM7 is connected to the power supply voltage VDD, the gate of the seventh PMOS transistor PM7 receives the output signal of the seventh inverter INV7, the drain of the seventh PMOS transistor PM7 is connected to the first end of the third resistor R3 and serves as the first output end Vd' of the RC delay unit 472, the second end of the third resistor R3 is connected to the drain and the gate of the eighth NMOS transistor NM8, and the source of the eighth NMOS transistor NM8 is grounded GND; the charge and discharge electronic unit comprises an eighth PMOS transistor PM8, a ninth NMOS transistor NM9 and a second charge and discharge capacitor 4721, wherein the source of the eighth PMOS transistor PM8 is connected to the power supply voltage VDD, the gate of the eighth PMOS transistor PM8 is connected to one end of the second charge and discharge capacitor 4721 and serves as a second output Vd of the RC delay unit 472, the other end of the second charge and discharge capacitor 4721 is grounded, the drain of the ninth NMOS transistor NM9 is connected to the drain of the eighth PMOS transistor PM8, the gate of the ninth NMOS transistor NM9 is connected to the gate of the eighth NMOS transistor NM8, and the source of the eighth NMOS transistor NM8 is grounded. In this embodiment, the second charge and discharge capacitor 4721 is implemented by a thirteenth NMOS transistor NM 13; the eighth NMOS transistor NM8 and the ninth NMOS transistor NM9 form a current mirror. When the output signal of the first output stage buffer module 46 is at a low level, the seventh PMOS transistor PM7 is turned off, the current passing through the third resistor R3 is zero, and the eighth PMOS transistor PM8 is turned on, so as to charge the second charge and discharge capacitor 4721; at the moment when the output signal of the first output stage buffer module 46 changes from low level to high level, the seventh PMOS transistor PM7 is turned on, the third resistor R3 and the eighth NMOS transistor NM8 divide the power voltage VDD to provide a bias for the ninth NMOS transistor NM9, the eighth PMOS transistor PM8 is turned off, the second charging and discharging capacitor 4721 discharges through the ninth NMOS transistor NM9, and the discharging time is the delay time of the delay module 47.
It should be noted that any circuit structure capable of performing charging and discharging according to the first delay control signal and the second delay control signal is applicable to the present invention, and is not limited to this embodiment.
More specifically, as shown in fig. 8, the comparison unit 473 includes a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, a tenth NMOS transistor NM10, and an eleventh NMOS transistor NM 11. The sources of the ninth PMOS transistor PM9 and the tenth PMOS transistor PM10 are connected to the power supply voltage VDD; the gate of the ninth PMOS transistor PM9 is connected to the gate and the drain of the tenth PMOS transistor PM 10; the drain of the ninth PMOS transistor PM9 is connected to the drain of the tenth NMOS transistor NM10 and serves as the output terminal of the comparing unit 473; the gate of the tenth NMOS transistor NM10 is connected to the first output terminal Vd of the RC delay unit 472 and the source ground GND; a drain terminal of the eleventh NMOS transistor NM11 is connected to the drain of the tenth PMOS transistor PM10, a gate thereof is connected to the second output terminal Vd' of the RC delay unit 472, and a source thereof is grounded. In the present embodiment, the tenth NMOS transistor NM10 has the same size as the eleventh NMOS transistor NM 11.
It should be noted that any circuit structure capable of comparing the magnitudes of two signals is applicable to the present invention, and is not limited to this embodiment.
Specifically, during the power-up process of the power supply voltage VDD, when the power supply voltage VDD is lower than the power-up detection threshold voltage V DD，thr Meanwhile, the third buffer BUF3 enhances the driving capability of the low level signal output by the first output stage buffer module 46, and the low level signal with enhanced driving capability is input to the reset terminal of the SR latch 471, so that the inverted output terminal q' of the SR latch 471 is set high, and the level inverted by the sixth inverter INV6 is used as the output signal of the delay module 47; the output low level signal of the third buffer BUF3 is used as the input level of the AND gate AND, which outputs a low level signal to control the charging path of the RC delay unit 472:the eighth PMOS transistor PM8 as a MOS switch is turned on, the power supply voltage VDD is charged to the gate of the thirteenth NMOS transistor NM13 as a MOS capacitor through the eighth PMOS transistor PM8 at a charge level Vd; the AND gate AND outputs a low level signal, which is inverted to a high level by the seventh inverter INV7, for controlling the discharge path of the RC delay unit 472: the seventh PMOS transistor PM7 as a MOS switch is turned off, so that no current flows through the branch of the third resistor R3, and the gate levels Vd' of the eighth NMOS transistor NM8 and the ninth NMOS transistor NM9 are low. The gate level Vd of the thirteenth NMOS transistor NM13 provides a level to the negative input terminal of the comparison unit 473, the gate level Vd ' of the eighth NMOS transistor NM8 and the gate level Vd ' of the ninth NMOS transistor NM9 provide a level to the positive input terminal of the comparison unit 473, since the negative input terminal level of the comparison unit 473 is greater than the positive input terminal level at this time, the output level of the comparison unit 473 is low, after the driving capability is enhanced by the fourth buffer BUF4, the low level signal output by the fourth buffer BUF4 is inverted by the fifth inverter INV5, the high level output by the fifth inverter INV5 is input to the set terminal of the SR latch 471, and since the inverted output terminal q ' of the SR latch 471 is high, the non-inverted output terminal q of the SR latch 471 is low.
In the process of powering up the power supply voltage VDD, when the power supply voltage VDD is higher than the power-up detection threshold voltage V DD，thr Then, the third buffer BUF3 receives the high level signal output by the first output stage buffer module 46, AND records that the corresponding time is t0, since before that, the level of the inverted output terminal q 'of the SR latch 471 is high, the output level of the sixth inverter INV6 (i.e., the output signal of the delay module 47) is low, the high level of the inverted output terminal q' of the SR latch 471 AND the high level signal output by the third buffer BUF3 are simultaneously used as the input signal of the AND gate AND, so that the output signal of the AND gate AND is turned high from low to control the charging path of the RC delay unit 472: as MOS switchesThe eighth PMOS transistor PM8 being off is turned off, and the power supply voltage VDD is no longer charged to the gate of the thirteenth NMOS transistor NM13 as a MOS capacitor through the eighth PMOS transistor PM 8. Meanwhile, the seventh inverter INV7 inverts the output signal of the AND gate AND to a low level to control the discharge path of the RC delay unit 472: the seventh PMOS transistor PM7 as a MOS switch is turned on, the power supply voltage VDD is charged to the gate of the eighth NMOS transistor NM8 and the gate capacitance of the ninth NMOS transistor NM9 through the third resistor R3, and the gate of the eighth NMOS transistor NM8 and the gate level Vd' of the ninth NMOS transistor NM9 are raised. The gate level Vd' of the ninth NMOS transistor NM9 is raised while providing a discharge path for the gate level Vd of the thirteenth NMOS transistor NM13 as a MOS capacitor. As described above, the gate level Vd of the thirteenth NMOS transistor NM13 provides a level to the negative input terminal of the comparison unit 473, the gate of the eighth NMOS transistor NM8 and the gate level Vd 'of the ninth NMOS transistor NM9 provide a level to the positive input terminal of the comparison unit 473, and when the gate level Vd of the thirteenth NMOS transistor NM13 is discharged by the ninth NMOS transistor NM9 to be equal to the gate of the eighth NMOS transistor NM8 and the gate level Vd' of the ninth NMOS transistor NM9, that is, when the negative input level of the comparison unit 473 is equal to the positive input level, the output level of the comparison unit 473 starts to be inverted from low to high. After the fourth buffer BUF4 enhances the driving capability, the high level output by the fourth buffer BUF4 is inverted by the fifth inverter INV5, the low level output by the fifth inverter INV5 is input to the set end of the SR latch 471, so that the positive phase output end q of the SR latch 471 is high level, the negative phase output end q' of the SR latch 471 is low level, therefore, the output level of the sixth inverter INV6 (i.e., the output signal of the delay module 47) is high level, the corresponding time is T1, and the time difference between T1 and T0 is the delay time of power-on detection, which is marked as T1, and is marked as the delay time of power-on detection of the power supply delay 。
The delay time T delay The following relationship is satisfied:
thus, the method can obtain the product,
wherein C is a MOS capacitance of the thirteenth NMOS transistor NM13, R 3 Q is a width-to-length ratio (natural number greater than or equal to 1) of the eighth NMOS transistor NM8 and the ninth NMOS transistor NM9, V is a resistance value of the third resistor R3 1 When the power supply voltage VDD is lower than the power-on detection threshold voltage V DD，thr Voltage value of time, V 2 For the power supply voltage VDD is higher than the power-on detection threshold voltage V DD，thr Value of the latter voltage, V GSN8 Is the gate source voltage value of the eighth NMOS transistor NM 8. After that, until the power supply voltage VDD is powered up to a stable level, the AND gate AND output level is turned from high to low again, AND the output level of the seventh inverter INV7 is turned from low to high, which means that the charging path of the RC delay unit 472 is opened again, AND the discharging path of the RC delay unit 472 is turned off again, so that the delay circuit does not consume any static power consumption because there is no current path for the delay module 47. It should be noted that, due to the existence of the SR latch 471, although the charging path of the RC delay unit 472 is opened again, the discharging path of the RC delay unit 472 is closed again, so that the output level of the comparison unit 473 changes from high to low again, the level of the non-inverting output terminal q of the SR latch 471 is latched high, the level of the inverting output terminal q' is latched low, the output level of the delay module 47 can be kept high, and the output result of the power detection circuit 4 will not be changed finally.
In the process of the power supply voltage VDD powering down, when the power supply voltage VDD is lower than the power down detection threshold voltage V DD，thf Then, the input level of the third buffer BUF3 is low, as analyzed above, the AND gate AND output level is low, AND the second buffer BUF3 is connected to the first bufferAn output level of the seven inverter INV7 is high, and an output end of the sixth inverter INV6 (i.e., the output level of the delay module 47) is low; while the charging path of the RC delay unit 472 is opened, the discharging path of the RC delay unit 472 is cut off, and the output level of the comparison unit 473 is kept low. Therefore, when the power supply voltage VDD is powered down, once the voltage value of the power supply voltage VDD is lower than the power-down detection threshold voltage V DD，thf Then, the output of the delay module 47 will immediately turn to low level, and will not generate any delay effect on the power-down process.
As shown in fig. 4, an input terminal of the second output stage buffer module 48 is connected to an output terminal of the delay module 47 for improving the driving capability.
Specifically, the second output stage buffering module 48 includes a fifth buffer BUF5, an input end of the fifth buffer BUF5 is connected to an output end of the delay module 47, and an output end of the fifth buffer BUF5 is a final output end POR _ OUT of the power detection circuit 4. The size of the fifth buffer BUF5 can be determined according to the load that needs to be driven by the external circuit.
Therefore, the power supply detection circuit not only realizes the power-on detection and power-off detection functions of the power supply voltage, but also realizes the delayed output function of the power-on detection signal, does not consume any static power consumption when the power supply is stable, has the characteristics of high precision and low temperature coefficient of the power-on detection threshold voltage, and provides a reliable reset effect for the chip. Compared with other high-precision power supply detection circuits, the invention effectively reduces the complexity of the circuit.
The present invention further provides a power detection method, in this embodiment, the power detection method is implemented based on the power detection circuit 4, and includes:
switching on a power supply voltage, carrying out partial pressure sampling on the power supply voltage, and carrying out power-on detection on the power supply voltage based on a signal obtained by the partial pressure sampling; performing power failure detection on the power supply voltage;
if the power supply voltage is greater than the power-on detection threshold voltage, outputting a first logic level, and performing delay output on the first logic level to ensure that the system works stably;
if the power supply voltage is less than the power failure detection threshold voltage, outputting a second logic level, and not performing delay output on the second logic level;
Wherein the power-up detection threshold voltage is greater than the power-down detection threshold voltage.
As shown in fig. 9, the method specifically includes the following steps:
step S1: the power switch module 41 is turned on or off according to a power-on or power-off condition.
Specifically, when the power supply voltage VDD is greater than the power-up detection threshold voltage V DD，thr Then, the power switch module 41 is turned off; when the power supply voltage VDD is less than the power failure detection threshold voltage V DD，thr After that, the power switch module 41 is turned on again.
Step S2: the voltage magnitude of the power voltage VDD at power-up is detected based on the divided voltage sampling module 42, and a power detection voltage VN is provided.
Specifically, in the present embodiment, the power supply voltage VDD is detected by using a resistance voltage division method. After the power voltage VDD is powered up to a stable voltage, the divided voltage sampling module 42 is disconnected from the power switch module 41, and static power consumption is not consumed.
Step S3: comparing the power supply voltage VDD with the power-up detection threshold voltage V based on the voltage comparison module 43 DD ， thr And comparing to perform power-on detection.
Specifically, the voltage difference between the sources of the input pair transistors is generated by resistors respectively connected to the sources of the input pair transistors, the input pair transistors (the first NMOS transistor NM1 and the second NMOS transistor NM2) respectively convert the signal obtained by voltage division sampling and the voltage difference between the sources of the input pair transistors into a first current and a second current, the first current and the second current are compared by a current mirror, and a corresponding voltage is output, and the corresponding voltage is amplified and shaped, then outputs a logic level, and is transmitted to a next-stage circuit through a transmission gate 433; wherein the first current is equal to the supply voltage A value proportional to the second current proportional to the value of the power-up detection threshold voltage. The power-on detection threshold voltage V is determined by adjusting the size of the input geminate transistors, the proportion of resistors respectively connected with the source electrodes of the input geminate transistors, the size of the current mirror and the size of the power supply voltage sampling resistor DD，thr A value of (d); setting the power-on detection threshold voltage V by adjusting the sizes of the input pair transistors and the current mirror DD，thr Is a zero temperature coefficient voltage; for more specific working principles, reference is made to the above, which is not repeated herein. After the power voltage VDD is powered up to a stable voltage, the voltage comparison module 43 is disconnected from the power switch module 41, and static power consumption is not consumed.
Step S4: and performing power-down detection on the power supply voltage VDD based on the power-down detection module 44.
Specifically, when the power supply voltage VDD is powered on, the power down detection module 44 does not change the output state of the pulse latch module 45; when the power supply voltage VDD is smaller than the power failure detection threshold value V DD，thf When the voltage is applied, the power down detection module 44 outputs a low level to the pulse latch module 45. After the power supply voltage VDD is powered up to a stable voltage, the power down detection module 44 does not consume static power.
Step S5: and latching the low level transmitted by the power failure detection module 44 based on the rising edge of the voltage transmitted by the voltage comparison module 43 latched by the pulse latch module 45.
Specifically, power up to the power-up detection threshold V at the power supply voltage VDD DD，thr Then, the pulse latch module 45 inputs a high level signal, and the output signal is latched to a high level as an output signal; when the power supply voltage VDD is powered down, the pulse latch module 45 inputs a low level signal, and latches the output signal as a low level signal as an output signal. After the power supply voltage VDD is powered up to a stable voltage, the pulse latch module 45 does not consume static power consumption.
Step S6: the driving capability of the output level of the pulse latch module 45 is enhanced based on the first output stage buffer module 46.
Specifically, when the output level of the pulse latch module 45 is a high level, the first output stage buffer module 46 transmits a high level signal as a control signal to the power switch module 41; when the output level of the pulse latch module 45 is low level, the first output stage buffer module 46 transmits a low level signal as a control signal to the power switch module 41. After the power supply voltage VDD is powered up to a stable voltage, the first output stage buffer module 46 does not consume static power.
Step S7: the power-on detection signal is delayed based on the delay module 47.
Specifically, when the power supply voltage VDD exceeds the power-up detection threshold voltage V DD，thr Then, the delay module 47 delays the rising edge output by the first output stage buffer module 46; when the power supply voltage VDD is lower than the power failure detection threshold voltage V DD，thf Thereafter, the delay module 47 does not delay. After the power supply voltage VDD is powered up to a stable voltage, the delay module 47 does not consume static power.
More specifically, in the present embodiment, the delay time is determined by controlling the discharge time, and the following relation is satisfied:
wherein C is the size of the charge-discharge capacitor, Q is the ratio of the width to the length of the current mirror in the charge-discharge electronic unit and the voltage divider unit, and R is 3 Is the resistance value, V, of the resistor in the branch of the voltage-dividing subunit 1 Is the voltage value, V, when the power supply voltage is lower than the power-on detection threshold voltage 2 For the voltage value, V, after the power supply voltage is higher than the power-on detection threshold voltage GSN8 And the voltage value is the gate source voltage value of the transistor in the branch of the voltage division subunit.
Step S8: based on the second output stage buffer module 48, the logic level driving capability output by the delay module 47 is enhanced, and the output signal is used as the output signal of the power detection circuit 4.
The power supply detection circuit and the method of the embodiment turn on or off the path of the power supply, the voltage division sampling module and the voltage comparison module through the power supply switch module, detect the voltage of the power supply voltage during electrification through the voltage division sampling module, convert the level obtained by voltage division sampling into current suitable for mutual comparison through the voltage comparison module, and amplify and shape the comparison result into a logic level. When the power supply voltage is electrified and exceeds the power-on detection threshold voltage, the pulse latch module latches a high level signal and outputs the high level signal to the first output stage buffer module, and the first output stage buffer module outputs the enhanced driving high level signal to the power supply switch module, so that the power supply switch module is turned off, and the paths of a power supply, the partial pressure sampling module and the voltage comparison module are cut off; meanwhile, the first output stage buffer module inputs the enhanced-driving high-level signal to the delay module, and the delay module delays the rising edge input by the first output stage buffer module after the power supply voltage exceeds the power-on detection threshold voltage. When the power supply voltage is powered down, the power failure detection module outputs a low level signal to the pulse latch module after detecting that the power supply voltage is lower than the power failure detection threshold voltage, the pulse latch module latches the low level signal and outputs the low level signal to the first output stage buffer module, the first output stage buffer module inputs the signal after enhanced driving to the delay module, the delay module does not delay the input low level signal, only keeps the low level signal input into the delay circuit, and outputs the low level. The second output stage buffer module enhances the logic level driving capability output by the delay circuit, and the output signal is used as the output signal of the power supply detection circuit 4.
In summary, the present invention provides a power detection circuit and method, in which a voltage division sampling module and a voltage comparison module, the detected voltage signal of the power supply during power-on is sampled and divided, converted into currents suitable for mutual comparison and then compared, and the result is shaped, amplified and transmitted to a pulse latch module which effectively latches the rising edge signal transmitted by the voltage comparison module, the voltage output after the driving capability is enhanced by the first output stage buffer module is used as a control signal of the power switch, the power switch is closed in time, a path between a power supply and the partial pressure sampling module and the voltage comparison module is cut off, and the voltage is input into the delay module, the delay module carries out delay processing on the input rising edge, and then the voltage is used as an output signal of the power detection circuit after the driving capability is enhanced by the second output stage buffer module. In addition, the power failure detection module detects a voltage threshold value when the power supply fails, when the detected power supply voltage is lower than the power failure detection threshold voltage, the output low level signal is transmitted to the pulse latch module, the pulse latch module effectively latches the low level signal transmitted by the power failure detection module, the low level signal is input to the delay module after the driving capability of the first output stage buffer circuit is enhanced, the delay module does not process the low level signal detected by the power failure, only holds the low level signal and outputs the low level signal to the second output stage buffer module, and the second output stage buffer module serves as an output signal of the power supply detection circuit after the driving capability of the second output stage buffer module is enhanced. In addition, when the power supply voltage is equal to the power supply power-on detection voltage threshold, the voltage comparison module enables the MOS transistor to work in the sub-threshold region, so that the switching threshold voltage is obtained by utilizing the sub-threshold working characteristic of the MOS transistor. In addition, after the power supply voltage is electrified to the stable voltage, no static power consumption is generated in any circuit part of the power supply detection circuit, and the characteristic of zero power consumption is achieved. The power supply detection circuit not only can accurately detect the power-on voltage of the power supply and delay the power-on voltage, provides a reliable reset function, but also can detect the power failure of the power supply, and can output the reset signal in time when the power supply voltage is not enough for the chip to normally work, thereby ensuring that circuit modules outside other chip power supply detection circuits can safely and correctly work under normal voltage. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (14)
1. A power detection circuit, comprising:
the power supply circuit comprises a power switch module, a partial pressure sampling module, a voltage comparison module, a power failure detection module and a pulse latch module;
the power switch module is connected with a power voltage, the partial pressure sampling module and the voltage comparison module, is controlled by the output signal of the pulse latch module, and is switched on when the power voltage is powered on or after the power failure; when the power supply voltage is electrified, the power supply switch module is turned off;
the voltage division sampling module is connected with the output end of the power switch module and is used for carrying out voltage division sampling on the voltage output by the power switch module;
The voltage comparison module is connected with the output ends of the power switch module and the partial pressure sampling module and is used for comparing the power voltage with a power-on detection threshold voltage so as to judge whether the power voltage is powered on;
the power failure detection module compares the power supply voltage with a power failure detection threshold voltage to judge whether the power supply voltage has power failure;
the pulse latch module is connected with the output ends of the voltage comparison module and the power failure detection module, and latches the high level of the output signal of the voltage comparison module after the power supply voltage is electrified; after the power supply voltage is powered down, latching the low level output by the power down detection module; the voltage comparison module comprises a comparator, a buffer unit and a transmission gate, wherein the comparator receives an output signal of the voltage division sampling module and judges whether the power supply voltage is electrified or not; the buffer unit is connected with the output end of the comparator and used for amplifying and shaping the output signal of the comparator into a corresponding logic high level or logic low level; the transmission gate is connected with the output end of the buffer unit and is used for outputting the output signal of the buffer unit;
The comparator comprises a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first resistor and a second resistor;
the source electrodes of the first PMOS transistor and the second PMOS transistor are connected with the output end of the power switch module; the grid and the drain of the first PMOS transistor are connected with the grid of the second PMOS transistor; the drain electrode of the first NMOS transistor is connected with the drain electrode of the first PMOS transistor, the grid electrode of the first NMOS transistor is connected with the grid electrode of the second NMOS transistor, and the source electrode of the first NMOS transistor is connected with the first end of the second resistor; the drain electrode of the second NMOS transistor is connected with the drain electrode of the second PMOS transistor, and the source electrode of the second NMOS transistor is connected with the first end of the second resistor after passing through the first resistor; the second end of the second resistor is grounded;
the ratio N of the width-to-length ratio of the second NMOS transistor to the width-to-length ratio of the first NMOS transistor is 8, and the ratio M of the resistance value of the second resistor to the resistance value of the first resistor is 11/15;
the power end of the buffer unit is connected with the output signal of the power switch module; the buffer unit comprises an eighth inverter and a ninth inverter, wherein the input end of the eighth inverter is connected with the output signal of the comparator, the output end of the eighth inverter is connected with the input end of the ninth inverter, and the output end of the ninth inverter is the output end of the buffer unit;
The power supply detection circuit also comprises a delay module, wherein the delay module receives the output signal of the pulse latch module and delays the signal output by the pulse latch module after the power supply is finished so as to ensure the stable work of the system;
the time delay module comprises an SR latch, an RC time delay unit, a comparison unit, a fifth inverter, a sixth inverter, an AND gate and a seventh inverter;
the reset end of the SR latch and the first output end of the AND gate receive the output signal of the pulse latch module; the second input end of the AND gate is connected with the inverted output end of the SR latch and the input end of the sixth inverter; the output end of the sixth inverter is used as the output end of the delay module; the output end of the AND gate is connected with the input end of the seventh inverter and outputs a first delay control signal; the output end of the seventh inverter outputs a second delay control signal; the RC time delay unit receives the first time delay control signal and the second time delay control signal and carries out charging and discharging according to the first time delay control signal and the second time delay control signal; the comparison unit is connected to the output end of the RC delay unit and used for comparing the charging voltage with the discharging voltage so as to determine the delay time; the fifth inverter receives the output signal of the comparison unit, and the output end of the fifth inverter is connected with the set end of the SR latch and is used for adjusting the output signal of the SR latch according to the delay time.
2. The power supply detection circuit of claim 1, wherein: the power failure detection module comprises a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a first charge-discharge capacitor;
the source electrode of the third PMOS transistor is connected with the power supply voltage; the grid electrode of the third PMOS transistor is connected with the drain electrode of the third PMOS transistor, and is connected with the source electrode of the fourth PMOS transistor, the source electrode of the fifth PMOS transistor and the first charge-discharge capacitor; the grid electrode of the fifth PMOS transistor and the grid electrode of the third NMOS transistor are connected with the power supply voltage; the drain electrode of the fifth PMOS transistor is connected with the drain electrode of the third NMOS transistor and is connected with the grid electrode of the fourth NMOS transistor and the grid electrode of the fifth NMOS transistor; the drain electrode of the fourth NMOS transistor is used as a first pull-down output end; the drain electrode of the fifth NMOS transistor is used as a second pull-down output end; and the drain electrode of the fourth PMOS transistor is used as a pull-up output end.
3. The power supply detection circuit of claim 2, wherein: the first charge-discharge capacitor is a sixth NMOS transistor, the grid electrode of the sixth NMOS transistor is connected with the drain electrode of the fourth NMOS transistor, and the source electrode and the drain electrode of the sixth NMOS transistor are grounded.
4. The power supply detection circuit of claim 1, wherein: the pulse latch module comprises a sixth PMOS transistor, a seventh NMOS transistor, a first capacitor, a first inverter, a second inverter, a third inverter, a fourth inverter and a latch loop;
the source electrode of the sixth PMOS transistor is connected with the output end of the voltage comparison module, and the grid electrode of the sixth PMOS transistor is connected with the output end of the third inverter; the drain electrode of the sixth PMOS transistor is connected with the input end of the fourth inverter and the source electrode of the seventh NMOS transistor; the output end of the fourth inverter is connected with the input end of the first inverter, the input end of the latch loop and the second end of the first capacitor; the first end of the first capacitor is connected with the power supply voltage; the output end of the first phase inverter is connected with the input end of the second phase inverter; the output end of the second inverter is connected with the input end of the third inverter; the grid electrode of the seventh NMOS transistor is connected with the output end of the latch loop circuit, and the drain electrode of the seventh NMOS transistor is connected with the power supply voltage; and the output end of the latch loop is used as the output end of the pulse latch module.
5. The power supply detection circuit of claim 4, wherein: the pulse latch module further comprises a second capacitor, wherein the first end of the second capacitor is connected with the drain electrode of the sixth PMOS transistor, and the second end of the second capacitor is grounded.
6. The power supply detection circuit of claim 4, wherein: and the substrate of the sixth PMOS transistor is connected with the source electrode.
7. The power supply detection circuit of claim 4, wherein: and the power end of the fourth inverter is connected with the output signal of the power switch module.
8. The power supply detection circuit of claim 1, wherein: the power supply detection circuit further comprises a first output stage buffer module connected to the output end of the pulse latch module.
9. The power supply detection circuit of claim 1, wherein: the RC time delay unit comprises a voltage division subunit and a charge-discharge electronic unit, wherein the voltage division subunit receives an output signal of the seventh inverter and provides bias voltage for the charge-discharge electronic unit; the charge-discharge electronic unit receives the output signal of the AND gate and is used for determining delay time through discharging; the voltage divider subunit comprises a seventh PMOS transistor, a third resistor and an eighth NMOS transistor, wherein the source electrode of the seventh PMOS transistor is connected with the power supply voltage, the grid electrode of the seventh PMOS transistor receives the output signal of the seventh inverter, the drain electrode of the seventh PMOS transistor is connected with the first end of the third resistor, the second end of the third resistor is connected with the drain electrode and the grid electrode of the eighth NMOS transistor and serves as the first output end of the RC delay unit, and the source electrode of the eighth NMOS transistor is grounded; the charge and discharge electronic unit comprises an eighth PMOS transistor, a ninth NMOS transistor and a second charge and discharge capacitor, wherein the source electrode of the eighth PMOS transistor is connected with the power voltage, the drain electrode of the eighth PMOS transistor is connected with one end of the second charge and discharge capacitor and serves as a second output end of the RC delay unit, the other end of the second charge and discharge capacitor is grounded, the drain electrode of the ninth NMOS transistor is connected with the drain electrode of the eighth PMOS transistor, the grid electrode of the ninth NMOS transistor is connected with the grid electrode of the eighth NMOS transistor, and the source electrode of the ninth NMOS transistor is grounded.
10. The power supply detection circuit of claim 9, wherein: the comparison unit comprises a tenth NMOS transistor, an eleventh NMOS transistor, a ninth PMOS transistor and a tenth PMOS transistor, wherein the tenth NMOS transistor and the eleventh NMOS transistor are used as input geminate transistors, and the ninth PMOS transistor and the tenth PMOS transistor are used as current mirrors; the grid electrode of the tenth NMOS transistor is connected with the second output end of the RC delay unit, the drain electrode of the tenth NMOS transistor is connected with the drain electrode of the ninth PMOS transistor and serves as the output end of the comparison unit, and the source electrode of the tenth NMOS transistor is grounded; the grid electrode of the ninth PMOS transistor is connected with the grid electrode and the drain electrode of the tenth PMOS transistor and is connected with the drain electrode of the eleventh NMOS transistor, and the source electrode of the ninth PMOS transistor is connected with the power supply voltage; the source electrode of the tenth PMOS transistor is connected with power voltage; the grid electrode of the eleventh NMOS transistor is connected with the first output end of the RC delay unit, and the source electrode of the eleventh NMOS transistor is grounded; the comparison unit compares the output result of the RC delay unit, and when the level of a second output end of the RC delay unit is higher than the level of a first output end, the output of the comparison unit is low level; when the level of the second output end of the RC delay unit is lower than that of the first output end, the output of the comparison unit is high level.
11. A power detection method based on the power detection circuit as claimed in any one of claims 1 to 10, wherein the power detection method at least comprises:
switching on a power supply voltage, performing voltage division sampling on the power supply voltage, and performing power-on detection on the power supply voltage based on a signal obtained by the voltage division sampling; performing power failure detection on the power supply voltage;
if the power supply voltage is greater than the power-on detection threshold voltage, outputting a first logic level, and performing delay output on the first logic level to ensure that the system works stably;
if the power supply voltage is less than the power failure detection threshold voltage, outputting a second logic level, and not performing delay output on the second logic level;
wherein the power-up detection threshold voltage is greater than the power-down detection threshold voltage; the method for carrying out power-on detection on the power supply voltage comprises the following steps:
the input geminate transistors convert signals obtained by partial pressure sampling and the source electrode voltage difference of the input geminate transistors into first current and second current respectively based on the source electrode voltage difference of the input geminate transistors, the first current and the second current are compared through a current mirror, corresponding voltage is output, and logic level is output after the corresponding voltage is amplified and shaped; setting the voltage with the power-on detection threshold value of zero temperature coefficient by adjusting the proportion between the input pair of tubes and the proportion between the resistors respectively connected with the source electrodes of the input pair of tubes; and the value of the power-on detection threshold voltage is determined by adjusting the size of the input geminate transistor, the proportion of resistors respectively connected with the source electrodes of the input geminate transistor, the size of the current mirror and the size of the power supply voltage sampling resistor.
12. The power supply detection method according to claim 11, characterized in that: and after the power supply voltage is greater than the power-on detection threshold voltage, the power-on detection is not carried out any more so as to reduce the static power consumption.
13. The power supply detection method according to claim 11, characterized in that: and after the power supply voltage is less than the power failure detection threshold voltage, carrying out power-on again and carrying out power-on detection.
14. The power supply detection method according to claim 11, characterized in that: determining the delay time of the first logic level by controlling the discharge time, wherein the following relation is satisfied:
wherein C is the size of the charge-discharge capacitor, Q is the ratio of the width to the length of the current mirror in the charge-discharge electronic unit and the voltage divider unit, and R is 3 Is the resistance value, V, of the resistor in the branch of the voltage-dividing subunit 1 Is the voltage value, V, when the power supply voltage is lower than the power-on detection threshold voltage 2 After the power supply voltage is higher than the power-on detection threshold voltageValue of voltage, V GSN8 And the voltage value is the gate source voltage value of the transistor in the branch of the voltage division subunit.
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| CN109379065B (en) * | 2018-11-30 | 2023-11-10 | 上海艾为电子技术股份有限公司 | Voltage detection circuit, overvoltage protection switch and electronic equipment |
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