CN108631753A - A kind of integration compensation digital filter design method - Google Patents
A kind of integration compensation digital filter design method Download PDFInfo
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- CN108631753A CN108631753A CN201810461952.1A CN201810461952A CN108631753A CN 108631753 A CN108631753 A CN 108631753A CN 201810461952 A CN201810461952 A CN 201810461952A CN 108631753 A CN108631753 A CN 108631753A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0219—Compensation of undesirable effects, e.g. quantisation noise, overflow
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/04—Recursive filters
- H03H17/0416—Recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
- H03H17/0427—Recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
- H03H17/0438—Recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer
- H03H17/0444—Recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer where the output-delivery frequency is higher than the input sampling frequency, i.e. interpolation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0219—Compensation of undesirable effects, e.g. quantisation noise, overflow
- H03H2017/0222—Phase error
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Abstract
A kind of integration compensation digital filter design method of the present invention, steps are as follows：(1) filter coefficient is designed, the inhibition completed to down coversion high fdrequency component is taken into account, the matching to formed filter of starting and the anti-aliasing filter to variable Rate processing；(2) it is stored after being recombinated to filter coefficient, wherein the recombination form adapts to different rates as far as possible, while being easy to the realization of parallel computation；(3) the valid data length for participating in operation and the data amount check for carrying out sampled data recovery are calculated, corresponding filter multiplexing operation is completed；(4) compensation is completed using the offset information that bit timing obtains, which includes compensation two parts of the compensation and input data of the coefficient to participating in filtering operation；(5) according to the coefficient and data after adjustment, the calculating of last filter result is completed using the realization method of parallel plus flowing water mixing.
Description
Technical field
The invention discloses integrations to compensate digital filter design method, in wideband satellite communication, deep space communication, movement
It is widely used in the communication systems such as communication, belongs to communication modulation demodulation techniques field.
Background technology
In recent ten years, the aerospace industry in China is in the prosperity and development stage.Manned spacecraft, navigation satellite, relaying are defended
The various spacecrafts such as star, earth observation satellite, telecommunication satellite, deep space probe and microsatellite are increasing, all-round developing.On
2 kinds of channels such as spacecraft Jun You low rates omnidirectional's observing and controlling channel and high-rate service data channel are stated, realize observing and controlling and height respectively
Fast number passes function.Observing and controlling and operation system are relatively independent, repeated construction deficiency in economic performance.Demand of the business datum to measuring and control data
Different, co-ordination is complicated.
The type and quantity of satellite in orbit continue to increase, and data transmission rate continues to improve, and space mission tends to diversification.Satellite
Use demand increased dramatically, and the satellite in orbit quantity managed simultaneously is needed to increase year by year.Existing operating mode cannot meet
Business demand.Observing and controlling number passes integrated design, can simplify on-board equipment, improve Electromagnetic Compatibility, reduces power consumption, section
About frequency resource, and incorporate earth station's resource, reduce management complexity.Integrated channel is conducive to the air-ground integrated test in day
The construction for controlling communication network, is conducive to participate in international cooperation, and adapts to the developing direction of following observing and controlling and the communication technology.
When passing the design of integrated physical layer system towards this observing and controlling number, receiver uses the non-spread spectrum bodies of PCM-BP SK
System provides high-speed transfer channel for several biography demands.Receiver symbol synchronizes by the way of Closed loop track, realizes sampling timing
Deviation data dynamic adjusts, and ability of tracking is strong, and can provide high-precision bit timing deviation phase information for completing observing and controlling
Correlation function.
Conventional sign synchronization front end signal processing needs several steps：Sampled data needs after being converted to base band
It carries out low-pass filtering and filters out image component；Variable Rate filtering is carried out for sample rate and the unmatched scene of information rate (to take out
Take and interpolation), multi-level can be divided, can also single-section filter realize, need consider variable Rate factor I/Q (interpolations/pumping
Take) value carry out different designs；Complete matched filtering correlation function, usually can with it is a certain in prime variable Rate filter
Grade (variable Rate filter is multiple filter), which merges, to be used；Ordinary symbol synchronizes interpolation filter and discrete can be adopted according to known
The value of sampling point calculates the value in unknown point, its calculating thinking is similar with curve matching, is remained unchanged on interpolation point, commonly
To be based on polynomial interpolation filter.
The closed loop symbols transmitted synchronous method of forward direction is not suitable for telemetry communication due to not having accurate bit timing information.Mesh
There are mainly two types of the closed loop symbol Self-synchronous algorithms of preceding digital receiver, first, adding loop by timing error detection (TED) algorithm
Phase difference between filter estimating sampling clock and optimum sampling moment, when then being sampled by digital controlled oscillator NCO adjustment
Clock, referred to as synchronized sampling restore；It is another also to be differed using identical method estimation clock, but it does not adjust sampling clock phase
Position, but sampled value is modified by interpolation algorithm, referred to as asynchronous-sampling restores.
For the timing data restoration methods in currently used sign synchronization, " one kind is same based on interpolation method symbol for document
The design of step circuit " realizes timing synchronization using the algorithm that cube interpolation and O＆M Timing Error Detections are combined, right first
It receives data and carries out filtering interpolation and extraction, generate interpolated signal；Timing Error Detection unit calculates timing error；Through overrunning
After rate transformation, loop filter and resampling, the control word of NCO is formed；NCO generates interpolation time-ofday signals and symbol clock.Text
It offers " the 8PSK demodulator designs based on FPGA " and uses a kind of reaction type symbol timing synchronization method based on interpolation, do not changing sampling
Under conditions of rate, by obtaining the optimal judgement data of each data symbol in output end into row interpolation to sampled data.The party
Method interpolation filter is Polynomial Filter, is calculated using fitting of a polynomial mode.Document " digital high speed OQPSK letters
The sign synchronization loop that number demodulation techniques analysis " uses uses the timing recovery algorithm based on interpolation filtering, and main includes timing
Error detector, loop filter, interpolation filter and interpolation controller etc..Input data is sampled with the rate of 1/Ts,
It obtains sampled point x (mTs) sampled point and carries out timing offset estimation generation error signal e (k) after filtering interpolation, filtered through loop
Wave device adds up after filtering out noise, adds up and overflows triggering shifting function or the operation of down-sampled advanced or late samples to fixed
When position be adjusted, to be gradually adjusted to y (kTi) optimum sampling output.Three kinds of algorithms inherently need to draw above
Enter the polynomial interopolation filter of absolute construction, only polynomial interopolation filter uses different structures, and the structure
Filter can not with front end filter is unified from design considers, be traditional receivers distribution process mode, realize framework compared with
For complexity, it is unfavorable for integrated General design, realizes that process is cumbersome.
The Farrow Structure Filters of document real time correction time error design " realize that one kind being based on Farrow configuration scores
Real time correction of time delay (Fractional Delay, the FD) filter to the non-homogeneous error of time in parallel sampling.Using optimization
The method of design, each sub- filtering for solving Farrow structure FD filters clamor coefficient in the case where resource consumption as far as possible is few,
So that the smaller of design deviation is ensured the precision of follow-up time delay error estimation and correction, and realizes that the time misses in the FPGA of Xilinx
The correction of difference.The same relative receiver front-end filtering of the structure is independent, can not integrated design.
Document " a kind of digital fabrication filter processing method of continuous variable rate " provides a kind of continuous variable rate
The step of digital fabrication filter processing method, this method includes：1 haplotype data clock signal A1 and N haplotype data is generated by digital NCO
Clock signal AN；Input signal is received according to the data clock signal A1；Using data clock signal AN to receiving
Signal carries out N times of zero padding interpolation；It is filtered using signal after digital fabrication filter interpolation；To the letter after molding filtration
Number carry out variable sampling rate filtering interpolation processing.The formed filter of fixed coefficient and inserting for variable coefficient is respectively adopted in this method
Value filter carries out molding filtration and filtering interpolation processing, and the molding filtration and filtering interpolation of different rates signal may be implemented,
It can be applied to the digital modulator of data rate continuous variable.This method can obtain the number of high power when handling low-speed applications
According to clock signal AN, but it is directed to this method application background, data rate needs for processing clock rate in further
The case where improving rate is inserted, then can not be applied.
Document " a kind of score times interpolation formed filter and its implementation method " proposes a kind of score times interpolation molding filter
Wave device and its implementation.The score times interpolation formed filter includes data simultaneous module, region filtering module, resampling mould
Block, digital controlled oscillator control module.Digital controlled oscillator control module generates slow overflow indicator according to the input of baseband modulation rate and send
Slow synchrodata output is generated to data simultaneous module, slow synchrodata output is defeated by region filtering module generation filter group
Go out, the output of filter group and fast overflow indicator and fractional time delay filter time delay generate molding filtration number by resampling module
According to.The offset dynamic that this method is not obtained by timing offset adjusts the data of sampling instant, at the same filter structure according to
It is so Polynomial Filter structure.
Invention content
The technology of the present invention solves the problems, such as：Overcome the deficiencies of the prior art and provide a kind of integration compensation digital filtering
Device design method, the thinking of use is to utilize " more accurate " information (improving sample rate) completion timing estimation of deviation, with the estimation
Value complement repays the timing phase control word of NCO, to ensure the required precision of observing and controlling.In realization, by variable Rate filtering
The factor is inserted, completes to improve the accurate compensation of data after sample rate, Measure Precision is more demanding if interpolation factor is smaller, can be with
Further increase interpolation multiple；If Measure Precision requirement is low, relatively low interpolation factor is used.
The technical scheme is that：A kind of integration compensation digital filter design method, it is characterised in that：Including
(1) filter coefficient is designed, the inhibition completed to down coversion high fdrequency component is taken into account, to for formed filter of starting
The anti-aliasing filter matched and variable Rate is handled；
(2) it is stored after being recombinated to filter coefficient, wherein the recombination form adapts to different rates as far as possible, simultaneously
It is easy to the realization of parallel computation；
(3) the valid data length for participating in operation and the data amount check for carrying out sampled data recovery are calculated, is completed corresponding
Filter be multiplexed operation；
(4) compensation is completed using the offset information that bit timing obtains, which includes to participating in filtering operation system
Compensation two parts of several compensation and input data；
(5) according to the coefficient and data after adjustment, last filtering knot is completed using the realization method of parallel plus flowing water mixing
The calculating of fruit.
The specific method of design filter coefficient is in the step (1)：
11) root raised cosine filter is designed, three dB bandwidth is selected as the half of system symbol rate；
12) filter order is Z, and Z is even number, then coefficient number is：L=Z+1；The last one coefficient is repeated one
It is secondary, obtain final coefficient number L_all=L+1=Z+2.
The specific method of the step (2) is：
21) assume the variable Rate factor be P/Q, if the system need to support be between a variety of character rates and several rates
2 power multiple proportion then selects minimum rate shelves, i.e. one group of interpolation factor Pmin of interpolation multiple minimum, this group of interpolation
The factor is the address size that is stored as filter coefficient, and corresponding address is (0 ..., Pmin-1)；
22) interval M=fs of the sampling rate f_sample of system at system clock f_clk is calculatedclk/fsambol；
And then it obtains for filtering the pipeline processes period M'≤M calculated；The multiplier resources number N_ that one clock cycle needs
The number of mul=L_all/M', that is, the filter coefficient needed are at least N_mul；
23) the data amount check D=L_all/P for participating in operation is calculatedmin, calculate the data bit width W of address storage
=D × W0；Wherein, W0For the quantization bit wide of a filter coefficient；By the way of respectively n sections, it is stored in different memories
In, i.e. D=[D_p1,D_p2,…,D_pn], wherein D_pnIt is the data length of each memory storage, by the way of dividing equally,
Each section of data amount check is：The length of D_p=D/n, D_p are more than N_mul；
24) filter coefficient of entire L_all length is recombinated, forms data after the recombination of P_min rows D row；It will
The data are uniformly split as n sections, and every section is P_min rows, and the coefficient matrix of D_p row is respectively stored in n memory.
The specific method of the step (3) is：
31) restore the required valid data number D of operation and adjacent need to count according to participating in currently enabled position data
According to the interval M of the timing position of recovery, the number of filter N_f >=D/M for needing parallel processing is calculated；
32) it is input N_f different numbers of enabled addition, is recycled from 1 to N_f, enabled under difference number independently gathers around
There are oneself data address, coefficient address and control signal.
The specific method of the step (4) is：
41) each clock cycle is sub-divided into Pmin position, i.e. 0~Pmin-1, it is assumed that valid data are in
The last one position Pmin-1；
42) each clock cycle is compensated respectively according to the different enabled lower different offset information Phase_in inputted
Filtering calculate, adjustment participate in filtering operation filter coefficient；
43) each clock cycle is compensated respectively according to the different enabled lower different offset information Phase_in inputted
Calculating, adjustment participate in filtering operation input data.
The specific method of the step (5) is：
51) clock cycle under each enabled number is counted, until next time identical enabled number arrives clearly
0；
52) the L_all/2-1 period positions after the data under currently calculative enable arrive, it is dynamic according to front
The data that state adjusts read initial address Rd_begin_addr, read and need participation present clock period operation after adjustment
Data；
The data amount check that operation is participated under the same clock cycle is multiplier number N_mul=L_all/M'；Wherein M'
For for filtering the clock cycle calculated；At least N_mul input data, a cycle is then needed to read address under the period
Rd_addr values are：
Rd_begin_addr~Rd_begin_addr+ (N_mul-1)
The second period clock cycle reads address Rd_addr values：
Rd_begin_addr+N_mul~Rd_begin_addr+ (2 × N_mul-1)
The rest may be inferred, is read after the M' period：
Rd_begin_addr+ (M'-1) × N_mul~Rd_begin_addr+ (M' × N_mul-1)；
53) the reading address Coe_addr of obtained coefficient memory is dynamically adjusted according to front, reads the needs after adjustment
Participate in the filter coefficient of current enabled operation；The coefficient read out is all coefficients for participating in the enabled operation, is carried out
It splits and takes out, coefficient and the data read out above correspond under each clock cycle；
54) each enabled lower data filtering calculates independent control, completes entire filtering operation；
55) entire processing delay is calculated, it is enabled to obtain the output inputted after enabling delay fixing process time delay.
Adjustment participates in the filter coefficient of filtering operation in the step 42), and specific method of adjustment is as follows：
If the offset information received is：Phase_in=0, then it is assumed that currently enabled position is accurate, need not adjust
Whole filter coefficient positions, center are still directed at the positions Pmin-1 under each clock cycle, and wherein Phase_in is to return
The one offset information changed, specific value are 0~Pmin-1；The then address Coe_addr=P_min- of filter coefficient storage
1；
If the offset information received meets：1≤Phase_in≤P_min-1 then shows to indicate that reality is most preferably adopted
Sampling point is located at the Phase_in, left side position, this position should be aligned filter most middle coefficient, store at this time in the calculation
In the reading address Coe_addr=Phase_in-1 of coefficient memory；
Adjustment participates in the input data of filtering operation in the step 43), and specific method of adjustment is as follows：
If the offset information received is：Phase_in=0, then it is assumed that currently enabled position is accurate, need not adjust
The whole data for participating in operation, then the starting reading address Rd_begin_addr of data is identical as before compensation, i.e.,：
Wherein L_all is still total filter coefficient, and Wr_addr is corresponding currently to need the data of Timed Recovery to enable
Write address；If currently writing ground Wr_addr<(L_all/2-1), then it needs to add address cycle length L_ram；
If the offset information received meets：1≤Phase_in≤P_min-1 then shows practical optimum sampling point
Positioned at the Phase_in, left side position, when calculating, address Rd_begin_addr relative complements are read in the starting of data for this position
Reduce an address before repaying, i.e.,：
The advantages of the present invention over the prior art are that：
(1) the down coversion low-pass filter, matched filter, variable Rate frequency overlapped-resistable filter of the invention by receiver front end
And the fusion of sign synchronization interpolation filter function, need not further according to systematic parameter individually to each filter independent design,
But according to integrated design thinking, a filter completes all above-mentioned filter functions, simplifies realization structure, enhance
System versatility, reduces design complexities.
(2) present invention be applied to closed loop feedback timing recovery method, this method by means of variable Rate filter interpolation because
Son (or variable Rate interpolation multiple it is smaller when, interpolation factor can be further increased) improve sample rate post filtering, obtain higher
The data (improving sample rate) of precision adjust NCO phases letter in real time to obtain smaller timing offset information with the information
Breath, to complete the application demand of high-precision observing and controlling.
(3) this method need not be introduced separately into based on polynomial interpolation filter, nor using the side of curve matching
Method completes data reconstruction, by the compensation to data to obtain the data of higher precision (smaller timing offset), then carries out " choosing
The operation of point " is completed.Additional multinomial operation need not be introduced to can be completed.
Description of the drawings
Fig. 1 receiver front end structural schematic diagrams using the present invention；
Fig. 2 schematic structural views of the invention；
Fig. 3 filter coefficients of the present invention store schematic diagram；
Fig. 4 filter filtering operation schematic diagrames of the present invention；
Fig. 5 filter calibration schematic diagrames of the present invention；
Specific implementation mode
As shown in Figs. 1-5, the present invention that specific implementation step it is as follows：
1, the design to filter coefficient and storage are completed first, specifically consider the following aspects：
11) root raised cosine filter is designed, being molded the selection of the factor will keep the selection with transmitter molding filtration consistent,
Three dB bandwidth is selected as the half of character rate, completes the generation of filter coefficient.The filter order is Z, and Z is even number, then is
Several numbers are：L=Z+1；The last one coefficient is repeated once, obtaining final coefficient number L_all is：L_all=L+1=
Z+2。
12) assume the variable Rate factor be P/Q, if the system need to support be between a variety of character rates and several rates
2 power multiple proportion, then select minimum rate shelves namely one group of interpolation factor Pmin of interpolation multiple minimum, in the group
It is the address size that is stored as filter coefficient to insert the factor, and corresponding address is (0 ..., Pmin-1)；
13) M=f is divided between according to the sampling rate f_sample of system at system clock f_clkclk/fsambol；Then
For filtering the pipeline processes period M'≤M calculated；The multiplier resources number that one clock cycle needs is N_mul=L_
All/M', therefore the number of the filter coefficient needed is at least N_mul；
14) the data amount check D=L_all/P for participating in operation is calculatedmin, calculate the data bit width W of address storage
=D × W0；Wherein, W0For the quantization bit wide of a filter coefficient；By the way of respectively n sections, it is stored in different memories
In, i.e. D=[D_p1,D_p2,…,D_pn], wherein D_pnIt is the data length of each memory storage, general use is divided equally here
Mode, each section of data amount check is：The length of D_p=D/n, D_p should be greater than N_mul；
15) filter coefficient of entire L_all length is recombinated, forms data after the recombination of P_min rows D row；It will
The data are uniformly split as n sections, and every section is P_min rows, and the coefficient matrix of D_p row is respectively stored in n memory.
2, the compensation for completing the filter coefficient and data to participating in filtering operation, the specific steps are：
21) the enabled and data that the alignment of the centre position of entire filter order is currently needed to participation operation, due to this
When input data rate be equal to processing clock rate, must further interpolation (inserting 0) on this basis when calculating, it is assumed that each when
The clock period is sub-divided into Pmin position (0~Pmin-1), and the valid data in each period are in the last one position
Pmin-1.Therefore that the center alignment of the filter coefficient is exactly the last one position Pmin-1 currently enabled.
22) each clock cycle is compensated respectively according to the different enabled lower different offset information Phase_in inputted
Filtering calculate, adjustment participates in the filter coefficient of filtering operation, and specific method of adjustment is as follows：
If the offset information received is：Phase_in=0, then it is assumed that currently enabled position is accurate, need not adjust
Whole filter coefficient positions, center are still directed at the positions Pmin-1 under each clock cycle, and wherein Phase_in is to return
The one offset information changed, specific value are Pmin,；The then address Coe_addr=P_min-1 of filter coefficient storage；
If the offset information received meets：1≤Phase_in≤P_min-1 then shows to indicate that reality is most preferably adopted
Sampling point is located at the Phase_in, left side position, this position should be aligned filter most middle coefficient, store at this time in the calculation
In the reading address Coe_addr=Phase_in-1 of coefficient memory；
23) each clock cycle is compensated respectively according to the different enabled lower different offset information Phase_in inputted
Calculating, adjustment participates in the input data of filtering operation, and specific method of adjustment is as follows：
If the offset information received is：Phase_in=0, then it is assumed that currently enabled position is accurate, need not adjust
The whole data for participating in operation, then the starting reading address Rd_begin_addr of data is identical as before compensation, i.e.,：
Wherein L_all is still total filter coefficient, and Wr_addr is corresponding currently to need the data of Timed Recovery to enable
Write address；If currently writing ground Wr_addr<(L_all/2-1), then it needs to add address cycle length L_ram；
If the offset information received meets：1≤Phase_in≤P_min-1 then shows practical optimum sampling point
Positioned at the Phase_in, left side position, when calculating, address Rd_begin_addr relative complements are read in the starting of data for this position
Reduce an address before repaying, i.e.,：
24) the L_all/2-1 period positions after the data under currently calculative enable arrive, it is dynamic according to front
The data that state adjusts read initial address Rd_begin_addr, read and need participation present clock period operation after adjustment
Data；
The data amount check that operation is participated under the same clock cycle is multiplier number N_mul=L_all/M'；Wherein M'
For for filtering the clock cycle calculated；At least N_mul input data, a cycle is then needed to read address under the period
Rd_addr values are：
Rd_begin_addr~Rd_begin_addr+ (N_mul-1)
The second period clock cycle reads address Rd_addr values：
Rd_begin_addr+N_mul~Rd_begin_addr+ (2 × N_mul-1)
The rest may be inferred, is read after the M' period：
Rd_begin_addr+ (M'-1) × N_mul~Rd_begin_addr+ (M' × N_mul-1)
3, the control to filtering operation process is completed：
31) the reading address Coe_addr of obtained coefficient memory is dynamically adjusted according to front, reads the needs after adjustment
Participate in the filter coefficient of current enabled operation；The coefficient read out is all coefficients for participating in the enabled operation, is carried out
It splits and takes out, coefficient and the data read out above correspond under each clock cycle；
32) restore the required valid data number D of operation and adjacent need to count according to participating in currently enabled position data
According to the interval M of the timing position of recovery, the number of filter N_f >=D/M for needing parallel processing is calculated；
33) it is input N_f different numbers of enabled addition, is recycled from 1 to N_f, enabled under difference number independently gathers around
There are oneself data address, coefficient address and control signal.
34) each enabled lower data filtering calculates independent control, completes entire filtering operation；
35) entire processing delay is calculated, it is enabled to obtain the output inputted after enabling delay fixing process time delay.
2. case study on implementation
It is assumed that system clock f_clk=83.961MHz, system symbol rate f_symbol1=1.573632Msps and f_
Symbol2=3.147264Msps samples multiple N=4, is molded factor-alpha=0.35.
Integration compensation digital filter design is carried out using the present invention to be as follows：
(1) design of filter coefficient is completed by the FDATOOL tools of MATLAB：
Step 1：Filter mode uses root raised cosine filter, forming coefficients to be set as 0.35 first.
Step 2：It is filtered the calculating of device input sampling rate.According to the character rate f_symbol1=of system
Relationship between 1.573632Msps and f_symbol2=3.147264Msps and system clock f_clk=83.961MHz,
Determine that the value of accurate variable Rate factor P/Q is 32/427 (being directed to f_symbol1) and 64/427 (being directed to f_symbol2).
The smaller interpolation factor Pmin=32 of selection.Then the data sampling rate into filter after interpolation is 2686.752MHz.
Step 3：The half that three dB bandwidth fc is character rate, i.e. 0.786816MHz are set.
Step 4：Filter overall coefficient is thought of as interpolation factor integral multiple, and exponent number is set as 4094 ranks, the filter actually generated
Wave device coefficient length is 4095, and final filter coefficient is once become 4096 by the extension of the last one coefficient, within meeting
The demand for inserting factor integral multiple, facilitates subsequent calculations to handle.
Step 5：If individually according to 32 row, 128 row packing coefficient, the coefficient bit wide of individual address is 128x12=
1536bit, bit wide is wide, and process resource occupied, and takes segment processing.It is adjacent it is enabled between be divided into f_clk/ (f_symbol1*
4)=13.34,8 clock cycle is selected to be multiplexed.In view of interpolation multiple is 32 times, the practical ginseng of 4096 filter coefficients
Reality with operation is 4096/32=128, is multiplexed according to 8 clock cycle, then needs parallel computation under a clock cycle
128/8=16 data.Then the filter coefficient bit wide of address storage at least should be greater than 16*12=192.Final choice will
Coefficient is stored according to 4 sections, and every section is 32 row, 384 bit wide.
(2) filtering operation is completed after being compensated by the offset of bit timing, to realize the number at accurate timing moment
According to recovery, it is assumed that each clock cycle is sub-divided into 32 positions (0~31), and the valid data in each period are located
In the last one position 31.Therefore the center alignment of the filter coefficient is exactly the last one position 31 currently enabled.Root
It compensates and is as follows according to the offset of the bit timing of input：
Step 1：The compensation control of filter coefficient is completed first.Currently enabling corresponding offset information is
Phase_in need not adjust filter coefficient position, centre bit if Phase_in=0 thinks currently to enable position accurate
Set 31 positions being still aligned under each clock cycle, therefore the address coe_addr=31 of filter coefficient storage；If 1≤
Phase_in≤31 then show that practical optimum sampling point is located at the Phase_in, left side position, this position in the calculation should
It is aligned filter most middle coefficient, the reading address coe_addr for being stored in coefficient memory at this time should be：
Coe_addr=Phase_in-1
Step 2：The compensation for completing to participate in the data of operation controls.If Phase_in=0 thinks currently to enable position standard
Really, filter coefficient position need not be adjusted, center is still directed at 31 positions under each clock cycle, therefore participates in fortune
It is identical as the address before compensation that address Rd_begin_addr is read in the starting of the data of calculation：
L_ram is the depth for the RAM for storing data.
If the offset information received meets：1≤Phase_in≤31
Then show to indicate that practical optimum sampling point is located at the Phase_in, left side position, this position when calculating, due to
Starting newly introduces data and participates in calculating, therefore to subtract before the opposite compensation of starting reading address Rd_begin_addr of data
A small address：
(3) independent process is enabled to each, since the valid data that a filter result participates in operation are 128, and
Enabled interval by the step five in front (1) can be 13.34, it is therefore desirable to enabled number at least more than 128/13.34=
9.6, take number 1~10 to be multiplexed；It is 83.961MHz's due to calculating the data under current enable to need 128 sample rates
Data participate in operation, therefore after current enabled arrival, and at least equal 64 periods is needed to carry out operation again.Calculating process uses 8
A clock cycle multiplexing, therefore each clock cycle control 16 coefficients of reading are multiplied with data completion, follow-up add up obtains most
Whole filter result.
Unspecified part of the present invention belongs to common sense well known to those skilled in the art.
Claims (8)
1. a kind of integration compensation digital filter design method, it is characterised in that：Including
(1) design filter coefficient, take into account and complete inhibition to down coversion high fdrequency component, to the matching of formed filter of starting with
And the anti-aliasing filter to variable Rate processing；
(2) it stores after being recombinated to filter coefficient, wherein the recombination form adapts to different rates as far as possible, is easy to simultaneously
The realization of parallel computation；
(3) the valid data length for participating in operation and the data amount check for carrying out sampled data recovery are calculated, corresponding filter is completed
Wave device is multiplexed operation；
(4) compensation is completed using the offset information that bit timing obtains, which includes the coefficient to participating in filtering operation
Compensation two parts of compensation and input data；
(5) according to the coefficient and data after adjustment, last filter result is completed using the realization method of parallel plus flowing water mixing
It calculates.
2. the digital filter design method of integration compensation according to claim 1, it is characterised in that：The step
(1) specific method of design filter coefficient is in：
11) root raised cosine filter is designed, three dB bandwidth is selected as the half of system symbol rate；
12) filter order is Z, and Z is even number, then coefficient number is：L=Z+1；The last one coefficient is repeated once, is obtained
To final coefficient number L_all=L+1=Z+2.
3. a kind of integration compensation digital filter design method according to claim 2, it is characterised in that：The step
(2) specific method is：
21) assume that the variable Rate factor is P/Q, if the system needs to support to be 2 between a variety of character rates and several rates
Power multiple proportion then selects minimum rate shelves, i.e. one group of interpolation factor Pmin of interpolation multiple minimum, this group of interpolation factor
Address size i.e. as filter coefficient storage, corresponding address are (0 ..., Pmin-1)；
22) interval M=fs of the sampling rate f_sample of system at system clock f_clk is calculatedclk/fsambol；In turn
It obtains for filtering the pipeline processes period M'≤M calculated；The multiplier resources number N_mul=that one clock cycle needs
The number of L_all/M', that is, the filter coefficient needed are at least N_mul；
23) the data amount check D=L_all/P for participating in operation is calculatedmin, calculate the data bit width W=D of address storage
×W0；Wherein, W0For the quantization bit wide of a filter coefficient；By the way of respectively n sections, it is stored in different memories,
That is D=[D_p1,D_p2,…,D_pn], wherein D_pnIt is the data length of each memory storage, it is each by the way of dividing equally
Section data amount check be：The length of D_p=D/n, D_p are more than N_mul；
24) filter coefficient of entire L_all length is recombinated, forms data after the recombination of P_min rows D row；By the number
According to being uniformly split as n sections, every section is P_min rows, and the coefficient matrix of D_p row is respectively stored in n memory.
4. a kind of integration compensation digital filter design method according to claim 2, it is characterised in that：The step
(3) specific method is：
31) restore the required valid data number D of operation and adjacent need data extensive according to participating in currently enabled position data
The interval M of multiple timing position calculates the number of filter N_f >=D/M for needing parallel processing；
32) it is input N_f different numbers of enabled addition, is recycled from 1 to N_f, lower enabled of difference number independently possesses certainly
Oneself data address, coefficient address and control signal.
5. a kind of integration compensation digital filter design method according to claim 2, it is characterised in that：The step
(4) specific method is：
41) each clock cycle is sub-divided into Pmin position, i.e. 0~Pmin-1, it is assumed that valid data are i.e. in last
One position Pmin-1；
42) filter of each clock cycle is compensated respectively according to the different enabled lower different offset information Phase_in inputted
Wave calculates, and adjustment participates in the filter coefficient of filtering operation；
43) meter of each clock cycle is compensated respectively according to the different enabled lower different offset information Phase_in inputted
It calculates, adjustment participates in the input data of filtering operation.
6. a kind of integration compensation digital filter design method according to claim 2, it is characterised in that：The step
(5) specific method is：
51) clock cycle under each enabled number is counted, until next time identical enabled number arrival clear 0；
52) the L_all/2-1 period positions after the data under currently calculative enable arrive are adjusted according to front dynamic
Whole obtained data read initial address Rd_begin_addr, read the number for needing to participate in present clock period operation after adjustment
According to；
The data amount check that operation is participated under the same clock cycle is multiplier number N_mul=L_all/M'；Wherein M' is to use
In the clock cycle that filtering calculates；At least N_mul input data, a cycle is then needed to read address Rd_ under the period
Addr values are：
Rd_begin_addr~Rd_begin_addr+ (N_mul-1)
The second period clock cycle reads address Rd_addr values：
Rd_begin_addr+N_mul~Rd_begin_addr+ (2 × N_mul-1)
The rest may be inferred, is read after the M' period：
Rd_begin_addr+ (M'-1) × N_mul~Rd_begin_addr+ (M' × N_mul-1)；
53) the reading address Coe_addr of obtained coefficient memory is dynamically adjusted according to front, is read and is needed to participate in after adjustment
The filter coefficient of current enabled operation；The coefficient read out is all coefficients for participating in the enabled operation, is split
It takes out, coefficient and the data read out above correspond under each clock cycle；
54) each enabled lower data filtering calculates independent control, completes entire filtering operation；
55) entire processing delay is calculated, it is enabled to obtain the output inputted after enabling delay fixing process time delay.
7. a kind of integration compensation digital filter design method according to claim 5, it is characterised in that：The step
42) adjustment participates in the filter coefficient of filtering operation in, and specific method of adjustment is as follows：
If the offset information received is：Phase_in=0, then it is assumed that currently enabled position is accurate, need not adjust filter
Wave device coefficient positions, center are still directed at the positions Pmin-1 under each clock cycle, and wherein Phase_in is normalization
Offset information, specific value be 0~Pmin-1；The then address Coe_addr=P_min-1 of filter coefficient storage；
If the offset information received meets：1≤Phase_in≤P_min-1 then shows to indicate practical optimum sampling point
Positioned at the Phase_in, left side position, this position should be aligned filter most middle coefficient in the calculation, be stored at this time and be
The reading address Coe_addr=Phase_in-1 of number memory.
8. a kind of integration compensation digital filter design method according to claim 5, it is characterised in that：The step
43) adjustment participates in the input data of filtering operation in, and specific method of adjustment is as follows：
If the offset information received is：Phase_in=0, then it is assumed that currently enabled position is accurate, need not adjust ginseng
With the data of operation, then the starting reading address Rd_begin_addr of data is identical as before compensation, i.e.,：
Wherein L_all is still total filter coefficient, and Wr_addr is that the data of Timed Recovery is currently needed to enable corresponding to write ground
Location；If currently writing ground Wr_addr<(L_all/2-1), then it needs to add address cycle length L_ram；
If the offset information received meets：1≤Phase_in≤P_min-1 then shows that practical optimum sampling point is located at
The Phase_in, left side position, when calculating, the starting of data reads address Rd_begin_addr and compensates it relatively for this position
One address of preceding reduction, i.e.,：
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