CN108630683A

CN108630683A - Semiconductor structure and forming method thereof

Info

Publication number: CN108630683A
Application number: CN201710175999.7A
Authority: CN
Inventors: 李勇
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-03-22
Filing date: 2017-03-22
Publication date: 2018-10-09
Anticipated expiration: 2037-03-22
Also published as: CN108630683B

Abstract

A kind of semiconductor structure and forming method thereof, method includes：Offer includes the substrate of NMOS area；Gate structure is formed in substrate；The areas N groove is formed in the substrate of gate structure both sides；The areas N doped epitaxial floor is formed in the areas N groove, the areas N doped epitaxial floor is the laminated construction that the first n-type doping epitaxial layer and the second n-type doping epitaxial layer are constituted, first n-type doping epitaxial layer is the first epitaxial layer doped with N-type ion, second n-type doping epitaxial layer is the second epitaxial layer doped with N-type ion, and the energy gap of the second epitaxial layer is less than the energy gap of the first epitaxial layer；Interlayer dielectric layer is formed on the areas N doped epitaxial floor；The first contact openings for exposing the areas N doped epitaxial floor are formed in interlayer dielectric layer；The first contact hole plug is formed in the first contact openings.The present invention doped with the second epitaxial layer of N-type ion by, to reduce schottky barrier height, and improving the N-type ion concentration of the areas N doped epitaxial floor, to reduce contact resistance.

Description

Semiconductor structure and forming method thereof

Technical field

The present invention relates to semiconductor applications more particularly to a kind of semiconductor structure and forming method thereof.

Background technology

With the continuous development of ic manufacturing technology, requirement of the people to the integrated level and performance of integrated circuit becomes It is higher and higher.In order to improve integrated level, cost is reduced, the critical size of component constantly becomes smaller, the circuit of IC interior Density is increasing, and this development is so that crystal column surface can not provide enough areas to make required interconnection line.

In order to meet needed for the interconnection line after critical dimension reduction, different metal layer or metal layer and substrate at present Conducting is realized by interconnection structure.Interconnection structure includes interconnection line and the contact hole plug that is formed in contact openings.It connects Contact hole plug is connected with semiconductor devices, and interconnection line realizes the connection between contact hole plug, to constitute circuit.

Contact hole plug in transistor arrangement includes the contact hole plug positioned at gate structure surface, for realizing grid The connection of structure and external circuit；And the contact hole plug positioned at source and drain doping area surface, for realizing transistor source region or The connection in drain region and external circuit.

Due to constantly becoming smaller for device critical dimensions, the contact zone area in the contact hole plug and source and drain doping area is not yet Disconnected to reduce, the reduction of contact zone area accordingly leads to the increase of contact resistance, so as to cause the reduction of device drive current, in turn Lead to the performance degradation of semiconductor devices.Therefore, in order to reduce contact resistance to improve driving current, the side mainly used at present Formula is：In the position of contact hole plug to be formed, corresponding substrate surface forms metal silicide layer, to reduce contact zone Contact resistance.

But using metal silicide layer technology after, the electric property of formed semiconductor structure is still to be improved.

Invention content

Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, improves the electricity of semiconductor structure Performance.

To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Substrate is provided, it is described Substrate includes being used to form the NMOS area of N-type device；Gate structure is formed on the substrate；In the NMOS area grid The areas N groove is formed in the substrate of structure both sides；The areas N doped epitaxial floor, the areas N doped epitaxial are formed in the areas N groove Layer is the laminated construction that the first n-type doping epitaxial layer and the second n-type doping epitaxial layer are constituted, wherein outside first n-type doping It is the first epitaxial layer doped with N-type ion to prolong layer, and the second n-type doping epitaxial layer is doped with outside the second of N-type ion Prolong layer, the energy gap of second epitaxial layer is less than the energy gap of first epitaxial layer；In the areas the N doped epitaxial floor Upper formation interlayer dielectric layer；It is formed in the interlayer dielectric layer of the NMOS area and exposes the first of the areas the N doped epitaxial floor Contact openings；The first contact hole plug being electrically connected with the areas the N doped epitaxial floor is formed in first contact openings.

Correspondingly, the present invention also provides a kind of semiconductor structures, including：Substrate, the substrate include having N-type device NMOS area；Gate structure is located in the substrate；It is adulterated positioned at the intrabasement areas N in NMOS area gate structure both sides Epitaxial layer, the areas the N doped epitaxial floor are the laminated construction that the first n-type doping epitaxial layer and the second n-type doping epitaxial layer are constituted, Wherein, the first n-type doping epitaxial layer is the first epitaxial layer doped with N-type ion, and the second n-type doping epitaxial layer is Doped with the second epitaxial layer of N-type ion, the energy gap of second epitaxial layer is wide less than the forbidden band of first epitaxial layer Degree；Interlayer dielectric layer is located on the areas the N doped epitaxial floor；First contact hole plug, the interlayer through the NMOS area are situated between It matter floor and is electrically connected with the areas the N doped epitaxial floor.

Compared with prior art, technical scheme of the present invention has the following advantages：

The present invention provides a kind of forming method of semiconductor structure, including：Substrate in NMOS area gate structure both sides The interior areas formation N groove；The areas N doped epitaxial floor is formed in the areas N groove, the areas the N doped epitaxial floor is the first n-type doping The laminated construction that epitaxial layer and the second n-type doping epitaxial layer are constituted, wherein the first n-type doping epitaxial layer is doped with N-type First epitaxial layer of ion, the second n-type doping epitaxial layer is the second epitaxial layer doped with N-type ion, outside described second The energy gap for prolonging layer is less than the energy gap of first epitaxial layer.Include doping with the areas N doped epitaxial floor is formed by only There is the scheme of the first epitaxial layer of N-type ion to compare, since the energy gap of the second epitaxial layer is smaller, the present invention passes through institute The second epitaxial layer is stated, the schottky barrier height (Schottky of the areas the N doped epitaxial floor and channel region is advantageously reduced Barrier Height, SBH)；In addition, the Doped ions of the second n-type doping epitaxial layer are N-type ion, the areas N is made to mix N-type ion concentration in miscellaneous epitaxial layer is improved；Since contact resistance is directly proportional to schottky barrier height, and with N-type from Sub- concentration is inversely proportional, therefore scheme of the present invention can reduce contact resistance, to improve the driving electricity of formed N-type device Stream, to make the electric property of the semiconductor structure be improved.

In alternative, the step of forming the areas the N doped epitaxial floor, includes：It is formed outside first in the areas N groove Prolong layer；To the first epitaxial layer doped N-type ion, the first n-type doping epitaxial layer is formed；In the first n-type doping extension The second epitaxial layer is formed on layer；To the second epitaxial layer doped N-type ion, the second n-type doping epitaxial layer is formed；Described second N-type doping epitaxial layer and the first n-type doping epitaxial layer constitute the areas N doped epitaxial floor.The material of second epitaxial layer is SiGe, and the material of the usually areas P doped epitaxial floor is the SiGe doped with p-type ion, subsequently in the interlayer of the NMOS area In the step of forming the first contact openings for exposing the areas the N doped epitaxial floor in dielectric layer, first contact openings also shape In the interlayer dielectric layer of PMOS area described in Cheng Yu and expose the areas the P doped epitaxial floor, and the NMOS area first contacts Opening exposes second epitaxial layer, the material that the first contact openings of the NMOS area and the first contact openings of PMOS area expose Expect identical, be SiGe, therefore is conducive to optimize the formation process of first contact openings and follow-up first contact hole is inserted The formation process of plug.

The present invention provides a kind of semiconductor structure, and the semiconductor structure includes being located at the NMOS area gate structure two The intrabasement areas the N doped epitaxial floor in side, the areas the N doped epitaxial floor are the first n-type doping epitaxial layer and the second n-type doping extension The laminated construction that layer is constituted, wherein the first n-type doping epitaxial layer is the first epitaxial layer doped with N-type ion, described the Two n-type doping epitaxial layers are the second epitaxial layer doped with N-type ion, and the energy gap of second epitaxial layer is less than described the The energy gap of one epitaxial layer.Compared with the areas N, doped epitaxial floor only includes the scheme doped with the first epitaxial layer of N-type ion, Since the energy gap of the second epitaxial layer is smaller, the present invention can reduce the areas the N doping by second epitaxial layer The schottky barrier height of epitaxial layer and channel region；In addition, the Doped ions of the second n-type doping epitaxial layer are N-type ion, The N-type ion concentration in the areas the N doped epitaxial floor is set to be improved；Since contact resistance and schottky barrier height are at just Than, and be inversely proportional with N-type ion concentration, therefore the contact resistance of semiconductor structure of the present invention is smaller, accordingly makes N-type device Driving current be improved, to make the electric property of the semiconductor structure be improved.

Description of the drawings

Fig. 1 to Figure 29 be semiconductor structure of the present invention one embodiment of forming method in each step counter structure schematic diagram；

Figure 30 to Figure 32 is the structural schematic diagram of one embodiment of semiconductor structure of the present invention.

Specific implementation mode

Parasitic non-essential resistance (Rext) is a key factor for influencing semiconductor structure electric property；Wherein, parasitic outer Mainly by the contact resistance between contact hole plug and source and drain doping area, ((ρ c) is influenced portion's resistance.Therefore, it is connect to reduce Get an electric shock resistance to improve driving current, the mode mainly used for：In the corresponding substrate table in the position of contact hole plug to be formed Face forms metal silicide layer, to reduce the contact resistance of contact zone.

But even if after using metal silicide layer technology, the electric property of formed semiconductor structure is still to be improved.

In order to solve the technical problem, the present invention provides a kind of forming method of semiconductor structure, including：In NMOS area The areas N groove is formed in the substrate of domain gate structure both sides；The areas N doped epitaxial floor is formed in the areas N groove, the areas N are mixed Miscellaneous epitaxial layer is the laminated construction that the first n-type doping epitaxial layer and the second n-type doping epitaxial layer are constituted, wherein first N-type Doped epitaxial layer is the first epitaxial layer doped with N-type ion, and the second n-type doping epitaxial layer is doped with N-type ion Second epitaxial layer, the energy gap of second epitaxial layer are less than the energy gap of first epitaxial layer.Be formed by the areas N Doped epitaxial layer only includes being compared doped with the scheme of the first epitaxial layer of N-type ion, due to the energy gap of the second epitaxial layer It is smaller, therefore the present invention advantageously reduces the Schottky of the areas N the doped epitaxial floor and channel region by second epitaxial layer Barrier height；In addition, the Doped ions of the second n-type doping epitaxial layer are N-type ion, make in the areas the N doped epitaxial floor N-type ion concentration be improved；Since contact resistance is directly proportional to schottky barrier height, and with N-type ion concentration at anti- Than, therefore scheme of the present invention can reduce contact resistance, to improve the driving current of formed N-type device, to make The electric property for stating semiconductor structure is improved.

To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.

Fig. 1 to Figure 29 be semiconductor structure of the present invention one embodiment of forming method in each step counter structure schematic diagram.

In conjunction with being stereogram (only illustrating two fins) with reference to figure 1 and Fig. 2, Fig. 1, Fig. 2 is Fig. 1 cuing open along AA1 secants Face figure, provides substrate (not indicating), and the substrate includes being used to form the NMOS area II (as shown in Figure 2) of N-type device.

The substrate provides technique platform to be subsequently formed semiconductor structure.

In the present embodiment, the substrate is used to form fin formula field effect transistor, therefore in the step of providing substrate, described Substrate includes substrate 100 and discrete fin on the substrate 100 (not indicating).In other embodiments, the base Bottom is used to form planar transistor, correspondingly, the substrate is planar substrate.

The substrate 100 provides technique platform to be subsequently formed semiconductor structure, and the fin is for providing formed fin The raceway groove of formula field-effect transistor.

In the present embodiment, for being formed by fin formula field effect transistor and be cmos device, the substrate 100 not only wraps The NMOS area II for being used to form N-type device is included, further includes the PMOS area I (as shown in Figure 2) for being used to form P-type device, institute It states and all has discrete fin on the substrate 100 of PMOS area I and NMOS area II.Specifically, it is located at the PMOS area I to serve as a contrast Fin on bottom 100 is the first fin 110, and it is the second fin 120 to be located at the fin on the NMOS area II substrates 100.

In other embodiments, be formed by fin formula field effect transistor can only include NMOS device when, the substrate It only include accordingly NMOS area.

In the present embodiment, the PMOS area I and NMOS area II are adjacent area.In other embodiments, described PMOS area and NMOS area can also be isolated.

In order to improve the carrier mobility of formed semiconductor devices, the substrate is germanic substrate.In the present embodiment, The germanic substrate is germanium substrate, correspondingly, the material of the substrate 100 is germanium.In other embodiments, the germanic substrate Material can also be SiGe, the germanic substrate can also be insulator on germanium substrate.The material of the substrate can be with Choose the material for being suitable for process requirements or being easily integrated.

In other embodiments, the material of the substrate can also be monocrystalline silicon, multicrystalline silicon substrate, amorphous silicon substrate or Germanium silicon substrate, carbon silicon substrate, silicon-on-insulator substrate, germanium substrate on insulator, glass substrate or III-V compound lining Bottom, such as gallium nitride substrate or gallium arsenide substrate etc.；The material of the substrate, which can be chosen, to be suitable for process requirements or is easy to collect At material.

The material identical of the material of the fin and the substrate 100.Therefore, in the present embodiment, the material of the fin Material for germanium, i.e., described first fin, 110 and second fin 120 is germanium.

Specifically, the step of forming the substrate 100 and fin include：Initial substrate is provided；In the initial substrate table Face forms fin hard mask layer 200；It is initial substrate described in mask etching with the fin hard mask layer 200, forms substrate 100 And protrude from the fin on 100 surface of the substrate.

In the present embodiment, after forming the substrate 100 and fin, retain the fin hard mask layer being located at the top of the fin 200.The material of the fin hard mask layer 200 is silicon nitride, and subsequently when carrying out planarization process technique, the fin is covered firmly 200 top surface of film layer is used to define the stop position of planarization process technique, and plays the role of at the top of the protection fin.

In conjunction with reference to figure 3, it should be noted that after forming the substrate 100 and fin (not indicating), the forming method Further include：Isolation structure 101 is formed on the substrate 100 that the fin exposes, the isolation structure 101 covers the fin Partial sidewall, and 101 top of the isolation structure is less than at the top of the fin.

Isolation structure of the isolation structure 101 as semiconductor devices, for being played to adjacent devices or adjacent fin Buffer action.In the present embodiment, the material of the isolation structure 101 is silica.In other embodiments, the isolation structure Material can also be silicon nitride or silicon oxynitride.

Specifically, the step of forming the isolation structure 101 include：The fin expose substrate 100 on formed every From film, top (as shown in Figure 2) higher than the fin hard mask layer 200 at the top of the isolation film；Grinding removal is higher than the fin The isolation film at 200 top of portion's hard mask layer；The remaining isolation film for carving segment thickness is returned to form isolation structure 101；Described in removal Fin hard mask layer 200.

In conjunction with being stereogram (only illustrating two fins) with reference to figure 4 and Fig. 5, Fig. 4, Fig. 5 is Fig. 4 cuing open along DD1 secants Face figure forms gate structure 102 on the substrate.

In the present embodiment, gate electrode layer (high k last metal gate are formed after forming high-k gate dielectric layer after Last technique), therefore the gate structure 102 is pseudo- grid structure (dummy gate), the gate structure 102 is follow-up shape It takes up space position at metal gate structure.

In other embodiments, gate electrode layer (high k first can also be initially formed using high-k gate dielectric layer is initially formed Metal gate first) technique；Correspondingly, the gate structure can also be metal gate structure (metal gate).

The substrate includes substrate 100 and discrete fin on the substrate 100 (not indicating), therefore described In the step of forming gate structure 102 in substrate, the gate structure 102 covers the portion of the fin across the fin Divide top surface and sidewall surfaces.

Specifically, the gate structure 102 of the PMOS area I is across first fin 110, and covers first fin The atop part surface in portion 110 and sidewall surfaces；The gate structure 102 of the NMOS area II across second fin 120, And cover atop part surface and the sidewall surfaces of second fin 120.

The gate structure 102 is single layer structure or laminated construction.The gate structure 102 includes pseudo- grid layer；Or institute It includes pseudo- oxide layer and the pseudo- grid layer in the pseudo- oxide layer to state gate structure 102.Wherein, the material of the pseudo- grid layer For polysilicon, silica, silicon nitride, silicon oxynitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride or amorphous carbon, the pseudo- oxidation The material of layer is silica or silicon oxynitride.

Specifically, the step of forming the gate structure 102 include：Pseudo- grid film, institute are formed on the isolation structure 101 Pseudo- grid film is stated across the fin, and covers the top surface and sidewall surfaces of the fin；It is formed in the pseudo- grid film surface Grid hard mask layer 210, the grid hard mask layer 210 define the figure of gate structure 102 to be formed；With the grid Hard mask layer 210 is mask, and the graphical pseudo- grid film forms gate structure 102.

It should be noted that after forming the gate structure 102, retain the grid being located on 102 top of the gate structure Extremely hard mask layer 210.In the present embodiment, the material of the grid hard mask layer 210 is silicon nitride, the grid hard mask layer 210 are used to play a protective role to 102 top of the gate structure during subsequent technique.

Subsequent step includes：The areas N groove is formed in the substrate of 102 both sides of NMOS area II gate structures；Institute It states and forms the areas N doped epitaxial floor in the areas N groove.

It should be noted that the substrate 100 further includes being used to form the PMOS area I of P-type device, therefore the formation Method further includes：The areas P groove is formed in the substrate of 102 both sides of PMOS area I gate structures；In the areas P groove Form the areas P doped epitaxial floor.

In the present embodiment, said for forming the areas the N doped epitaxial floor after being initially formed the areas the P doped epitaxial floor It is bright.

In conjunction with being the cross-sectional view based on Fig. 5 with reference to figure 6 and Fig. 7, Fig. 6, Fig. 7 is based on Fig. 5 in fin position Place is along the cross-sectional view perpendicular to fin extending direction secant (as shown in EE1 secants in Fig. 4), in first fin The areas P mask layer 310 is formed on 110 side walls and top.

The technique for forming the areas P mask layer 310 can be chemical vapor deposition method, physical gas-phase deposition or original Sublayer depositing operation.In the present embodiment, the areas P mask layer 310 is formed using atom layer deposition process.The areas P mask layer 310 are also located on the top of second fin 120 and side wall, the areas P mask layer 310 be also located at the PMOS area I and 102 top of gate structure of NMOS area II and side wall, and be also located on the isolation structure 101.

The effect of the areas P mask layer 310 includes：The areas P mask layer 310 on the fin side wall plays protection institute The effect for stating fin side wall avoids carrying out epitaxial growth work subsequently on 110 and second fin of the first fin, 120 side wall Skill；In addition, being located at one of the areas the P mask layer 310 of NMOS area II subsequently also as the areas the N mask layer of follow-up NMOS area II Point.

The material of the areas P mask layer 310 can be silicon nitride, silica, boron nitride or silicon oxynitride.The areas P cover The material of film layer 310 is different from the material of the fin, the material of the material and the isolation structure 101 of the areas P mask layer 310 Material also differs.In the present embodiment, the material of the areas P mask layer 310 is silicon nitride.

In conjunction with being the cross-sectional view based on Fig. 7 with reference to figure 8 and Fig. 9, Fig. 8, Fig. 9 is along the first fin extending direction The cross-sectional view of secant (BB1 secants in such as Fig. 1), the shape in the substrate of 102 both sides of PMOS area I gate structures At the initial groove in the areas P 111.

The initial groove in the areas P 111 provides Process ba- sis to be subsequently formed the areas P groove.

Specifically, using anisotropic etch process etching positioned at the first of 102 both sides of PMOS area I gate structures The areas P mask layer 310 on 110 top of fin, wherein be located at 102 the first fin of both sides of the PMOS area I gate structures in etching In the technical process of the areas P mask layer 310 on 110 top of portion, also etching is located at 102 top of the PMOS area I gate structures The areas P mask layer 310 on the upper and described isolation structure 101；The first fin in 102 both sides of PMOS area I gate structures After 110 top of portion is exposed, continue first fin 110 of etched portions thickness, the shape in first fin 110 At the initial groove in the areas P 111.

In the present embodiment, subsequent step further includes performing etching the side wall of the initial groove in the areas P 111 and bottom with shape At the areas P groove, therefore in order to make the depth of the areas P groove and opening size meet process requirements, the areas PMOS are stated described in etching In the step of 102 the first fin of two side portions thickness 110 of domain I gate structures, the removal amount of first fin 110 be 10nm extremely 60nm, correspondingly, the depth of the initial groove in the areas P 111 is 10nm to 60nm.

It should be noted that being located on 102 first fin of both sides of PMOS area I gate structures, 110 top in etching The areas P mask layer 310 before, the forming method further includes：The first graph layer 220 is formed on the NMOS area II (such as Shown in Fig. 8), first graph layer 220 covers the areas the P mask layer 310 of the NMOS area II.

First graph layer 220 plays the role of the areas P mask layer 310 on the protection NMOS area II, and described first Graph layer 220 can also cover the region for not expecting to be etched in the PMOS area I.

In the present embodiment, the material of first graph layer 220 is Other substrate materials.Forming the initial groove in the areas P After 111, retain first graph layer 220, etch mask of first graph layer 220 as subsequent etching processes.

It should also be noted that, in order to increase the volume of the formed areas the P doped epitaxial floor subsequently in the areas P groove, carving While losing the first fin 110, also etching is located at the areas the P mask layer 310 on 110 side wall of the first fin, makes After the initial groove in the areas P 111 must be formed, be located at the areas P mask layer 310 on 110 side wall of the first fin with it is described First fin, 110 top flushes.

In conjunction with being the cross-sectional view based on Fig. 8 with reference to figure 10 and Figure 11, Figure 10, Figure 11 is the section based on Fig. 9 Structural schematic diagram carves the side wall of the areas P initial groove 111 (as shown in Figure 9) and bottom using mixing etching gas Erosion forms the areas P groove 112；The mixing etching gas includes silicon source gas and HCl gases.

The areas P groove 112 provides spatial position to be subsequently formed the areas P doped epitaxial floor.

It should be noted that in the etching process for forming the initial groove in the areas P 111, the initial groove in the areas P 111 side walls and 110 material of the first fin of bottom are easy to cause first fin 110 of segment thickness by ion bombardment Material is damaged and has defect (such as Ge atoms deviate lattice position), therefore in order to improve follow-up p-type doped epitaxial layer Formation quality, side wall and bottom by the mixing etching gas of silicon source gas and HCl gases to the initial groove in the areas P 111 Portion performs etching, to impaired 110 material of the first fin of removal and the etching technics to first fin 110 damage compared with It is small, therefore the quality for 110 material of the first fin that the areas P groove 112 exposes can be made preferable, it is follow-up so as to improve The formation quality of p-type doped epitaxial layer.

Specifically, the step of forming the areas P groove 112 include：The gaseous mixture of the silicon source gas and HCl gases is provided Body；The first fin 110 that the initial groove in the silicon source gas and the areas P 111 exposes reacts to form Ge-Si keys；The HCl Gas removes the Ge-Si keys, to remove 110 material of the first fin of segment thickness.

In the present embodiment, the silicon source gas is SiH₄, formed the areas P groove 112 technological temperature be 400 DEG C extremely 700℃.In other embodiments, the silicon source gas can also be Si₂Cl₂Or SiHCl₃。

In the present embodiment, SiH₄For reacting to form Ge-Si keys with the first fin 110, HCl is for removing the Ge-Si Key is to remove 110 material of the first fin of segment thickness, therefore SiH₄First fin is influenced with the gas flow of HCl 110 removal amount.In order to while completely removing tool defective first fin, 110 material, avoid to first fin 110 cause excessively to be lost, the SiH₄It is both needed to control in the reasonable scope with the gas flow of HCl, and reasonably combined.

It should be noted that SiH₄Gas flow it is unsuitable very few, it is also unsuitable excessive.If SiH₄Gas flow it is very few, It is accordingly reacted with the first fin 110 exposed and is formed by that Ge-Si keys are very few, be accordingly easy to cause the first fin exposed 110 removal amounts are very few, to be difficult to completely remove defective first fin, 110 material of tool；On the contrary, if SiH₄Gas stream Amount is excessive, then is easy to cause excessive 110 material of the first fin and SiH₄It reacts, so as to cause to formed semiconductor device The electric property of part generates harmful effect.For this purpose, in the present embodiment, SiH₄Gas flow be 10sccm to 1000sccm.

It should also be noted that, the gas flow of HCl is unsuitable very few, it is also unsuitable excessive.The gas flow mistake of the HCl Few, then the effect for removing the Ge-Si keys is accordingly poor, has defective first fin 110 so as to cause being difficult to completely remove Material；On the contrary, if the gas flow of the HCl is excessive, it is easy to cause and remaining first fin 110 is caused to damage, Increase process risk.For this purpose, in the present embodiment, the gas flow of HCl is 5sccm to 100sccm.

The removal amount of the first fin 110 exposed to the initial groove in the areas P 111 is depending on actual process.If going It is very few except measuring, accordingly cause 110 quality of materials of the first fin that the formed areas P groove 112 exposes poor；If removal amount mistake It is more, it mutually copes with 110 material of the first fin corresponding to formed semiconductor device channel area and causes harmful effect, or even be easy to cause The areas P mask layer 310 on 102 side wall of PMOS area I gate structures caves in.It is initial to the areas P in the present embodiment After the side wall of groove 111 and bottom perform etching, the removal amount for the first fin 110 that the initial groove in the areas P 111 exposes is 1nm to 2nm.

In the present embodiment, after forming the areas P groove 112, is removed photoresist using wet method or cineration technics removes first figure Shape layer 220.

In conjunction with being the cross-sectional view based on Figure 10 with reference to figure 12 and Figure 13, Figure 12, Figure 13 is cuing open based on Figure 11 Face structural schematic diagram forms the areas P doped epitaxial floor 131 in the areas P in groove 112 (as shown in figure 11).

The areas the P doped epitaxial floor 131 is used for the source region as follow-up formed P-type device or drain region.

In the present embodiment, using selective epitaxial process, p type semiconductor layer is formed in groove 112 in the areas P and (schemed not Show), and in the technical process for forming the p type semiconductor layer, auto-dope p-type ion in situ is outer to form the areas the P doping Prolong layer 131.The p type semiconductor layer provides action of compressive stress for the channel region of the PMOS area I, to improve formed P The carrier mobility of type device.

It should be noted that the doping concentration of p-type ion is higher in the areas the P doped epitaxial floor 131, that accordingly plays carries It is more apparent for action of compressive stress；But the doping concentration of p-type ion is higher that corresponding to also result in contact resistance excessive.

Therefore, in the present embodiment, while in order to ensure to provide action of compressive stress, reduce contact resistance, it is recessed in the areas P The step of formation areas P doped epitaxial floor 131, includes in slot 112：In the areas P, the bottom and side wall of groove 112 forms the Semi-conductor layer (not shown), and the auto-dope p-type ion in situ in the step of forming first semiconductor layer, to form the One p-type doped epitaxial layer (not indicating)；The second semiconductor layer (not shown) is formed on the first p-type doped epitaxial layer, and The auto-dope p-type ion in situ in the step of forming second semiconductor layer, (is not marked with forming the second p-type doped epitaxial layer Show), and the Doped ions concentration of the second p-type doped epitaxial layer is less than the Doped ions of the first p-type doped epitaxial layer Concentration.Wherein, the second p-type doped epitaxial floor and the first p-type doped epitaxial floor constitute the areas the P doped epitaxial floor 131。

Specifically, the material of first semiconductor layer and the second semiconductor layer is SiGe, the p-type ion be B from Son, therefore the material of the first p-type doped epitaxial layer is the SiGe doped with B ions, the second p-type doped epitaxial layer Material is the SiGe doped with B ions.

The doping concentration of the first p-type doped epitaxial layer and the second p-type doped epitaxial layer according to actual process demand and It is fixed.In the present embodiment, the atom percentage content of Ge is mixing for 30% to 60%, B ions in the first p-type doped epitaxial layer Miscellaneous a concentration of 1.4E21atom/cm³To 2.6E21atom/cm³；The atomic percent of Ge contains in the first p-type doped epitaxial layer Amount is that the doping concentration of 10% to 20%, B ions is 1.4E20atom/cm³To 2.6E20atom/cm³.And described the first half lead The ratio of bulk layer thickness and second layer semiconductor thickness is 1:15 to 1:5.Wherein, the atom percentage content of Ge refers to The total atom number of Ge accounts for the percentage of the total atom number of Si and Ge.

It should be noted that in order to avoid subsequent technique causes process-induced damage to 131 surface of the areas P doped epitaxial floor, After forming the areas the P doped epitaxial floor 131, the method further includes：Oxygen is carried out to 131 surface of the areas P doped epitaxial floor Change is handled, and oxide protective layer (not shown) is formed on 131 surface of the areas P doped epitaxial floor；The oxidation processes can be dry Oxygen oxidation, wet-oxygen oxidation or steam oxidation.

In conjunction with reference to figs. 14 to Figure 18, Figure 14 is the cross-sectional view based on Figure 12, in the NMOS area II grid N area's grooves 122 (as shown in figure 18) are formed in the substrate of 102 both sides of pole structure.

The areas N groove 122 provides spatial position to be subsequently formed the areas N doped epitaxial floor.

Below in conjunction with attached drawing, elaborate to the step of forming the areas N groove 122.

With reference to figure 14, the areas N mask layer 330 is formed on the top of second fin 120 and side wall.

Specifically, being formed after the areas the P doped epitaxial floor 131, on the areas the P mask layer 310 of the NMOS area II The areas N mask side wall 320 is formed, institute is used as positioned at the areas the P mask layer 310 of the NMOS area II and the areas the N mask side wall 320 State the areas N mask layer 330.Correspondingly, the areas N mask layer 330 be also located at the NMOS area II gate structures 102 top and On side wall, and it is also located on the isolation structure 101 of the NMOS area II.

In the present embodiment, the areas the N mask side wall 320 is also located on the p-type doped epitaxial floor 131 and PMOS area On the isolation structure 101 of I, and it is also located on 102 side wall of gate structure and top of PMOS area I.

Material in relation to the areas the N mask side wall 320 can refer to the related of the aforementioned areas P mask layer 310 to formation process and retouch It states, details are not described herein.

The effect of the areas the N mask side wall 320 includes：On the one hand, the areas the N mask side wall 320 and the areas P mask layer 310 constitute the areas the N mask layer 330 of laminated construction, 102 two side portions thickness of NMOS area II gate structures described in subsequent etching When the second fin 120, using the areas N mask layer 330 as mask, therefore can increase follow-up the formed areas N groove 122 and The distance of NMOS channel regions is conducive to improve short-channel effect.

In conjunction with being the cross-sectional view based on Figure 14 with reference to figure 15 and Figure 16, Figure 15, Figure 16 is to prolong along the second fin The cross-sectional view for stretching direction secant (CC1 secants in such as Fig. 1), in 102 both sides of NMOS area II gate structures The initial groove in the areas N 121 is formed in substrate.

The initial groove in the areas N 121 provides Process ba- sis to be subsequently formed the areas N groove.

Specifically, 102 both sides second of NMOS area II gate structures are located at using anisotropic etch process etching The areas N mask layer 330 on 120 top of fin, wherein be located at 102 both sides second of NMOS area II gate structures in etching In the technical process of the areas N mask layer 330 on 120 top of fin, also etching is located at the NMOS area II gate structures 102 and pushes up The areas N mask layer 330 in portion and on isolation structure 101；The second fin in 102 both sides of NMOS area II gate structures After 120 tops are exposed, continue second fin 120 of etched portions thickness, is formed in second fin 120 The initial groove in the areas N 121.

The step of 102 the second fin of two side portions thickness 120 of NMOS area II gate structures is stated in the present embodiment, described in etching In rapid, the removal amount of second fin 120 is 10nm to 60nm, correspondingly, the depth of the initial groove in the areas N 121 is 10nm to 60nm.

The concrete technology and parameter description of the initial groove in the formation areas N 121 are please referred to and be previously formed the initial groove in the areas P The corresponding description of 111 (as shown in Figure 9), details are not described herein.

It should be noted that the N on etching 102 second fin of both sides of NMOS area II gate structures, 120 top Before area's mask layer 330, the forming method further includes：230 (such as Figure 15 of second graph layer is formed on the PMOS area I It is shown), the second graph layer 230 covers the p-type doped epitaxial layer 131, described in the second graph layer 230 also covers The gate structure 102 of PMOS area I.

Specifically, the second graph floor 230 is formed on the areas the N mask side wall 320 of the PMOS area I, and described Two graph layers 230 can play the role of the protection PMOS area I, and the second graph layer 230 can also cover described The region being etched is not expected in NMOS area II.

In the present embodiment, the material of the second graph layer 230 is Other substrate materials.Forming the initial groove in the areas N After 121, retain the second graph layer 230, etch mask of the second graph layer 230 as subsequent etching processes.

It should also be noted that, in order to increase the volume of subsequently the formed areas the N doped epitaxial floor in the areas N groove 122, While etching the second fin 120, also etching is located at the areas the N mask layer 330 on 120 side wall of the second fin so that After forming the initial groove in the areas N 121, it is located at the areas N mask layer 330 on 120 side wall of the second fin and described the Two fins, 120 top flushes.

In conjunction with being the cross-sectional view based on Figure 15 with reference to figure 17 and Figure 18, Figure 17, Figure 18 is cuing open based on Figure 16 Face structural schematic diagram carries out the side wall of the areas N initial groove 121 (as shown in figure 16) and bottom using mixing etching gas Etching forms the areas N groove 122；The mixing etching gas includes silicon source gas and HCl gases.

It should be noted that in the etching process for forming the initial groove in the areas N 121, the initial groove in the areas N 121 side walls and 120 material of the second fin of bottom are easy to cause second fin 120 of segment thickness by ion bombardment Material is damaged and has defect (such as Ge atoms deviate lattice position), therefore in order to improve follow-up n-type doping epitaxial layer Formation quality, side wall and bottom by the mixing etching gas of silicon source gas and HCl gases to the initial groove in the areas N 121 Portion performs etching, damaged to impaired 120 material of the second fin of removal and to second fin 120 it is smaller, therefore can be with Keep the quality for 120 material of the second fin that the formed areas N groove 122 exposes preferable, so as to improve outside follow-up n-type doping Prolong the formation quality of layer.

In the present embodiment, in the step of forming the areas N groove 122, the silicon source gas is SiH₄, SiH₄Gas stream Amount is 10sccm to 1000sccm, and the gas flow of HCl is 5sccm to 100sccm, and technological temperature is 400 DEG C to 700 DEG C. In other embodiment, the silicon source gas can also be Si₂Cl₂Or SiHCl₃。

In the present embodiment, after side wall and bottom to the initial groove in the areas N 121 perform etching, the initial groove in the areas N The removal amount of 121 the second fins 110 exposed is 1nm to 2nm.

The aforementioned areas P groove 112 is please referred to (such as to the specific descriptions of the technique and parameter that form the areas N groove 122 Shown in Figure 11) the corresponding description of formation process, details are not described herein.

In the present embodiment, after forming the areas N groove 122, is removed photoresist using wet method or cineration technics removes second figure Shape layer 230.

In conjunction with being the cross-sectional view based on Figure 17 with reference to figure 19 and Figure 20, Figure 19, Figure 20 is cuing open based on Figure 18 Face structural schematic diagram, forms the areas N doped epitaxial floor 231 in the areas N in groove 122 (as shown in figure 18), the areas the N doping is outer It is the laminated construction that the first n-type doping epitaxial layer 235 and the second n-type doping epitaxial layer 236 are constituted to prolong layer 231, wherein described the One n-type doping epitaxial layer 235 is the first epitaxial layer doped with N-type ion, and the second n-type doping epitaxial layer 236 is doping There are the second epitaxial layer of N-type ion, the energy gap of second epitaxial layer to be less than the energy gap of first epitaxial layer.

The areas the N doped epitaxial floor 231 is used for the source region as follow-up formed N-type device or drain region.

Since the energy gap of the second epitaxial layer is smaller, by second epitaxial layer, the areas N are advantageously reduced The schottky barrier height of doped epitaxial layer 231 and channel region；And the Doped ions of the second n-type doping epitaxial layer 236 are N Type ion, to make the N-type ion concentration in the areas the N doped epitaxial floor 231 be improved.It is subsequently formed and is mixed with the areas N After the contact hole plug that miscellaneous epitaxial layer 231 is electrically connected, the areas the N doped epitaxial floor 231 and the contact of contact hole plug contact zone Resistance is directly proportional to schottky barrier height and is inversely proportional with N-type ion concentration, therefore by being formed outside second n-type doping Prolong layer 236, contact resistance can be reduced.

In the present embodiment, it is initially formed the first n-type doping epitaxial layer 235, re-forms the second n-type doping epitaxial layer 236.That is, the step of forming the areas N doped epitaxial floor 231 includes：It is formed outside first in the areas N groove 122 Prolong layer；To the first epitaxial layer doped N-type ion, the first n-type doping epitaxial layer 235 is formed；Outside first n-type doping Prolong and forms the second epitaxial layer on layer 235；To the second epitaxial layer doped N-type ion, the second n-type doping epitaxial layer 236 is formed； The second n-type doping epitaxial layer 236 and the first n-type doping epitaxial layer 235 constitute the areas N doped epitaxial floor 231.

In other embodiments, it can also be initially formed the second n-type doping epitaxial layer, first N-type is re-formed and mix Miscellaneous epitaxial layer.

In the present embodiment, the areas the N doped epitaxial floor 231 is formed using selective epitaxial process.Specifically, described in formation The step of first n-type doping epitaxial layer 235 includes：In the step of forming the first epitaxial layer in the areas N groove 122, to institute State the first epitaxial layer in-situ doped N-type ion；The step of forming the second n-type doping epitaxial layer 236 include：Described first In the step of forming the second epitaxial layer on n-type doping epitaxial layer 235, to the second epitaxial layer in-situ doped N-type ion.

In other embodiments, the areas the N doped epitaxial floor can also be formed using non-epitaxial technique.Correspondingly, being formed The step of first n-type doping epitaxial layer includes：After forming the first epitaxial layer in the areas N groove, to outside described first Prolong a layer doped N-type ion；The step of forming the second n-type doping epitaxial layer include：It is formed in first n-type doping layer After second epitaxial layer, to the second epitaxial layer doped N-type ion.

In the present embodiment, the material of first epitaxial layer is Si, and the N-type ion is P ion, therefore the first N The material of type doped epitaxial layer 235 is the Si doped with P ion；Wherein, the doping concentration of P ion according to actual process demand and It is fixed.In the present embodiment, the doping concentration of P ion is 1E21atom/cm³To 2E21atom/cm³.In other embodiments, described The material of first epitaxial layer can also be SiC.

In the present embodiment, the material of second epitaxial layer is SiGe, and the N-type ion is P ion, therefore described second The material of n-type doping epitaxial layer 236 is the SiGe doped with P ion.

It should be noted that the doping concentration of P ion is unsuitable too small in the second n-type doping epitaxial layer 236.If P The doping concentration of ion is too small, then be easy to cause reduce contact resistance effect unobvious, and due to by P ion in sige Solid solubility limitation, in the present embodiment, the doping concentration of P ion is in the second n-type doping epitaxial layer 236 2.5E20atom/cm³To 1.8E21atom/cm³。

It should be noted that the atom percentage content of Ge is unsuitable too low in the second n-type doping epitaxial layer 236, It is unsuitable excessively high.If the atom percentage content of Ge is too low, the reducing effect unobvious of schottky barrier height；If Ge's Atom percentage content is excessively high, then is easy to cause harmful effect to the electric property of formed N-type device.For this purpose, the present embodiment In, the atom percentage content of Ge is 5% to 45%.Wherein, the atom percentage content of Ge refers to the total atom number of Ge Account for the percentage of the total atom number of Si and Ge.

Correspondingly, while in order to ensure to reduce schottky barrier height effect, the electricity to formed N-type device is avoided Performance causes harmful effect, and in the present embodiment, the thickness of second epitaxial layer is 2nm to 8nm.

In conjunction with being the cross-sectional view based on Figure 19 with reference to figures 21 to Figure 23, Figure 21, Figure 22 is to prolong along the first fin The cross-sectional view of direction secant (BB1 secants in such as Fig. 1) is stretched, Figure 23 is along second fin extending direction secant (such as Fig. 1 Middle CC1 secants) cross-sectional view, on the areas the N doped epitaxial floor 231 formed interlayer dielectric layer 104.

The interlayer dielectric layer 104 is additionally operable to for realizing the electric isolution between adjacent semiconductor constructs to be subsequently formed Contact hole plug provides technique platform.

In the present embodiment, in the step of forming interlayer dielectric layer 104 on the areas the N doped epitaxial floor 231, the interlayer Dielectric layer 104 is also located on the areas the P doped epitaxial floor 131.

The material of the interlayer dielectric layer 104 is insulating materials.In the present embodiment, the material of the interlayer dielectric layer 104 For silica.In other embodiments, the material of the interlayer dielectric layer can also be silicon nitride or silicon oxynitride.

It should be noted that it is pseudo- grid structure that the gate structure 102 is (as shown in figure 20), therefore forms the areas N and mix It after miscellaneous epitaxial layer 231 and the areas P doped epitaxial floor 131, is formed before the interlayer dielectric layer 104, the forming method further includes： Bottom dielectric layer 103 is formed in the substrate that the gate structure 102 exposes, the bottom dielectric layer 103 exposes the NMOS 102 top of gate structure of region II and PMOS area I；The gate structure 102 is removed, in the bottom dielectric layer 103 Form gate openings (not shown)；Metal gate structure 250 (as shown in figure 22) is formed in the gate openings.

102 top of the gate structure is formed with grid hard mask layer 210 (as shown in figure 20), therefore removes the grid Before structure 102, the forming method further includes：Remove the grid hard mask layer 210.

The bottom dielectric layer 103 is additionally operable to for realizing the electric isolution between adjacent semiconductor constructs to be subsequently formed Contact hole plug provides technique platform, and is additionally operable to form gate openings, to define the size of formed metal gate structure 250 The position and.

The material of the bottom dielectric layer 103 is insulating materials.It is described in order to improve processing compatibility in the present embodiment The material of the material identical of the material of bottom dielectric layer 103 and the interlayer dielectric layer 104, the bottom dielectric layer 103 is oxygen SiClx.In other embodiments, the material of the bottom dielectric layer can also be silicon nitride or silicon oxynitride.

The metal gate structure 250 is used to control the conducting of formed semiconductor structure raceway groove and blocks.

Specifically, include the step of formation metal gate structure 250 (as shown in figure 22) in the gate openings：Institute It states and forms high-k gate dielectric layer (not indicating) in the bottom and side wall of gate openings, the high-k gate dielectric layer is also located at the bottom The top of dielectric layer 103；Metal layer (not indicating) is formed on the high-k gate dielectric layer；Removal is higher than the bottom dielectric layer The metal layer at 103 tops, and the high-k gate dielectric layer higher than 103 top of the bottom dielectric layer is also removed, in the gate openings The residue high-k gate dielectric layer and metal layer constitute the metal gate structure 250.Correspondingly, the bottom dielectric layer 103 Top is flushed with 250 top of the metal gate structure.

The material of the high-k gate dielectric layer is the gate medium material that relative dielectric constant is more than silica relative dielectric constant Material.In the present embodiment, the material of the high-k gate dielectric layer is HfO₂.In other embodiments, the material of the high-k gate dielectric layer Material can also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO₂Or Al₂O₃。

In the present embodiment, the material of the metal layer is W.In other embodiments, the material of the metal layer can be with For Al, Cu, Ag, Au, Pt, Ni or Ti.

Correspondingly, in the step of forming the interlayer dielectric layer 104, the interlayer dielectric layer 104 covers the bottom and is situated between Matter layer 103 and the metal gate structure 250.

In conjunction with reference to figure 24 to Figure 26, Figure 24 is the cross-sectional view based on Figure 21, and Figure 25 is cuing open based on Figure 22 Face structural schematic diagram, Figure 26 are the cross-sectional views based on Figure 23, in the interlayer dielectric layer 104 of the NMOS area II Form the first contact openings 114 for exposing the areas the N doped epitaxial floor 231.

The first contact openings 114 of the NMOS area II are to be subsequently formed to be electrically connected with the areas the N doped epitaxial floor 231 The first contact hole plug provide spatial position.

In the present embodiment, first contact openings 114 are also formed into the interlayer dielectric layer 104 of the PMOS area I And expose the areas the P doped epitaxial floor 131；The first contact openings 114 of the PMOS area I are to be subsequently formed and the areas P The first contact hole plug that doped epitaxial layer 131 is electrically connected provides spatial position.

Specifically, the interlayer dielectric layer 104 covers the bottom dielectric layer 103 and the metal gate structure 250, because This was formed in the step of the first contact openings 114, and the first contact openings 114 of the NMOS area II also extend through the bottom For portion's dielectric layer 103 to expose the areas the N doped epitaxial floor 231, the first contact openings 114 of the PMOS area I also extend through institute Bottom dielectric layer 103 is stated to expose the areas the P doped epitaxial floor 131.

In the present embodiment, 231 top of the areas the N doped epitaxial floor and the areas P are removed by the way of dry etching The interlayer dielectric layer 104 and bottom dielectric layer 103 of 131 top of doped epitaxial layer.

It should be noted that in the present embodiment, first contact openings 114 are formed using non-self-aligned technique.So Before etching the interlayer dielectric layer 104 and bottom dielectric layer 103, the formation figure also on the interlayer dielectric layer 104 of part Shape layer；In the step of forming the first contact openings 114, performed etching as mask using the graph layer.In other implementations In example, first contact openings can also be formed by self-registered technology.

It should also be noted that, in the step of forming the first contact openings 114, also in the NMOS area II and The second contact openings 124 (as shown in figure 25) are formed in the interlayer dielectric layer 104 of 250 top of PMOS area I metal gate structures, Second contact openings 124 expose the metal gate structure 250.

Second contact openings 124 are to be subsequently formed the second contact hole being electrically connected with the metal gate structure 250 Plug provides spatial position.

In conjunction with reference to figure 27 to Figure 29, Figure 27 is the cross-sectional view based on Figure 24, and Figure 28 is cuing open based on Figure 25 Face structural schematic diagram, Figure 29 are the cross-sectional views based on Figure 26, in first contact openings 114 (as shown in figure 24) It is interior to form the first contact hole plug 151 being electrically connected with the areas the N doped epitaxial floor 231.

It is described in the step of forming the first contact hole plug 151 in first contact openings 114 in the present embodiment First contact hole plug 151 be also formed into the first contact openings 114 of the PMOS area I and with the areas P doped epitaxial Layer 131 is electrically connected.

The first contact hole plug 151 of the PMOS area I is electrically connected with the areas the P doped epitaxial floor 131 realization, described The first contact hole plug 151 of NMOS area II is electrically connected with the areas the N doped epitaxial floor 231 realization, first contact hole Plug 151 is additionally operable to realize being electrically connected between device and device for realizing the electrical connection in semiconductor devices.

In the present embodiment, the interlayer dielectric layer of 250 top the NMOS area II and PMOS area I metal gate structures It is formed with the second contact openings 124 (as shown in figure 25) for exposing the metal gate structure 250 in 104, therefore described the In the step of forming the first contact hole plug 151 in one contact openings 114, also formed in second contact openings 124 with The second contact hole plug 152 (as shown in figure 28) that the metal gate structure 250 is electrically connected.

Second contact hole plug 152 is electrically connected with the realization of the metal gate structure 250, for realizing semiconductor device Electrical connection in part is additionally operable to realize being electrically connected between device and device.

Specifically, the step of formation 151 and second contact hole plug 152 of the first contact hole plug include：To described The first contact openings 114 and the second contact openings 124 of PMOS area I, 114 and of the first contact openings of the NMOS area II Full conductive material is filled in second contact openings 124, the conductive material is also located at 104 top of the interlayer dielectric layer；To institute It states conductive material and carries out planarization process, removal connects higher than the conductive material at 104 top of the interlayer dielectric layer described first It touches and forms the first contact hole plug 151 in opening 114 and form the second contact hole plug in second contact openings 124 152。

In the present embodiment, the material of first contact hole plug, 151 and second contact hole plug 152 is equal W, can be adopted First contact hole plug, 151 and second contact hole is formed with chemical vapor deposition method, sputtering technology or electroplating technology to insert Plug 152.In other embodiments, the material of first contact hole plug can also be the metal materials such as Al, Cu, Ag or Au, The material of second contact hole plug can also be the metal materials such as Al, Cu, Ag or Au.

It should be noted that in order to reduce the contact resistance of contact zone, to the first contact openings of the PMOS area I 114 and second contact openings 124, the NMOS area II the first contact openings 114 and the second contact openings 124 in fill it is full Before conductive material, the forming method further includes：Metal silicide layer is formed in the bottom of first contact openings 114 (not shown).In the present embodiment, the material of the metal silicide layer is TiSi.In other embodiments, the metal silication The material of nitride layer can also be NiSi.

It should also be noted that, in other embodiments, gate electrode layer is initially formed when use is initially formed high-k gate dielectric layer It is described on the substrate in the step of formation gate structure when the technique of (high k first metal gate first) Gate structure is metal gate structure；Correspondingly, in the step of forming the interlayer dielectric layer, expose in the gate structure The interlayer dielectric layer is formed in substrate, is higher than at the top of the gate structure at the top of the interlayer dielectric layer；Form described second In the step of contact openings, is formed in the interlayer dielectric layer above the NMOS area and PMOS area gate structure and expose institute State the second contact openings of gate structure；In the step of forming the first contact hole plug in first contact openings, also exist The second contact hole plug is formed in second contact openings.

In the technical solution of the forming method of semiconductor structure provided by the present invention, the areas formation N are mixed in the areas N groove Miscellaneous epitaxial layer, the areas the N doped epitaxial floor are the lamination knot that the first n-type doping epitaxial layer and the second n-type doping epitaxial layer are constituted Structure, wherein the first n-type doping epitaxial layer is the first epitaxial layer doped with N-type ion, the second n-type doping extension Layer is the second epitaxial layer doped with N-type ion, and the energy gap of second epitaxial layer is less than the taboo of first epitaxial layer Bandwidth.Be formed by the areas N doped epitaxial floor only include doped with the scheme of the first epitaxial layer of N-type ion compared with, due to The energy gap of second epitaxial layer is smaller, therefore it is outer to advantageously reduce the areas the N doping by second epitaxial layer by the present invention Prolong the schottky barrier height of layer and channel region；In addition, the Doped ions of the second n-type doping epitaxial layer are N-type ion, make N-type ion concentration in the areas the N doped epitaxial floor is improved；Since contact resistance is directly proportional to schottky barrier height, And be inversely proportional with N-type ion concentration, therefore scheme of the present invention can reduce contact resistance, to improve formed N-type device Driving current, to make the electric property of the semiconductor structure be improved.

In addition, the step of forming the areas the N doped epitaxial floor includes：The first epitaxial layer is formed in the areas N groove；To The first epitaxial layer doped N-type ion forms the first n-type doping epitaxial layer；It is formed on the first n-type doping epitaxial layer Second epitaxial layer；To the second epitaxial layer doped N-type ion, the second n-type doping epitaxial layer is formed；Second n-type doping Epitaxial layer and the first n-type doping epitaxial layer constitute the areas N doped epitaxial floor, correspondingly, material at the top of the areas the N doped epitaxial floor In the step of expecting to be the SiGe doped with N-type ion, be subsequently formed the first contact openings, first contact openings are also formed into In the interlayer dielectric layer of the PMOS area and expose the areas the P doped epitaxial floor, the material of the areas the P doped epitaxial floor is to mix The miscellaneous SiGe for having p-type ion, that is to say, that the material that first contact openings expose is SiGe, therefore is conducive to optimize The formation process of the formation process of first contact openings and follow-up first contact hole plug.

In conjunction with reference to figure 30 to Figure 32, the structural schematic diagram of one embodiment of semiconductor structure of the present invention, Tu30Wei are shown Along the section knot perpendicular to fin extending direction secant (in such as Fig. 4 shown in EE1 secants) at the fin position of gate structure side Structure schematic diagram, Figure 31 are the cross-sectional view along the first fin extending direction secant (BB1 secants in such as Fig. 1), Tu32Wei Along the cross-sectional view of the second fin extending direction secant (CC1 secants in such as Fig. 1).Correspondingly, the present invention also provides one Kind semiconductor structure, including：

Substrate (does not indicate), and the substrate includes the NMOS area II for having N-type device；Gate structure 450 is (such as Figure 32 institutes Show), it is located in the substrate；Positioned at the intrabasement areas the N doped epitaxial floor in 450 both sides of NMOS area II gate structures 631 (as shown in figure 32), the areas the N doped epitaxial floor 631 are the first n-type doping epitaxial layer 635 and the second n-type doping epitaxial layer 636 The laminated construction of composition, wherein the first n-type doping epitaxial layer 635 is the first epitaxial layer doped with N-type ion, described Second n-type doping epitaxial layer 636 is the second epitaxial layer doped with N-type ion, and the energy gap of second epitaxial layer is less than The energy gap of first epitaxial layer；Interlayer dielectric layer 402 is located on the areas the N doped epitaxial floor 631；First contact hole Plug 451 runs through the interlayer dielectric layer 402 of the NMOS area II and is electrically connected with the areas the N doped epitaxial floor 631.

In the present embodiment, in the substrate have fin formula field effect transistor, therefore the substrate include substrate 400 and Discrete fin (not the indicating) on the substrate 400.In other embodiments, there is planar transistor in the substrate, Correspondingly, the substrate is planar substrate.

In the present embodiment, by taking the fin formula field effect transistor is cmos device as an example, the substrate 400 includes not only tool The NMOS area II for having N-type device further includes the PMOS area I, the PMOS area I and NMOS area II with P-type device Substrate 400 on all have discrete fin.In other embodiments, when the fin formula field effect transistor is NMOS device, The substrate only includes NMOS area.

Therefore, the semiconductor structure further includes：Positioned at the intrabasement areas P in 450 both sides of PMOS area I gate structures Doped epitaxial layer 531 (as shown in figure 31).

In the present embodiment, it is the first fin 410 to be located at the fin on the PMOS area I substrates 400, is located at the NMOS Fin on region II substrates 400 is the second fin 420.Correspondingly, the gate structure 450 of the PMOS area I is across described First fin 410, and cover atop part surface and the sidewall surfaces of first fin 410；The grid of the NMOS area II Pole structure 450 covers atop part surface and the sidewall surfaces of second fin 420 across second fin 420；Institute The areas N doped epitaxial floor 631 is stated to be located in the second fin 420 of 450 both sides of NMOS area II gate structures；The areas P are mixed Miscellaneous epitaxial layer 531 is located in the first fin 410 of 450 both sides of PMOS area I gate structures.

In order to improve the carrier mobility of semiconductor devices, the substrate is germanic substrate.It is described to contain in the present embodiment Germanium substrate is germanium substrate, correspondingly, the material of the substrate 400 is germanium.In other embodiments, the material of the germanic substrate Can also be SiGe, the germanic substrate can also be the germanium substrate on insulator.The material of the substrate can be chosen suitable The material for being suitable for process requirements or being easily integrated.

The material identical of the material of the fin and the substrate 400.Therefore, in the present embodiment, the material of the fin Material for germanium, i.e., described first fin, 410 and second fin 420 is germanium.

It should be noted that the semiconductor structure further includes：Isolation junction on the substrate 400 that the fin exposes Structure 401 (as shown in figure 30), the isolation structure 401 cover the partial sidewall of the fin, and 401 top of the isolation structure Less than at the top of the fin.

Isolation structure of the isolation structure 401 as semiconductor devices, for being played to adjacent devices or adjacent fin Buffer action.In the present embodiment, the material of the isolation structure 401 is silica.In other embodiments, the isolation structure Material can also be silicon nitride or silicon oxynitride.

In the present embodiment, the gate structure 450 is metal gate structure (metal gate), the gate structure 450 It conducting for controlling formed semiconductor structure raceway groove and blocks.

Specifically, the gate structure 450 includes high-k gate dielectric layer and the metal layer positioned at high-k gate dielectric layer surface.

The areas the P doped epitaxial floor 531 is used for the source region as the P-type device or drain region.

In the present embodiment, the areas the P doped epitaxial floor 531 includes the first p-type doped epitaxial floor (not indicating) and is located at The second p-type doped epitaxial layer (not indicating) on the first p-type doped epitaxial layer；Wherein, the first p-type doped epitaxial layer For the first semiconductor layer doped with p-type ion, the second p-type doped epitaxial layer is to be led doped with the second the half of p-type ion Body layer.

First semiconductor layer and the second semiconductor layer can be used for providing action of compressive stress for the channel region of P-type device, To improve the carrier mobility of P-type device.

It should be noted that the doping concentration of p-type ion is higher in the areas the P doped epitaxial floor 531, that accordingly plays carries It is more apparent for action of compressive stress；But the higher corresponding contact resistance for also resulting in contact hole plug of the doping concentration of p-type ion It is excessive.Therefore, while in order to ensure to provide action of compressive stress, reduce contact resistance, the second p-type doped epitaxial layer is mixed Heteroion concentration is less than the Doped ions concentration of the first p-type doped epitaxial layer.Wherein, the first p-type doped epitaxial layer Doping concentration with the second p-type doped epitaxial layer is depending on actual process demand.

In the present embodiment, in the first p-type doped epitaxial layer the atom percentage content of Ge be 30% to 60%, B from The doping concentration of son is 1.4E21atom/cm³To 2.6E21atom/cm³；The atom hundred of Ge in the first p-type doped epitaxial layer It is 1.4E20atom/cm to divide than the doping concentration that content is 10% to 20%, B ions³To 2.6E20atom/cm³.And described The ratio of semiconductor layer thickness and second layer semiconductor thickness is 1:15 to 1:5.Wherein, the atom percentage content of Ge Refer to that the total atom number of Ge accounts for the percentage of the total atom number of Si and Ge.

The areas the N doped epitaxial floor 631 is used for the source region as N-type device or drain region.

Since the energy gap of second epitaxial layer is smaller, by second epitaxial layer, institute is advantageously reduced State the schottky barrier height of the areas N doped epitaxial floor 631 and channel region；And the doping of the second n-type doping epitaxial layer 636 from Son is N-type ion, to make the N-type ion concentration in the areas the N doped epitaxial floor 631 be improved.The areas N doped epitaxial Layer 631 directlys proportional to schottky barrier height to the contact resistance of contact hole plug contact zone and is inversely proportional with N-type ion concentration, Therefore by the second n-type doping epitaxial layer 636, contact resistance can be reduced.

In the present embodiment, the areas the N doped epitaxial floor 631 includes the first n-type doping epitaxial layer 635 and is located at described The second n-type doping epitaxial layer 636 on first n-type doping epitaxial layer 635；Wherein, the first n-type doping epitaxial layer 635 is Doped with the first epitaxial layer of N-type ion, the second n-type doping epitaxial layer 636 is the second extension doped with N-type ion Layer.

In other embodiments, the areas the N doped epitaxial floor is including the second n-type doping epitaxial layer and positioned at described second The first n-type doping epitaxial layer on n-type doping epitaxial layer.

In the present embodiment, the material of first epitaxial layer is Si, and the N-type ion is P ion, therefore the first N The material of type doped epitaxial layer 635 is the Si doped with P ion；Wherein, the doping concentration of P ion according to actual process demand and It is fixed.In the present embodiment, the doping concentration of P ion is 1E21atom/cm³To 2E21atom/cm³.In other embodiments, described The material of first epitaxial layer can also be SiC.

In the present embodiment, the material of second epitaxial layer is SiGe, and the N-type ion is P ion, therefore described second The material of n-type doping epitaxial layer 636 is the SiGe doped with P ion.

It should be noted that the doping concentration of P ion is unsuitable too small in the second n-type doping epitaxial layer 636.If P The doping concentration of ion is too small, then be easy to cause reduce contact resistance effect unobvious, and due to by P ion in sige Solid solubility limitation, in the present embodiment, the doping concentration of P ion is in the second n-type doping epitaxial layer 636 2.5E20atom/cm³To 1.8E21atom/cm³。

It should be noted that the atom percentage content of Ge is unsuitable too low, it is also unsuitable excessively high.If the atomic percent of Ge Content is too low, then the reducing effect unobvious of schottky barrier height；If the atom percentage content of Ge is excessively high, easy pair The electric property of formed N-type device causes harmful effect.For this purpose, in the present embodiment, the atom percentage content of Ge be 5% to 45%.Wherein, the atom percentage content of Ge refers to that the total atom number of Ge accounts for the percentage of the total atom number of Si and Ge.

The interlayer dielectric layer 402 is additionally operable to be described first for realizing the electric isolution between adjacent semiconductor constructs The formation process of contact hole plug 451 provides technique platform.

In the present embodiment, the interlayer dielectric layer 402 is located in the substrate of the exposing of the gate structure 450, the interlayer The top of dielectric layer 402 is higher than the top of the gate structure 450.

The material of the interlayer dielectric layer 402 is insulating materials.In the present embodiment, the material of the interlayer dielectric layer 402 For silica.In other embodiments, the material of the interlayer dielectric layer can also be silicon nitride or silicon oxynitride.

It should be noted that the interlayer dielectric layer 402 is also located on the areas the P doped epitaxial floor 531.

Correspondingly, the first contact hole plug 451 extends not only through the interlayer dielectric layer 402 of the NMOS area II, described One contact hole plug 451 also extends through the interlayer dielectric layer 402 of the PMOS area I and is electrically connected with the areas the P doped epitaxial floor 531 It connects.

The first contact hole plug 451 of the PMOS area I is electrically connected with the areas the P doped epitaxial floor 531 realization, described The first contact hole plug 451 of NMOS area II is electrically connected with the areas the N doped epitaxial floor 631 realization, first contact hole Plug 451 is additionally operable to realize being electrically connected between device and device for realizing the electrical connection in semiconductor devices.

It should be noted that in the present embodiment, the semiconductor structure further includes：Through the NMOS area II and PMOS The interlayer dielectric layer 402 of 450 top of region I gate structures and the second contact hole plug being electrically connected with the gate structure 450 452 (as shown in figure 32).Second contact hole plug 452 is electrically connected with the realization of the gate structure 450, for realizing partly leading Electrical connection in body device is additionally operable to realize being electrically connected between device and device.

In the present embodiment, the material of first contact hole plug, 451 and second contact hole plug 452 is equal W.At other In embodiment, the material of first contact hole plug can also be the metal materials such as Al, Cu, Ag or Au, second contact The material of hole plug can also be the metal materials such as Al, Cu, Ag or Au.

It should also be noted that, in order to reduce the contact resistance of contact zone, the semiconductor structure further includes metal silication Nitride layer (not shown), the metal silicide layer are located at first contact hole plug 451 and the areas the N doped epitaxial floor 631 Between, and be also located between first contact hole plug 451 and the areas the P doped epitaxial floor 531.It is described in the present embodiment The material of metal silicide layer is TiSi.In other embodiments, the material of the metal silicide layer can also be NiSi.

Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

In the present embodiment, the semiconductor structure includes being located at the intrabasement areas N in NMOS area gate structure both sides Doped epitaxial layer, the areas the N doped epitaxial floor are the lamination that the first n-type doping epitaxial layer and the second n-type doping epitaxial layer are constituted Structure, wherein the first n-type doping epitaxial layer is the first epitaxial layer doped with N-type ion, outside second n-type doping It is the second epitaxial layer doped with N-type ion to prolong layer, and the energy gap of second epitaxial layer is less than first epitaxial layer Energy gap.Compared with the areas N, doped epitaxial floor only includes the scheme doped with the first epitaxial layer of N-type ion, outside second The energy gap for prolonging layer is smaller, therefore the present invention can reduce the areas the N doped epitaxial floor and ditch by second epitaxial layer The schottky barrier height in road area；In addition, the Doped ions of the second n-type doping epitaxial layer are N-type ion, make the areas N N-type ion concentration in doped epitaxial layer is improved；Since contact resistance is directly proportional to schottky barrier height, and and N-type Ion concentration is inversely proportional, therefore the contact resistance of semiconductor structure of the present invention is smaller, accordingly makes the driving current of N-type device It is improved, to make the electric property of the semiconductor structure be improved.

Claims

1. a kind of forming method of semiconductor structure, which is characterized in that including：

Substrate is provided, the substrate includes being used to form the NMOS area of N-type device；

Gate structure is formed on the substrate；

The areas N groove is formed in the substrate of NMOS area gate structure both sides；

Form N areas doped epitaxial floor in the areas N groove, the areas the N doped epitaxial floor is the first n-type doping epitaxial layer and the The laminated construction that two n-type doping epitaxial layers are constituted, wherein the first n-type doping epitaxial layer is doped with the first of N-type ion Epitaxial layer, the second n-type doping epitaxial layer are the second epitaxial layer doped with N-type ion, the forbidden band of second epitaxial layer Width is less than the energy gap of first epitaxial layer；

Interlayer dielectric layer is formed on the areas the N doped epitaxial floor；

The first contact openings for exposing the areas the N doped epitaxial floor are formed in the interlayer dielectric layer of the NMOS area；

The first contact hole plug being electrically connected with the areas the N doped epitaxial floor is formed in first contact openings.

2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material packet of first epitaxial layer Include Si；The material of second epitaxial layer is SiGe.

3. the forming method of semiconductor structure as described in claim 1, which is characterized in that the first n-type doping epitaxial layer Material be Si doped with P ion, the doping concentration of P ion is 1E21atom/cm³To 2E21atom/cm³。

4. the forming method of semiconductor structure as described in claim 1, which is characterized in that the second n-type doping epitaxial layer Material be SiGe doped with P ion, the doping concentration of P ion is 2.5E20atom/cm³To 1.8E21atom/cm³, Ge's Atom percentage content is 5% to 45%.

5. the forming method of semiconductor structure as described in claim 1, which is characterized in that the thickness of second epitaxial layer is 2nm to 8nm.

6. the forming method of semiconductor structure as described in claim 1, which is characterized in that form the areas the N doped epitaxial floor The step of include：The first epitaxial layer is formed in the areas N groove；

To the first epitaxial layer doped N-type ion, the first n-type doping epitaxial layer is formed；

The second epitaxial layer is formed on the first n-type doping epitaxial layer；

To the second epitaxial layer doped N-type ion, the second n-type doping epitaxial layer is formed；The second n-type doping epitaxial layer and The first n-type doping epitaxial layer constitutes the areas N doped epitaxial floor.

7. the forming method of semiconductor structure as described in claim 1, which is characterized in that the step of forming the areas the N groove Including：The initial groove in the areas N is formed in the substrate of NMOS area gate structure both sides；Using mixing etching gas to described The side wall of the initial groove in the areas N and bottom perform etching, and remove segment thickness base material, form the areas N groove, the mixing etching Gas includes silicon source gas and HCl gases.

8. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the silicon source gas is SiH₄、 Si₂Cl₂Or SiHCl₃。

9. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the step of forming the areas the N groove In, the silicon source gas is SiH₄, SiH₄Gas flow be 10sccm to 1000sccm, the gas flow of HCl be 5sccm extremely 100sccm, technological temperature are 400 DEG C to 700 DEG C.

10. the forming method of semiconductor structure as described in claim 1, which is characterized in that described in the step of providing substrate Substrate further includes being used to form the PMOS area of P-type device；

After forming gate structure on the substrate, before forming interlayer dielectric layer on the areas the N doped epitaxial floor, the shape Further include at method：The areas P groove is formed in the substrate of PMOS area gate structure both sides；The shape in the areas P groove At the areas P doped epitaxial floor；

In the step of forming interlayer dielectric layer on the areas the N doped epitaxial floor, the interlayer dielectric layer is also located at the areas P and mixes On miscellaneous epitaxial layer；

The step of the first contact openings for exposing the areas the N doped epitaxial floor are formed in the interlayer dielectric layer of the NMOS area In, first contact openings are also formed into the interlayer dielectric layer of the PMOS area and expose the areas the P doped epitaxial floor；

The step of the first contact hole plug being electrically connected with the areas the N doped epitaxial floor is formed in first contact openings In, first contact hole plug be also formed into the first contact openings of the PMOS area and with the areas P doped epitaxial Layer electrical connection.

11. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that the gate structure is pseudo- grid knot Structure；

After forming the areas the N doped epitaxial floor and the areas P doped epitaxial floor, formed before the interlayer dielectric layer, the formation side Method further includes：Bottom dielectric layer is formed in the substrate that the gate structure exposes, the bottom dielectric layer exposes the NMOS At the top of the gate structure of region and PMOS area；The gate structure is removed, gate openings are formed in the bottom dielectric layer； Metal gate structure is formed in the gate openings；

In the step of forming the interlayer dielectric layer, the interlayer dielectric layer covers the bottom dielectric layer and the metal gates Structure；

In the step of forming first contact openings, first contact openings also extend through the bottom dielectric layer；

After forming the interlayer dielectric layer, before forming the first contact hole plug in first contact openings, the formation Method further includes：It is formed in the interlayer dielectric layer above the NMOS area and PMOS area metal gate structure described in exposing Second contact openings of metal gate structure；

In the step of forming the first contact hole plug in first contact openings, also formed in second contact openings The second contact hole plug being electrically connected with the metal gate structure.

12. the forming method of semiconductor structure as described in claim 1, which is characterized in that described in the step of providing substrate Substrate includes substrate and discrete fin on the substrate；

In the step of forming gate structure on the substrate, the gate structure covers the fin across the fin Atop part surface and sidewall surfaces；

In the step of forming N area's grooves in the substrate of NMOS area gate structure both sides, in the NMOS area grid The areas N groove is formed in the fin of structure both sides.

13. a kind of semiconductor structure, which is characterized in that including：

Substrate, the substrate include the NMOS area for having N-type device；

Gate structure is located in the substrate；

Positioned at the intrabasement areas the N doped epitaxial floor in NMOS area gate structure both sides, the areas the N doped epitaxial floor is first The laminated construction that n-type doping epitaxial layer and the second n-type doping epitaxial layer are constituted, wherein the first n-type doping epitaxial layer is to mix Miscellaneous the first epitaxial layer for having N-type ion, the second n-type doping epitaxial layer is the second epitaxial layer doped with N-type ion, described The energy gap of second epitaxial layer is less than the energy gap of first epitaxial layer；

Interlayer dielectric layer is located on the areas the N doped epitaxial floor；

First contact hole plug runs through the interlayer dielectric layer of the NMOS area and is electrically connected with the areas the N doped epitaxial floor.

14. semiconductor structure as claimed in claim 13, which is characterized in that the material of first epitaxial layer includes Si；Institute The material for stating the second epitaxial layer is SiGe.

15. semiconductor structure as claimed in claim 13, which is characterized in that the material of the first n-type doping epitaxial layer is Doped with the Si of P ion, the doping concentration of P ion is 1E21atom/cm³To 2E21atom/cm³。

16. semiconductor structure as claimed in claim 13, which is characterized in that the material of the second n-type doping epitaxial layer is Doped with the SiGe of P ion, the doping concentration of P ion is 2.5E20atom/cm³To 1.8E21atom/cm³, the atomic percent of Ge It is 5% to 45% than content.

17. semiconductor structure as claimed in claim 13, which is characterized in that the thickness of second epitaxial layer be 2nm extremely 8nm。

18. semiconductor structure as claimed in claim 13, which is characterized in that the areas the N doped epitaxial floor is mixed including the first N-type Miscellaneous epitaxial layer and the second n-type doping epitaxial layer on the first n-type doping epitaxial layer.

19. semiconductor structure as claimed in claim 13, which is characterized in that the substrate further includes having P-type device PMOS area；

The semiconductor structure further includes：Positioned at the intrabasement areas the P doped epitaxial floor in PMOS area gate structure both sides；

The interlayer dielectric layer is also located on the areas the P doped epitaxial floor；

First contact hole plug also extends through the interlayer dielectric layer of the PMOS area and is electrically connected with the areas the P doped epitaxial floor It connects.

20. semiconductor structure as claimed in claim 13, which is characterized in that the substrate include substrate and be located at the lining Discrete fin on bottom；

The gate structure covers atop part surface and the sidewall surfaces of the fin across the fin；

The areas the N doped epitaxial floor is located in the fin of NMOS area gate structure both sides.