CN108628731B

CN108628731B - Method for selecting test instruction and processing equipment

Info

Publication number: CN108628731B
Application number: CN201710156359.1A
Authority: CN
Inventors: 程捷; 李景超; 李扬
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2017-03-16
Filing date: 2017-03-16
Publication date: 2020-12-22
Anticipated expiration: 2037-03-16
Also published as: CN108628731A

Abstract

The application discloses a method for selecting a test instruction and processing equipment, which are used for solving the problem that in the prior art, due to the fact that a plurality of screened test segments are discrete, a simulator consumes longer time when testing the test segments. The method comprises the following steps: the processing equipment divides the instruction to be tested into a plurality of segments, determines the number of each characteristic instruction contained in each segment, and determines the average value of each characteristic instruction contained in each segment; and selecting N segments from the M segments as test instructions according to the number of each characteristic instruction contained in each segment and the average value of each characteristic instruction contained in each segment, wherein the N segments comprise at least two continuous segments. Therefore, the accuracy of the performance index of the instruction to be tested, which is determined by the performance indexes of the N segments, can be ensured, the times of loading programs by the simulator is reduced, and the testing efficiency of the simulator is improved.

Description

Method for selecting test instruction and processing equipment

Technical Field

The present application relates to the field of computer technologies, and in particular, to a method for selecting a test instruction and a processing device.

Background

During the design and development process of a large program, a developer often needs to run the designed program through a simulator to perform a test, and then collect performance indexes of the program. For example, when designing a processor architecture, a developer tests a program of the designed processor architecture, and collects the number of Instructions (IPC) running Per clock Cycle, cache hit rate of each level, and energy consumption.

However, due to the design process of the program, multiple tests on the simulator are required. It is also well known that the runtime required by an emulator is much longer than the runtime required by a hardware platform when running the same program. Therefore, the simulator may take weeks or months or even longer to complete after the repeated test operation, which seriously affects the program development process and efficiency.

Research shows that during the running process of a program, each performance index can present obvious stage characteristics, so that on the premise of ensuring the accuracy of the finally obtained performance index of the whole program as much as possible, research personnel obtain the performance index of the whole program from the perspective of simplifying the test program by the following method:

1) the method comprises the steps that a processor obtains an instruction stream of a program to be tested and determines the type of a Basic Block (BB) contained in the instruction stream;

2) the processor cuts the instruction stream into a plurality of segments (intervals), determines the number of each BB in each segment, and obtains a Basic Block Vector (BBV) corresponding to each segment;

3) the processor performs K-Means (K-Means) clustering processing on the BBV of each obtained segment, divides the obtained BBV into a plurality of classes, screens out one BBV closest to the class center in each class, and finally determines test segments corresponding to the screened BBVs;

4) sequentially testing the plurality of determined test segments by the simulator to obtain the performance index of each test segment;

5) and the processor determines the proportion of the segment corresponding to each type of BBV in the whole program, namely determines the weight of the performance index of each test segment, and then calculates the weighted sum of the performance indexes of each test segment according to the determined weight of the performance index of each test segment, thereby obtaining the performance index of the whole program.

In the method, the processor screens the test fragments by adopting a K-Means clustering method, so that the obtained test fragments are discrete, namely the starting times of the simulator are the same as the number of the test fragments when the simulator tests the test fragments; in addition, since it takes a long time for the simulator to load (load) the test segment to the memory during each boot process, and it takes a short time for the simulator to run each test segment, in summary, the time taken for the simulator to test the plurality of test segments is still long.

Disclosure of Invention

The application provides a method for selecting a test instruction and a processing device, which are used for solving the problem that in the prior art, due to the fact that a plurality of screened test segments are discrete, a simulator consumes a long time when testing the test segments.

In a first aspect, the present application provides a method of selecting test instructions, the method comprising the steps of:

after dividing the instructions to be tested into M segments, the processing equipment determines the number of each characteristic instruction contained in each segment of the M segments, and further determines the average value of each characteristic instruction contained in each segment of the M segments; finally, the processing device selects N segments containing at least two continuous segments from the M segments as test instructions according to the number of each characteristic instruction contained in each segment of the M segments and the average value of each characteristic instruction contained in each segment of the M segments, wherein M is an integer greater than 1, and N is an integer greater than 1 and less than M.

In the method, the processing device selects the N segments according to an average value of each characteristic instruction contained in each segment of the M segments, so that a distribution of characteristic instructions in the N segments (i.e., test instructions) selected by the processing device by the method matches a distribution of characteristic instructions in the instructions to be tested, and an accuracy of a performance index of the instructions to be tested, which is determined by performance indexes of the N segments subsequently, can be ensured; compared with the conventional method for selecting N discrete test segments, the method has the advantages that the N segments selected by the processor comprise at least two continuous segments, so that the times of loading programs by the simulator in the subsequent test process are reduced, the time of testing the N segments by the simulator can be reduced, and the test efficiency of the simulator is improved. In summary, the method can ensure the accuracy of the performance index of the instruction to be tested, which is determined by the performance indexes of the N segments, and can reduce the time for testing the N segments by the simulator, thereby improving the testing efficiency of the simulator.

In one possible design, the processing device may select the N segments as the test instruction from the M segments by:

the processing equipment selects the N segments which have running time summation smaller than a preset first time threshold value and meet a first condition from the M segments as the test instruction; the first condition includes: the N segments comprise at least two continuous segments, and the difference value between the weighted sum of the feature vectors of all the segments in the N segments and the basic vector is smaller than a preset first threshold value, wherein the feature vector of each segment is a vector formed by the number of each feature instruction contained in each segment, and the basic vector is a vector formed by the average value of each feature instruction contained in each segment in the M segments.

By the method, the processing device can select the N segments in the M segments, wherein the distribution of the feature vectors of the included segments is similar to or consistent with that of the feature vectors in the M segments, so that the accuracy of the performance index of the instruction to be tested, which is determined by the performance indexes of the N segments subsequently, can be ensured.

In one possible design, the processing device selects, as the test instruction, the N segments having a running time less than the first time threshold and satisfying the first condition, from among the M segments, by:

step a: the processing equipment initializes residual vectors to be the basic vectors and initializes a subspace to be selected to be all X-subspaces, wherein the X-subspaces are spaces formed by characteristic vectors of any continuous X segments in the M segments, and X is an integer larger than 1 and smaller than M;

step b: the processing equipment selects a subspace with the smallest included angle with the residual vector in a subspace to be selected, determines a projection vector of the residual vector in the selected subspace, takes the difference between the residual vector and the projection vector as a new residual vector, and takes all subspaces of the subspace to be selected, from which the selected subspace is removed, as a new subspace to be selected;

step c: if the size of the residual error vector is smaller than the first threshold value or the sum of the running times of the segments corresponding to the feature vectors contained in all the selected subspaces is larger than a preset second time threshold value, the processing equipment takes the N segments corresponding to the feature vectors contained in all the selected subspaces as the test instruction; if the size of the residual vector is not smaller than the first threshold and the sum of the running times of the segments corresponding to the feature vectors contained in all the selected subspaces is not larger than the second time threshold, the processing equipment returns to execute the step b; wherein the second time threshold is less than the first time threshold.

By the method, the N fragments selected by the processing equipment comprise at least one continuous X fragment, so that the times of loading programs by the simulator can be further reduced in the subsequent test process, the time of testing the N fragments by the simulator is greatly reduced, and the test efficiency of the simulator is improved.

In one possible design, the second time threshold satisfies any one of the following conditions:

the second time threshold is greater than a difference between the first time threshold and a maximum run time, the maximum run time being a maximum of the run times of the M segments;

the second time threshold is greater than the difference between the first time threshold and X times a minimum run time, the minimum run time being a minimum of the run times of the M segments;

the second time threshold is greater than a difference between the first time threshold and the minimum run time.

By setting the second time threshold value through the method, when the sum of the running times of the segments corresponding to the feature vectors contained in all the selected subspaces by the processing device is greater than the second time threshold value, the processing device can be ensured not to select the subspaces again, and the flow of selecting the subspaces can be stopped. Because of the re-selection of the subspaces, the sum of the running times of the segments corresponding to the feature vectors contained in all the selected subspaces is greater than the first time threshold, and the condition that the sum of the running times of the N segments is less than the first time threshold is not met.

In one possible design, the processing device may also select, as the test instruction, the N segments that have a running time less than the first time threshold and satisfy the first condition, from among the M segments, by:

step a 1: the processing equipment initializes residual vectors to be the basic vectors and initializes a subspace to be selected to be all X-subspaces, wherein the X-subspaces are spaces formed by characteristic vectors of any continuous X segments in the M segments, and X is an integer larger than 1 and smaller than M;

step b 1: the processing equipment selects a first subspace with the smallest included angle with the residual vector in the subspace to be selected;

step c 1: the processing equipment determines a second subspace with a smaller included angle with the residual vector in the subspace to be selected;

step d 1: the processing device takes all subspaces except the selected first subspace in the to-be-selected subspace as new to-be-selected subspaces, and updates the residual vector in the following way:

the processing equipment finds out the correlation coefficients of all vectors in the first subspace and the residual vector and finds out the target direction with the maximum correlation coefficient; the processing device determines a target vector Y according to the determined direction, wherein one endpoint of the target vector Y is at a bisection angle position of the first subspace and the second subspace, and the other endpoint is an intersection point of the residual vector and the first subspace; the processing equipment takes the difference value of the residual error vector and Y as a new residual error vector;

step e 1: if the size of the residual error vector is smaller than the first threshold value or the sum of the running times of the segments corresponding to the feature vectors contained in all the selected subspaces is larger than a preset second time threshold value, the processing equipment takes the N segments corresponding to the feature vectors contained in all the selected subspaces as the test instruction; if the size of the residual vector is not less than the first threshold and the sum of the running times of the segments corresponding to the feature vectors contained in all the selected subspaces is not greater than the second time threshold, the processing device returns to execute step b 1; wherein the second time threshold is less than the first time threshold and greater than a difference between the first time threshold and a maximum run time, the maximum run time being a maximum of the run times of the M segments.

In one possible design, the processing device may further select the N segments as the test instruction from the M segments by:

firstly, the processing device takes at least two continuous segments of the M segments as a group, thereby determining S segment groups, wherein S is an integer greater than 1 and less than M, and one segment of the M segments is contained in one segment group of the S segment groups; then, the processing device determines a target vector of each segment group in the S segment groups, wherein the target vector of any segment group in the S segment groups is a vector formed by an average value of each feature instruction contained in each segment in the segment groups; finally, the processing device selects at least one segment group, in the S segment groups, in which a difference between a target vector and a basic vector is smaller than a preset second threshold, and uses the N segments included in the at least one segment group as the test instruction, where the basic vector is a vector composed of an average value of each feature instruction included in each of the M segments.

In the above method, the target vector of any segment group may represent the distribution of the feature instructions in all the segments included in the segment group, and therefore, with the above method, the distribution of the feature instructions in the segments included in each segment group in the at least one segment group selected by the processing device is similar to or matches the distribution of the feature vectors in the M segments. Therefore, the N segments are selected as the test segments by the method, so that the speed of selecting the test segments by the processing equipment can be increased, and the accuracy of the performance indexes of the to-be-tested instructions determined by the performance indexes of the N segments can be ensured.

In one possible design, the feature instructions are basic blocks contained in the M segments.

In a second aspect, an embodiment of the present application further provides a processing device, where the processing device has a function of implementing the processing device in the above method example. The functions can be realized by hardware, and the functions can also be realized by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the above-described functions.

In a possible design, the structure of the processing device includes a determining unit and a processing unit, and these units may perform corresponding functions in the foregoing method example, which is specifically referred to the detailed description in the method example, and is not described herein again.

In one possible design, the processing device includes a processor and a memory, and the processor is configured to support the processing device to execute the corresponding functions of the method. The memory is coupled to the processor and holds the program instructions and data necessary for the processor.

In a third aspect, the present application further provides a computer-readable storage medium for storing computer software instructions for executing the functions designed in any one of the first aspect and the first aspect, wherein the computer software instructions comprise a program designed to execute the method designed in any one of the first aspect and the first aspect.

In the embodiment of the application, the processing device divides the instructions to be tested into M segments, and determines the number of each characteristic instruction contained in each segment, so as to determine the average value of each characteristic instruction contained in each segment; the processing device may select N segments from the M segments as the test instructions according to the number of each of the M segments containing each of the feature instructions and an average value of each of the M segments containing each of the feature instructions, where the N segments include at least two consecutive segments. In this embodiment of the application, since the processing device selects the N segments according to an average value of each characteristic instruction included in each segment of the M segments, a distribution of characteristic instructions in the N segments (i.e., test instructions) selected by the processing device matches a distribution of characteristic instructions in the to-be-tested instructions, so as to ensure an accuracy of a performance index of the to-be-tested instruction determined by the performance indexes of the N segments subsequently; compared with the conventional method for selecting N discrete test segments, the N segments selected by the processor comprise at least two continuous segments, so that the times of loading programs by the simulator in the subsequent test process are reduced, the method provided by the embodiment of the application can reduce the time of testing the N segments by the simulator, and the test efficiency of the simulator is improved. Obviously, the method provided by the embodiment of the application can ensure the accuracy of the performance index of the instruction to be tested, which is determined by the performance indexes of the N segments, can reduce the time for testing the N segments by the simulator, and improve the testing efficiency of the simulator.

Drawings

Fig. 1 is a schematic diagram of a test system according to an embodiment of the present disclosure;

FIG. 2 is a flowchart of a method for selecting a test command according to an embodiment of the present disclosure;

FIG. 3 is a schematic subspace diagram according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a selection subspace provided in an embodiment of the present application;

fig. 5 is a schematic diagram of a target direction with the largest correlation coefficient with a residual vector according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a target vector according to an embodiment of the present disclosure;

fig. 7 is a block diagram of a processing device according to an embodiment of the present disclosure;

fig. 8 is a block diagram of another processing device according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clear, the present application will be further described in detail with reference to the accompanying drawings.

The application provides a method for selecting a test instruction and a processing device, which are used for solving the problem that in the prior art, due to the fact that a plurality of screened test segments are discrete, a simulator consumes a long time when testing the test segments. The method and the device are based on the same inventive concept, and because the principles of solving the problems of the method and the device are similar, the implementation of the device and the method can be mutually referred, and repeated parts are not repeated.

Hereinafter, some terms in the present application are explained to facilitate understanding by those skilled in the art.

The instructions to be tested, which may also be referred to as an instruction stream, are instructions in the running of a program, which are typically assembler instructions. Before the process of testing the program, a to-be-tested instruction of the to-be-tested program needs to be obtained; the simulator can run the to-be-tested instruction of the to-be-tested program, so that each performance index of the to-be-tested program is obtained.

The characteristic instruction is an instruction which influences the performance index in the instruction to be tested. Optionally, the characteristic instruction is a specific instruction in the instructions to be tested, such as a control instruction (e.g., a jump instruction, an interrupt instruction, etc.), or the characteristic instruction is a basic block composed of two adjacent control instructions and all instructions in between, which is not limited in this application.

The performance index of the segment or the instruction to be tested related to the present application is an IPC, a cache hit rate of each level (for example, a cache hit rate of a second layer (L2)), or a parameter such as energy consumption of a device running the segment or the instruction to be tested.

The plural in the present application means two or more.

In addition, it is to be understood that the terms first, second, etc. in the description of the present application are used for distinguishing between the descriptions and not necessarily for describing a sequential or chronological order.

The scheme provided by the application is specifically explained in the following with reference to the attached drawings.

Fig. 1 shows a test system to which the method for selecting a test instruction according to the embodiment of the present application is applied, and referring to fig. 1, the test system includes a processing device 101 and a simulator 102.

In the process that the test system tests a to-be-tested instruction corresponding to a to-be-tested program, the processing device 101 is configured to split the to-be-tested instruction into M segments, and determine the number of each characteristic instruction included in each of the M segments, so as to determine an average value of each characteristic instruction included in each of the M segments; and selecting N segments among the M segments as test instructions according to the number of each of the M segments containing each of the characteristic instructions and the average value of each of the M segments containing each of the characteristic instructions; wherein, at least two continuous fragments M in the N fragments are integers which are more than 1, and N is an integer which is more than 1 and less than M;

the simulator 102 is configured to test the test instruction selected by the processing device, so as to obtain a performance index of the test instruction.

Optionally, the processing device 101 may further obtain a performance index of the instruction to be tested according to the performance index of the test instruction obtained by the simulator 102.

The processing device 101 may be a computer or an integrated circuit. The simulator 102 may be a simulator or a software simulator, which is not limited in this application.

In the test system provided in the embodiment of the present application, since the processing device 101 selects the N segments according to an average value of each characteristic instruction included in each segment of the M segments, a distribution of characteristic instructions in the N segments (i.e., test instructions) selected by the processing device 101 matches a distribution of characteristic instructions in the to-be-tested instructions, so as to ensure an accuracy of a performance index of the to-be-tested instruction determined by performance indexes of the N segments subsequently; compared with the conventional method for selecting N discrete test segments, the N segments selected by the processor comprise at least two continuous segments, so that the times of loading programs by the simulator in the subsequent test process are reduced, the method provided by the embodiment of the application can reduce the time of testing the N segments by the simulator, and the test efficiency of the simulator is improved. Obviously, the test system provided by the embodiment of the application can ensure the accuracy of the performance index of the instruction to be tested, which is determined by the performance indexes of the N segments, and can reduce the time for testing the N segments by the simulator, thereby improving the test efficiency of the simulator.

The embodiment of the present application provides a method for selecting a test instruction, where the method is applicable to a test system shown in fig. 1, and a processing device related to the embodiment of the present application may be a processing device 101 in the test system. Referring to fig. 2, the flow of the method includes:

s201: the processing equipment divides an instruction to be tested into M segments, wherein M is an integer larger than 1.

Optionally, the instructions to be tested may be stored in a plurality of instruction stream files, that is, the instructions to be tested may be stored in a plurality of instruction stream files. Therefore, when the processing device executes S201, the instructions to be tested may be split in units of the instruction stream file storing the instructions to be tested, that is, the instructions stored in each instruction stream file are regarded as a segment.

S202: the processing device determines a number of each feature instruction included in each of the M segments.

Optionally, the characteristic instruction is a plurality of basic blocks included in the M segments (or in the instructions to be tested), or a plurality of control instructions. In the embodiments of the present application, only the characteristic instruction is taken as an example for description.

Optionally, the characteristic instruction may be preset by a tester, or determined by the processing device according to the instruction to be tested.

For example, the processing device determines a plurality of basic blocks according to the instructions to be tested by:

and the processing equipment determines all basic blocks contained in the instruction to be tested, classifies all the determined basic blocks by using the same basic block as a class, and thus determines a plurality of basic blocks.

S203: the processing device determines that each of the M segments contains an average value for each of the characteristic instructions.

Example 1, an instruction to be tested is divided into 3 segments, the number of characteristic instructions included in the instruction to be tested is 5, and the processing device determines that each segment respectively includes the number of 1 st to 5 th characteristic instructions as follows: fragment 1: {0,2,0,4,5}, fragment 2: {1,3,5,4,0}, fragment 3: {2,1,0,4,2}, then each of the 3 fragments contains an average of {1,2,5/3,4,7/3} for each of the characteristic instructions.

Since the characteristic instructions have an influence on the performance indexes of the instructions to be tested, the distribution condition of each characteristic instruction in the M segments (i.e., the instructions to be tested) can be used as a reference, so that it can be ensured that N segments most similar to or consistent with the distribution condition of each characteristic instruction in the M segments are selected as test instructions, and further the accuracy of the performance indexes of the instructions to be tested, which are determined by the performance indexes of the N segments, is ensured. In this embodiment, the distribution of each characteristic instruction in the M segments may be represented by an average value of each characteristic instruction contained in each segment in the M segments.

S204: the processing device selects N segments from the M segments as test instructions according to the number of each feature instruction contained in each segment in the M segments and the average value of each feature instruction contained in each segment in the M segments, wherein the N segments contain at least two continuous segments, and N is an integer greater than 1 and less than M.

The processing device may select the N segments among the M segments by a plurality of methods, and ensure that the distribution of characteristic instructions in the N segments coincides with the distribution of the M segment characteristic instructions. Wherein, the distribution of the characteristic instructions in the M segments can be represented by the basic vector. The basis vector consists of the average of each of the M segments containing each of the feature instructions, e.g., the average of each of the M segments containing each of the feature instructions is {1,2,5/3,4,7/3} in example 1, then the basis vector is [1,2,5/3,4,7/3 ]]Or [1,2,5/3,4,7/3 ]]^T。

Optionally, the selecting, by the processing device, the N segments from the M segments as the test instruction may include:

the processing equipment selects the N segments which have running time summation smaller than a preset first time threshold value and meet a first condition from the M segments as the test instruction;

the first condition includes: the N segments comprise at least two continuous segments, and the difference value between the weighted sum of the feature vectors of all the N segments and the basic vector is smaller than a preset first threshold value.

The feature vector of each segment is a vector composed of the number of each feature instruction contained in each segment, which is described by taking the segment 1 in example 1 as an example, and the number of each feature instruction contained in the segment 1 is {0,2,0,4,5}, so that the feature vector of the segment 1 is [0,2,0,4, 5}, and then]Or [0,2,0,4,5 ]]^T。

The first threshold is set according to a specific test scenario, and when the value of the first threshold is smaller, the distribution of the characteristic instructions in the N segments selected by the processing device in the method is more similar to the distribution of the characteristic instructions in the M segments.

Optionally, the running time of each of the M segments may be predicted for the processing device. Optionally, the processing device may predict the runtime of each segment by considering at least one of the number of instructions of each segment, characteristics of the instructions, and the working performance of the simulator, which is not limited in this embodiment of the present application.

In the above method, the distribution of the feature instructions in the N segments may be represented by a weighted sum of the feature vectors of all the N segments. Since the difference between the weighted sum of the feature vectors of all of the N segments and the basis vector is smaller than the first threshold, i.e. the weighted sum of the feature vectors of all of the N segments fits to the basis vector, the distribution of the feature vectors in the N segments is similar or coincides with the distribution of the feature vectors in the M segments. Therefore, the N segments are selected as the test segments by the method, so that the accuracy of the performance index of the instruction to be tested, which is determined by the performance indexes of the N segments, can be ensured.

In the method, compared with the method of selecting N discrete test segments by a traditional method, the N segments selected by the processor comprise at least two continuous segments, so that the continuous segments can be loaded into the simulator at one time in the subsequent test process, and due to the working characteristics of the simulator, the loading time for loading one segment by the simulator at one time is similar to the loading time for loading a plurality of segments at one time, but the time for loading each time is longer, so that the method can reduce the times for loading programs by the simulator, reduce the time for testing the N segments by the simulator and improve the test efficiency of the simulator.

In addition, in the method, the sum of the running times of the N segments selected by the processing device is smaller than the first time threshold, so that the time for testing the N segments by the simulator is within the range of the first time threshold, and the phenomenon of overlong testing time is avoided.

In the above-mentioned first method, the processing apparatus selects, as the test instruction, the N segments whose running time is less than the first time threshold and which satisfy the first condition, from among the M segments, that is, the N segments whose weighted sum of feature vectors of all segments is included is fitted to the basis vector. Optionally, the processing device may select the N segments from the M segments by a subspace regression algorithm.

Optionally, the present application provides a method for selecting the N segments by using a subspace regression algorithm, which specifically includes the following steps:

step b: the processing equipment selects a subspace with the smallest included angle with the residual vector in the subspace to be selected, determines a projection vector of the residual vector in the selected subspace, takes the difference between the residual vector and the projection vector as a new residual vector, and takes all subspaces of the subspace to be selected, from which the selected subspace is removed, as a new subspace to be selected;

Optionally, the second time threshold is greater than a difference between the first time threshold and a maximum running time, where the maximum running time is a maximum value of running times of the M segments, or

The second time threshold is greater than the difference between the first time threshold and X times the minimum running time, which is the minimum of the running times of the M segments, or

According to the vector theory in the mathematical field, the projection vector on any subspace selected by the processing device is a weighted sum of X eigenvectors contained in that subspace, and in the above method, the magnitude of the difference between the sum of the projection vectors on all subspaces selected by the processing device and the basis vector is smaller than the first threshold, that is, the difference between the weighted sum of the X eigenvectors (eigenvectors of N segments) contained in all subspaces selected by the processing device and the basis vector is smaller than the first threshold.

In the method, X is the number of continuous segments, and can be specifically set according to the requirements of specific test scenes, so that the freedom degree of selecting the continuous segments by the processing equipment can be improved.

Optionally, before step a, the processing device may determine all X-subspaces by:

the processing equipment divides every continuous X segments in the M segments into one group to generate a plurality of groups of segments;

the processing device composes the feature vectors of the X segments contained in each group of segments into an X-subspace.

Since in the mathematical domain, the vector may be a directional line, and a plurality of vectors may determine a plane, in this embodiment, the X-subspace corresponding to a set of segments is represented by a plane determined by X eigenvectors. As shown in FIG. 3, a set of segments includes two segments, wherein the feature vector of one segment is a1, and the feature vector of the other segment is a2, so that the two vectors define a plane C₁The plane is a subspace.

Optionally, based on the same principle as the method described above, the processing device may further select the N segments by:

step 1: the processing equipment initializes residual vectors to be the basic vectors and initializes a subspace to be selected to be all X-subspaces, wherein the X-subspaces are spaces formed by characteristic vectors of any continuous X segments in the M segments, and X is an integer larger than 1 and smaller than M;

step 2: the processing equipment selects a subspace with the smallest included angle with the residual vector in the subspace to be selected, determines a projection vector of the residual vector in the selected subspace, takes the difference between the residual vector and the projection vector as a new residual vector, and takes all subspaces of the subspace to be selected, from which the selected subspace is removed, as a new subspace to be selected;

and step 3: if the size of the residual vector is smaller than the first threshold value and the sum of the running times of the segments corresponding to the feature vectors contained in all the selected subspaces is smaller than the first time threshold value, the processing equipment returns to execute the step 2; if the size of the residual vector is not less than the first threshold or the sum of the running times of the segments corresponding to the feature vectors contained in all the selected subspaces is not less than the first time threshold, the processing device discards the subspace selected this time, and takes the N segments corresponding to the feature vectors contained in all the subspaces selected this time as the test instruction.

Example 2, the processing device initializes residual vector R as base vector B and initializes the subspace to be selected as all 2-subspaces. Since the subspace can be understood as a plane, the vector can be understood as a straight line. When the processing device selects the subspace, as shown in fig. 4, the processing device first needs to determine the subspace that best fits R (i.e. the subspace having the smallest included angle with R), assuming that the subspace is C₁. At this time, the processing device may determine C₁The 2 segments corresponding to the two feature vectors contained in the test segment can be used as test segments, the residual vectors and the subspace to be selected are continuously updated, and the subspace is continuously selected until the size of the residual vector which is updated last is smaller than the first threshold value, or the sum of the running time of the selected test segments is larger than the first threshold valueA second time threshold. Wherein the processing device is selecting C₁Then, the residual vector is updated to be R-U, the subspace to be selected is updated to be the subspace to be selected, and C is removed₁All subspaces of the back.

Optionally, an embodiment of the present application further provides another method for selecting the N segments by using a subspace regression algorithm, which specifically includes the following steps:

the processing device finds the correlation coefficients of all vectors in the first subspace and the residual vector, and finds the target direction with the maximum correlation coefficient, as shown in fig. 5; the processing device determines a target vector Y according to the determined direction, wherein one end point of the target vector Y is at a bisector angle position U of the first subspace and the second subspace, and the other end point is an intersection point of the residual vector and the first subspace, as shown in fig. 6; the processing equipment takes the difference value of the residual error vector and Y as a new residual error vector;

step e 1: if the size of the residual error vector is smaller than the first threshold value or the sum of the running times of the segments corresponding to the feature vectors contained in all the selected subspaces is larger than a preset second time threshold value, the processing equipment takes the N segments corresponding to the feature vectors contained in all the selected subspaces as the test instruction; if the size of the residual vector is not less than the first threshold and the sum of the running times of the segments corresponding to the feature vectors contained in all the selected subspaces is not greater than the second time threshold, the processing device returns to execute step b 1; the setting of the second time threshold is the same as the first method, and is not described herein again.

By the method, the processing equipment can also accurately select N fragments meeting the two conditions from the M fragments.

According to the vector theory in the mathematical field, any one vector in any subspace selected by the processing device is a weighted sum of X eigenvectors contained in the subspace, and in the above method, the magnitude of the difference between the sum of target vectors in all subspaces selected by the processing device and the basis vector is smaller than the first threshold, that is, the difference between the weighted sum of X eigenvectors (eigenvectors of N segments) contained in all subspaces selected by the processing device and the basis vector is smaller than the first threshold.

the processing device determines S segment groups in the M segments, wherein S is an integer greater than 1 and less than M, each segment group in the S segment groups comprises at least two continuous segments, and one segment in the M segments is contained in one segment group in the S segment groups;

the processing equipment selects at least one segment group of which the difference value between a target vector and a basic vector is smaller than a preset second threshold value from the S segment groups, and takes the N segments contained in the at least one segment group as the test instruction; the target vector of any one of the S segment groups is a vector composed of the average values of each feature instruction included in each segment of the segment group, and the basic vector is a vector composed of the average values of each feature instruction included in each segment of the M segments.

The second threshold is set according to a specific test scenario, and when the value of the second threshold is smaller, the distribution of the characteristic instructions in the N segments selected by the processing device in the method is more similar to the distribution of the characteristic instructions in the M segments.

In the following, the simulation times of the test instructions selected by the conventional method and the method provided by the embodiment of the present application are compared by using a specific example.

Example 3, assume that the loading time required for the simulator to load a test instruction once (to load a discrete segment, or to load several consecutive segments simultaneously) is 25 minutes, while the running time required to run a segment to be tested once is 1 minute.

Under the condition that the processing equipment adopts a K-Means clustering method, and 24 discrete test fragments are contained in the test instruction selected from the multiple fragments, the total time S (25) 24+1 (24) 624 minutes required by the simulator to test the 24 discrete test fragments is;

in a scenario where the processing device employs the method provided by the embodiment of the present application, the test instruction selected from the plurality of fragments includes 6 sets of fragments, and the 6 sets of fragment sets include 24 fragments, the simulator requires 25 × 6+1 × 24 minutes to test the 6 sets of fragments.

Through the comparison, under the condition that the processing equipment selects the same number of test segments through two methods, the total time for testing the test instruction by the simulator can be obviously reduced by adopting the method provided by the embodiment of the application to select the test instruction.

In this embodiment of the application, since the processing device selects the N segments according to an average value of each characteristic instruction included in each segment of the M segments, a distribution of characteristic instructions in the N segments (i.e., test instructions) selected by the processing device matches a distribution of characteristic instructions in the to-be-tested instructions, so as to ensure an accuracy of a performance index of the to-be-tested instruction determined by the performance indexes of the N segments subsequently; compared with the conventional method for selecting N discrete test segments, the N segments selected by the processor comprise at least two continuous segments, so that the times of loading programs by the simulator in the subsequent test process are reduced, the method provided by the embodiment of the application can reduce the time of testing the N segments by the simulator, and the test efficiency of the simulator is improved. Obviously, the method provided by the embodiment of the application can ensure the accuracy of the performance index of the instruction to be tested, which is determined by the performance indexes of the N segments, can reduce the time for testing the N segments by the simulator, and improve the testing efficiency of the simulator.

After the processing device adopts the method in the above embodiment, after selecting the N segments from the M segments as the test instruction, the simulator may perform Q tests on the selected N segments, where each test requires the simulator to load a discrete segment or a group of segments (including at least two continuous segments) into the memory and run, so as to obtain the performance indexes of the N segments (the performance indexes of each discrete segment and each group of segments in the N segments); wherein Q is an integer greater than 1 and less than N.

Optionally, the processing device may further obtain, but is not limited to, a performance index of the instruction to be tested according to the performance index of each discrete segment and each group of segments in the N segments in the following manners:

the processing device may obtain weights of performance indicators of each discrete segment and each group of segments in the N segments, then multiply the performance indicator of each discrete segment in the N segments by the corresponding weight, multiply the performance indicator of each group of segments in the N segments by the corresponding weight, and add the obtained calculation results as the performance indicator of the instruction to be tested; or

The processing device determines the quotient of M and N, determines the sum of the performance indexes of all discrete segments and all group segments in the N segments, and takes the product of the sum and the quotient as the performance index of the instruction to be tested.

The weight of each discrete segment of the N segments and the performance index of each group of segments may be set by a tester or determined by the processing device, which is not limited in this application.

By the method, the processing equipment can accurately obtain the performance index of the instruction to be tested according to the selected series performance indexes of the N segments.

Based on the same inventive concept as the method embodiment, the present application further provides a processing device, which is configured to implement the method for selecting a test instruction shown in fig. 2, as shown in fig. 7, where the processing device 700 includes: a determination unit 701 and a processing unit 702, wherein,

a determining unit 701, configured to divide an instruction to be tested into M segments, where M is an integer greater than 1; and are

Determining a number of each feature instruction contained in each of the M segments; and

determining an average value of each characteristic instruction contained in each of the M segments;

a processing unit 702, configured to select N segments from the M segments as test instructions according to the number of each feature instruction included in each segment of the M segments and an average value of each feature instruction included in each segment of the M segments, where the N segments include at least two consecutive segments, where N is an integer greater than 1 and less than M.

Optionally, the processing unit 702 is specifically configured to:

selecting the N segments which have running time sums smaller than a preset first time threshold and meet a first condition from the M segments as the test instruction;

the first condition includes: the N segments comprise at least two continuous segments, and the difference value between the weighted sum of the feature vectors of all the segments in the N segments and the basic vector is smaller than a preset first threshold value, wherein the feature vector of each segment is a vector formed by the number of each feature instruction contained in each segment, and the basic vector is a vector formed by the average value of each feature instruction contained in each segment in the M segments.

Optionally, when the running time of the N segments that are smaller than the first time threshold and satisfy the first condition is selected as the test instruction from the M segments, the processing unit 702 is specifically configured to execute the following steps:

step a: initializing a residual vector as the basic vector, and initializing a subspace to be selected as all X-subspaces, wherein the X-subspaces are spaces formed by the feature vectors of any continuous X segments in the M segments, and X is an integer larger than 1 and smaller than M;

step b: selecting a subspace with the smallest included angle with the residual vector in a subspace to be selected, determining a projection vector of the residual vector in the selected subspace, taking the difference between the residual vector and the projection vector as a new residual vector, and taking all subspaces of the subspace to be selected, from which the selected subspace is removed, as new subspaces to be selected;

step c: if the size of the residual error vector is smaller than the first threshold value or the sum of the running times of the segments corresponding to the feature vectors contained in all the selected subspaces is larger than a preset second time threshold value, taking the N segments corresponding to the feature vectors contained in all the selected subspaces as the test instruction; if the size of the residual vector is not smaller than the first threshold value and the sum of the running times of the segments corresponding to the feature vectors contained in all the selected subspaces is not larger than the second time threshold value, returning to execute the step b; wherein the second time threshold is less than the first time threshold.

Optionally, the processing unit 702 is specifically configured to:

determining S fragment groups in the M fragments, wherein S is an integer greater than 1 and less than M, each fragment group in the S fragment groups comprises at least two continuous fragments, and one fragment in the M fragments is contained in one fragment group in the S fragment groups;

selecting at least one segment group of which the difference value between the target vector and the basic vector is smaller than a preset second threshold value from the S segment groups, and taking the N segments contained in the at least one segment group as the test instruction; the target vector of any one of the S segment groups is a vector composed of the average values of each feature instruction included in each segment of the segment group, and the basic vector is a vector composed of the average values of each feature instruction included in each segment of the M segments.

Optionally, the characteristic instruction is a basic block included in the M segments.

In this embodiment of the application, since the processing device selects the N segments according to an average value of each characteristic instruction included in each segment of the M segments, a distribution of characteristic instructions in the N segments (i.e., test instructions) selected by the processing device matches a distribution of characteristic instructions in the to-be-tested instructions, so as to ensure an accuracy of a performance index of the to-be-tested instruction determined by the performance indexes of the N segments subsequently; compared with the method for selecting N discrete test segments by the traditional method, the N segments selected by the processor comprise at least two continuous segments, so that the times of loading programs by the simulator in the subsequent test process are reduced, the processing equipment provided by the embodiment of the application can reduce the time of testing the N segments by the simulator, and the test efficiency of the simulator is improved. Obviously, the processing device provided in the embodiment of the present application can ensure the accuracy of the performance index of the instruction to be tested, which is determined by the performance indexes of the N segments, and can reduce the time for testing the N segments by the simulator, thereby improving the testing efficiency of the simulator.

The division of the modules in the embodiments of the present application is schematic, and only one logical function division is provided, and in actual implementation, there may be another division manner, and in addition, each functional module in each embodiment of the present application may be integrated in one processor, may also exist alone physically, or may also be integrated in one module by two or more modules. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.

Where the integrated modules are implemented in hardware, as shown in fig. 8, the processing device 800 may include a processor 801 and a memory 802. The hardware of the entity corresponding to the above modules may be the processor 801. The processor 801 may be a Central Processing Unit (CPU), a digital Processing module, or the like. The memory 802 is used for storing programs executed by the processor 801. The Memory 802 may be a non-volatile Memory, such as a Hard Disk Drive (HDD) or a Solid-State Drive (SSD), and may also be a volatile Memory (RAM), such as a Random-Access Memory (RAM). The memory 802 may also be, but is not limited to, any other medium that can be used to carry or store program code in the form of instructions or data structures and that can be accessed by a computer.

The processor 801 is configured to execute the program code stored in the memory 802, and is specifically configured to perform the method according to the embodiment shown in fig. 2. Reference may be made to the method described in the embodiment shown in fig. 2, which is not described herein again.

Optionally, the processing device 800 provided in this embodiment of the present application may further include a communication interface 803, where the communication interface 803 is used for communicating with other devices (e.g., an emulator).

The specific connection medium among the communication interface 803, the processor 801, and the memory 802 is not limited in the embodiments of the present application. In the embodiment of the present application, the processor 801, the memory 802, and the communication interface 803 are connected by a bus 804 in fig. 8, the bus 804 is represented by a thick line in fig. 8, and the connection manner between other components is merely illustrated schematically and is not limited thereto. The bus 804 may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 8, but this is not intended to represent only one bus or type of bus.

The embodiment of the present invention further provides a computer-readable storage medium, which is used for storing computer software instructions required to be executed for executing the processor, and which contains a program required to be executed for executing the processor.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A method of selecting a test instruction, the method comprising:

dividing an instruction to be tested into M segments by using the processing equipment, wherein M is an integer greater than 1;

the processing device determining a number of each feature instruction contained in each of the M segments;

the processing device determines an average value of each characteristic instruction contained in each of the M segments;

the processing device selects N segments from the M segments as test instructions according to the number of each characteristic instruction contained in each segment of the M segments and the average value of each characteristic instruction contained in each segment of the M segments, wherein the N segments comprise at least two continuous segments, and N is an integer greater than 1 and less than M.

2. The method according to claim 1, wherein the selecting, by the processing device, the N segments among the M segments as the test instructions according to the number of each type of feature instruction included in each segment of the M segments and an average value of each type of feature instruction included in each segment of the M segments comprises:

3. The method of claim 2, wherein the processing device selects, as the test instruction, the N segments having a running time less than the first time threshold and satisfying the first condition from among the M segments, comprising:

4. The method according to claim 1, wherein the selecting, by the processing device, the N segments among the M segments as the test instructions according to the number of each type of feature instruction included in each segment of the M segments and an average value of each type of feature instruction included in each segment of the M segments comprises:

5. The method according to any one of claims 1 to 4, wherein the characteristic instruction is a basic block contained in the M segments.

6. A processing device, comprising:

the device comprises a determining unit, a judging unit and a judging unit, wherein the determining unit is used for dividing an instruction to be tested into M segments, and M is an integer larger than 1; and are

and the processing unit is used for selecting N segments from the M segments as the test instruction according to the number of each characteristic instruction contained in each segment of the M segments and the average value of each characteristic instruction contained in each segment of the M segments, wherein the N segments comprise at least two continuous segments, and N is an integer greater than 1 and less than M.

7. The processing device according to claim 6, wherein the processing unit is specifically configured to:

8. The processing apparatus according to claim 7, wherein the processing unit, when selecting, as the test instruction, the N segments that have a running time less than the first time threshold and satisfy the first condition from among the M segments, is specifically configured to perform the steps of:

9. The processing device according to claim 6, wherein the processing unit is specifically configured to:

10. The processing device according to any of claims 6 to 9, wherein the characteristic instruction is a basic block contained in the M segments.

11. A processing device, characterized in that the processing device comprises: a processor, a bus, and a memory, wherein,

the processor and the memory are connected through the bus;

the processor invokes instructions stored in the memory to perform the method of any of claims 1-5.