CN108628699B - ECC-based FLASH data exception processing method and device - Google Patents
ECC-based FLASH data exception processing method and device Download PDFInfo
- Publication number
- CN108628699B CN108628699B CN201810451180.3A CN201810451180A CN108628699B CN 108628699 B CN108628699 B CN 108628699B CN 201810451180 A CN201810451180 A CN 201810451180A CN 108628699 B CN108628699 B CN 108628699B
- Authority
- CN
- China
- Prior art keywords
- flash
- address
- data
- chip
- reading
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000003672 processing method Methods 0.000 title abstract description 4
- 238000000034 method Methods 0.000 claims abstract description 66
- 230000002159 abnormal effect Effects 0.000 claims abstract description 33
- 238000012545 processing Methods 0.000 claims abstract description 18
- 238000013479 data entry Methods 0.000 claims description 19
- 238000010586 diagram Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 238000004590 computer program Methods 0.000 description 2
- 230000006399 behavior Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Retry When Errors Occur (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention provides a FLASH data exception processing method and device based on ECC, wherein the method comprises the following steps: the method comprises the steps that an MCU judges whether a read or written on-chip flash address is a protected address or not in the process of reading or writing on-chip flash data of a current flash sector; if yes, judging whether to enter abnormal interrupt processing; if yes, the reading instruction or the writing instruction is corrected to be the address of the Flash in the next chip, so that the system can be ensured to normally operate under the ECC occurrence state as far as possible.
Description
Technical Field
The invention relates to the technical field of computer processing, in particular to a FLASH data exception handling method and device based on ECC.
Background
EEPROM is the most ideal non-volatile memory for microprocessors to read, write, and update variables. In a microcontroller without an internal EEPROM, internal Flash can be simulated into the EEPROM to achieve the aim.
When the currently used FLASH module based on the ECC is used for simulating the function of the EEPROM, the FLASH may enter a protection mode due to behaviors such as data operation abnormality (improper reading and writing or some external reasons, such as power failure during writing data); when reading the data of the abnormal address under the condition that the FLASH enters the protection mode, the MCU in the controller can be reset or enter some abnormal states, and finally the function of the controller is abnormal, so that danger is caused.
Disclosure of Invention
The invention provides a FLASH data exception processing method and device based on ECC, which at least partially solves the technical problems.
In a first aspect, the present invention provides an ECC-based FLASH data exception handling method, including:
the method comprises the steps that an MCU judges whether a read or written on-chip flash address is a protected address or not in the process of reading or writing on-chip flash data of a current flash sector;
if yes, judging whether to enter abnormal interrupt processing;
if yes, the reading instruction or the writing instruction is corrected to be the address of the next Flash in the chip.
Preferably, the method further comprises:
the Flash abnormal mark position corresponding to the protected address is valid, and abnormal interrupt processing is quitted;
judging whether the flash abnormal zone bit of the protected address is valid or not;
if so, giving a default invalid value to a predicted target address, setting the Flash abnormal flag position as invalid, and reading data of the next on-chip Flash address or writing data into the next on-chip Flash address.
Preferably, before determining whether the read or written on-chip flash address is a protected address, the method further includes:
judging whether all data entries in the Flash sector are valid or not;
if so, the data entry is populated with entry data.
Preferably, after determining whether all data entries in the Flash sector are valid, the method further includes:
if not, judging whether all the backup sectors are completely inquired;
if not, judging whether the currently inquired data item is effective or not;
if yes, repeating the step of judging whether all data items in the Flash sector are valid.
Preferably, after determining whether the currently queried data entry is valid, the method further includes:
if not, searching a data area of the current flash sector, acquiring data, and filling the data into the currently inquired data entry;
judging whether reading of the current flash sector is finished;
if yes, repeating the step of judging whether all data items in the Flash sector are valid.
Preferably, the method further comprises:
and generating MCU fault information, and sending the MCU fault information to a display device so that the display device displays the MCU fault information.
In a second aspect, the present invention further provides an ECC-based FLASH data exception handling apparatus, which is characterized by comprising:
the first judging unit is used for judging whether the read or written on-chip flash address is a protected address or not in the process of reading or writing on-chip flash data of the current flash sector by the MCU;
the second judgment unit is used for judging whether to enter abnormal interrupt processing if the judgment unit is yes;
and the correcting unit is used for correcting the reading instruction or the writing instruction into reading or writing the next on-chip Flash address if the Flash address is in the correct state.
Preferably, the apparatus further comprises:
the setting unit is used for setting the Flash abnormal mark position corresponding to the protected address to be effective and exiting the abnormal interrupt processing;
a third judging unit, configured to judge whether a flash exception flag of the protected address is valid;
and the assignment unit is used for assigning a default invalid value to a predicted target address if the Flash memory is in the invalid state, reading the data of the next Flash memory address in the chip or writing the data into the next Flash memory address in the chip.
In a third aspect, the present invention provides an electronic device, including:
at least one processor; and
at least one memory communicatively coupled to the processor, wherein:
the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform the method.
In a fourth aspect, the invention also provides a non-transitory computer-readable storage medium storing computer instructions that cause the computer to perform the method.
According to the technical scheme, in the FLASH data exception handling method based on the ECC, the MCU judges whether the read or written in-chip FLASH address is a protected address or not in the process of reading or writing in-chip FLASH data of the current FLASH sector; if yes, judging whether to enter abnormal interrupt processing; if yes, the reading instruction or the writing instruction is corrected to be the address of the Flash in the next chip, so that the system can be ensured to normally operate under the ECC occurrence state as far as possible.
Drawings
Fig. 1 is a flowchart of a FLASH data exception handling method based on ECC according to an embodiment of the present invention;
fig. 2 is a flowchart of a FLASH data exception handling method based on ECC according to another embodiment of the present invention;
FIG. 3 is a flowchart of a FLASH data exception handling method based on ECC according to another embodiment of the present invention;
fig. 4 is a flowchart of a FLASH data exception handling method based on ECC according to another embodiment of the present invention;
FIG. 5 is a flowchart of a FLASH data exception handling method based on ECC according to another embodiment of the present invention;
FIG. 6 is a flowchart of a FLASH data exception handling method based on ECC according to another embodiment of the present invention;
fig. 7 is a schematic block diagram of an ECC-based FLASH data exception handling apparatus according to another embodiment of the present invention;
fig. 8 is a block diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a flowchart of a FLASH data exception handling method based on ECC according to an embodiment of the present invention.
As shown in fig. 1, an ECC-based FLASH data exception handling method includes:
s101, judging whether a read or written on-chip flash address is a protected address or not by an MCU (micro control unit) in the process of reading or writing on-chip flash data of a current flash sector; if yes, go to step S102; if not, executing step S102';
s102, judging whether to enter abnormal interrupt processing; if yes, go to step S103; if not, executing step S103'; s103, correcting the reading instruction or the writing instruction to read or write the next Flash address in the chip.
In this step, the next on-chip Flash address is the next on-chip Flash address according to the preset reading or writing order.
S103', reading or writing according to a normal reading or writing method.
It will be appreciated that the reading or writing according to the normal reading or writing method may be reading or writing to the on-chip flash address.
S102', reading or writing the flash address in the chip.
Fig. 2 is a flowchart of a FLASH data exception handling method based on ECC according to another embodiment of the present invention.
Steps S201 to S203 'in fig. 2 are the same as steps S101 to S103' described above and will not be described again.
As a preferred embodiment, the method further comprises:
s204, the Flash abnormal mark position corresponding to the protected address is valid, and abnormal interrupt processing is quitted;
in this step, the address is an on-chip Flash address, which is not described in detail below.
S205, judging whether the flash abnormal zone bit of the protected address is valid or not; if yes, go to step S206; if not, go to step S206'.
And S206, giving a default invalid value to a predicted target address, setting the Flash abnormal flag position as invalid, and reading data of the next on-chip Flash address or writing data into the next on-chip Flash address.
S206', read the next address data.
Fig. 3 is a flowchart of a FLASH data exception handling method based on ECC according to another embodiment of the present invention.
Steps S303 to S308 'in fig. 3 are the same as steps S201 to S206' described above, and are not described again.
As a preferred embodiment, before the step S303, the method further includes:
s301, judging whether all data entries in the Flash sector are valid or not; if yes, go to step S302.
S302, filling entry data into the data entry.
Fig. 4 is a flowchart of a FLASH data exception handling method based on ECC according to another embodiment of the present invention.
Steps S401 to S408 'in fig. 4 are the same as steps S301 to S308' described above, and are not described again.
As a preferred embodiment, after the step S401, the method further includes:
if not, executing step S409;
s409, judging whether all the backup sectors are queried; if not, go to step S410;
s410, judging whether the currently inquired data item is effective;
it should be noted that, in the present invention, each data entry is sequentially queried according to a preset order.
If yes, the step S401 is repeated.
Fig. 5 is a flowchart of a FLASH data exception handling method based on ECC according to another embodiment of the present invention.
Steps S501 to S510 in fig. 5 are the same as steps S401 to S410, and are not described again.
As a preferred embodiment, after the step S510, the method further includes:
if not, executing step S511;
s511, searching a data area of the current flash sector, acquiring data, and filling the data into the currently inquired data entry;
it is worth noting that the query sector is a sector-by-sector sequential query starting from the newest data storage sector, and the valid contents of the newest data entry are filled in the address of the currently queried data entry. After the current search entry queries valid data once, the data entry is set to be valid, and the search is not executed any more.
S512, judging whether reading of the current flash sector is finished; if yes, repeating the step S501; if not, go to step S513;
and S513, continuing to read the current flash sector until the reading is finished.
Fig. 6 is a flowchart of a FLASH data exception handling method based on ECC according to another embodiment of the present invention.
Steps S601 to S613 in fig. 6 are the same as steps S501 to S513 described above, and are not described again.
As a preferred embodiment, the method further comprises:
and S614, generating MCU fault information, and sending the MCU fault information to a display device so that the display device displays the MCU fault information. So that information about the occurrence of an abnormality can be recorded.
In the FLASH data exception handling method based on ECC, an MCU judges whether the read or written in-chip FLASH address is a protected address or not in the process of reading or writing in-chip FLASH data of the current FLASH sector; if yes, judging whether to enter abnormal interrupt processing; if so, correcting the reading instruction or the writing instruction to read or write the next Flash address in the chip, thereby ensuring that the system can normally operate in the ECC occurrence state as far as possible; ensuring that all data entries store data that is as efficient as possible. And after the data exception of the FLASH is eliminated, correcting the relevant FLASH sector.
Fig. 7 is a schematic block diagram of an ECC-based FLASH data exception handling apparatus according to another embodiment of the present invention.
An ECC-based FLASH data exception handling apparatus as shown in fig. 7 includes:
a first judging unit 701, configured to judge, by the MCU, whether a read or write on-chip flash address is a protected address in a process of reading or writing on-chip flash data of a current flash sector;
a second determining unit 702, configured to determine whether to enter an abnormal interrupt process if the determination result is positive;
and the correcting unit 703 is configured to correct the read instruction or the write instruction to read or write the next on-chip Flash address if the read instruction or the write instruction is correct.
In the device, the next on-chip Flash address is the next on-chip Flash address according to the preset reading or writing sequence.
As a preferred embodiment, the apparatus further comprises:
the setting unit is used for setting the Flash abnormal mark position corresponding to the protected address to be effective and exiting the abnormal interrupt processing;
a third judging unit, configured to judge whether a flash exception flag of the protected address is valid;
and the assignment unit is used for assigning a default invalid value to a predicted target address if the Flash memory is in the invalid state, reading the data of the next Flash memory address in the chip or writing the data into the next Flash memory address in the chip.
In the FLASH data exception handling method based on ECC, an MCU judges whether the read or written in-chip FLASH address is a protected address or not in the process of reading or writing in-chip FLASH data of the current FLASH sector; if yes, judging whether to enter abnormal interrupt processing; if so, correcting the reading instruction or the writing instruction to read or write the next Flash address in the chip, thereby ensuring that the system can normally operate in the ECC occurrence state as far as possible; ensuring that all data entries store data that is as efficient as possible. And after the data exception of the FLASH is eliminated, correcting the relevant FLASH sector.
Fig. 8 is a block diagram of an electronic device according to an embodiment of the present invention.
An electronic device as shown in fig. 8, comprising: a processor 801(processor), a memory 802(memory), and a bus 803; wherein,
the processor 801 and the memory 802 complete communication with each other through the bus 803;
the processor 801 is configured to call the program instructions in the memory 802 to execute the method provided by the above method embodiments, for example, including: the method comprises the steps that an MCU judges whether a read or written on-chip flash address is a protected address or not in the process of reading or writing on-chip flash data of a current flash sector; if yes, judging whether to enter abnormal interrupt processing; if yes, the reading instruction or the writing instruction is corrected to be the address of the next Flash in the chip.
The present invention also provides a non-transitory computer-readable storage medium storing computer instructions that cause the computer to perform a method provided by the above method embodiments, for example, comprising: the method comprises the steps that an MCU judges whether a read or written on-chip flash address is a protected address or not in the process of reading or writing on-chip flash data of a current flash sector; if yes, judging whether to enter abnormal interrupt processing; if yes, the reading instruction or the writing instruction is corrected to be the address of the next Flash in the chip.
It should be noted that, in the respective components of the apparatus of the present invention, the components therein are logically divided according to the functions to be implemented, but the present invention is not limited thereto, and the respective components may be re-divided or combined as needed, for example, some components may be combined into a single component, or some components may be further decomposed into more sub-components.
The various component embodiments of the invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that a microprocessor or Digital Signal Processor (DSP) may be used in practice to implement some or all of the functionality of some or all of the components in an apparatus according to an embodiment of the invention. The present invention may also be embodied as apparatus or device programs (e.g., computer programs and computer program products) for performing a portion or all of the methods described herein. Such programs implementing the present invention may be stored on computer-readable media or may be in the form of one or more signals. Such a signal may be downloaded from an internet website or provided on a carrier signal or in any other form.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
The above embodiments are only suitable for illustrating the present invention and not limiting the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so that all equivalent technical solutions also belong to the scope of the present invention, and the scope of the present invention should be defined by the claims.
Claims (8)
1. An ECC-based FLASH data exception handling method is characterized by comprising the following steps:
the method comprises the steps that an MCU judges whether a read or written on-chip flash address is a protected address or not in the process of reading or writing on-chip flash data of a current flash sector;
if yes, judging whether to enter abnormal interrupt processing;
if so, correcting the reading instruction or the writing instruction to read or write the next Flash address in the chip;
the Flash abnormal mark position corresponding to the protected address is valid, and abnormal interrupt processing is quitted;
judging whether the flash abnormal zone bit of the protected address is valid or not;
if so, giving a default invalid value to a predicted target address, setting the Flash abnormal flag position as invalid, and reading data of the next on-chip Flash address or writing data into the next on-chip Flash address.
2. The method of claim 1, wherein before determining whether the read or write on-chip flash address is a protected address, the method further comprises:
judging whether all data entries in the Flash sector are valid or not;
if so, the data entry is populated with entry data.
3. The method of claim 2, wherein after determining whether all data entries in the Flash sector are valid, the method further comprises:
if not, judging whether all the backup sectors are completely inquired;
if not, judging whether the currently inquired data item is effective or not;
if yes, repeating the step of judging whether all data items in the Flash sector are valid.
4. The method of claim 3, wherein after determining whether the currently queried data entry is valid, the method further comprises:
if not, searching a data area of the current flash sector, acquiring data, and filling the data into the currently inquired data entry;
judging whether reading of the current flash sector is finished;
if yes, repeating the step of judging whether all data items in the Flash sector are valid.
5. The method of claim 1, further comprising:
and generating MCU fault information, and sending the MCU fault information to a display device so that the display device displays the MCU fault information.
6. An ECC-based FLASH data exception handling device, comprising:
the first judging unit is used for judging whether the read or written on-chip flash address is a protected address or not in the process of reading or writing on-chip flash data of the current flash sector by the MCU;
the second judgment unit is used for judging whether to enter abnormal interrupt processing if the judgment unit is yes;
the correcting unit is used for correcting the reading instruction or the writing instruction into reading or writing a next on-chip Flash address if the Flash address is in the first on-chip Flash address;
the setting unit is used for setting the Flash abnormal mark position corresponding to the protected address to be effective and exiting the abnormal interrupt processing;
a third judging unit, configured to judge whether a flash exception flag of the protected address is valid;
and the assignment unit is used for assigning a default invalid value to a predicted target address if the Flash memory is in the invalid state, reading the data of the next Flash memory address in the chip or writing the data into the next Flash memory address in the chip.
7. An electronic device, comprising:
at least one processor; and
at least one memory communicatively coupled to the processor, wherein:
the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform the method of any of claims 1-5.
8. A non-transitory computer-readable storage medium storing computer instructions that cause a computer to perform the method of any one of claims 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810451180.3A CN108628699B (en) | 2018-05-11 | 2018-05-11 | ECC-based FLASH data exception processing method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810451180.3A CN108628699B (en) | 2018-05-11 | 2018-05-11 | ECC-based FLASH data exception processing method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108628699A CN108628699A (en) | 2018-10-09 |
| CN108628699B true CN108628699B (en) | 2021-10-19 |
Family
ID=63692804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810451180.3A Active CN108628699B (en) | 2018-05-11 | 2018-05-11 | ECC-based FLASH data exception processing method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108628699B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112968979B (en) * | 2020-12-10 | 2023-05-12 | 江苏奥雷光电有限公司 | Method for effectively preventing slave address abnormality in multi-slave system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102207913A (en) * | 2011-06-09 | 2011-10-05 | 中兴通讯股份有限公司 | Write protection control method and device in embedded system |
| CN102804146A (en) * | 2009-06-29 | 2012-11-28 | 桑迪士克科技股份有限公司 | System And Method Of Tracking Error Data Within A Storage Device |
| CN103092717A (en) * | 2013-01-18 | 2013-05-08 | 深圳市硅格半导体有限公司 | Flash memory data processing method and device |
| CN106991324A (en) * | 2017-03-30 | 2017-07-28 | 兴华永恒（北京）科技有限责任公司 | It is a kind of that the malicious code Tracking Recognition method that type is monitored is protected based on internal memory |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI332611B (en) * | 2007-05-24 | 2010-11-01 | Realtek Semiconductor Corp | Method for writing data in flash memory and error correction coding/decoding method thereof |
| CN106294089A (en) * | 2015-06-23 | 2017-01-04 | 阿里巴巴集团控股有限公司 | The method and apparatus assisting the access monitoring to monitored memory headroom |
| CN105183676A (en) * | 2015-10-21 | 2015-12-23 | 上海斐讯数据通信技术有限公司 | Memory write protection system and method |
| CN105974838A (en) * | 2016-05-10 | 2016-09-28 | 镇江恒驰科技有限公司 | Method for quickly responding to program operation endless loop of 9S12X-series single-chip microprocessor |
| CN106293832B (en) * | 2016-08-09 | 2020-01-14 | 上海盈方微电子有限公司 | SOC chip boot starting method and system |
-
2018
- 2018-05-11 CN CN201810451180.3A patent/CN108628699B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102804146A (en) * | 2009-06-29 | 2012-11-28 | 桑迪士克科技股份有限公司 | System And Method Of Tracking Error Data Within A Storage Device |
| CN102207913A (en) * | 2011-06-09 | 2011-10-05 | 中兴通讯股份有限公司 | Write protection control method and device in embedded system |
| CN103092717A (en) * | 2013-01-18 | 2013-05-08 | 深圳市硅格半导体有限公司 | Flash memory data processing method and device |
| CN106991324A (en) * | 2017-03-30 | 2017-07-28 | 兴华永恒（北京）科技有限责任公司 | It is a kind of that the malicious code Tracking Recognition method that type is monitored is protected based on internal memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108628699A (en) | 2018-10-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101969008B1 (en) | Techniques for handling errors in persistent memory | |
| CN103268201B (en) | A kind of date storage method, memory storage and read method | |
| JP2005190201A (en) | Information processor and rom image generation device for the same | |
| CN102750191A (en) | Method for initiating a refresh operation in a solid-state nonvolatile memory device | |
| WO2015103917A1 (en) | Management method and apparatus of wireless routing device | |
| US9311235B2 (en) | Method of erasing information stored in a nonvolatile rewritable memory, storage medium and motor vehicle computer | |
| US20080016415A1 (en) | Evaluation system and method | |
| CN109086086B (en) | Starting method and device of non-space-sharing multi-core CPU | |
| CN109614119B (en) | Burning method, device, electronic equipment and medium | |
| CN112540725A (en) | Nonvolatile data storage method, embedded system and storage medium | |
| US9786373B2 (en) | EEPROM backup method and device | |
| CN107168750B (en) | Firmware upgrade protection method and system | |
| EP0023821A2 (en) | Apparatus and method for checking a memory and a computer system including a memory and apparatus for checking the memory | |
| CN108628699B (en) | ECC-based FLASH data exception processing method and device | |
| CN107657153B (en) | Code protection method and device for flash area in chip | |
| JP5504604B2 (en) | RAM diagnostic device | |
| CN112667442A (en) | Control method, device and equipment based on nonvolatile memory device starting system | |
| CN108647119A (en) | The startup method, apparatus and equipment of linux system | |
| CN110781031B (en) | Controller data recovery method and device, controller and automobile | |
| CN112634964A (en) | Data writing method, device and equipment of electronic control unit and storage medium | |
| CN113468008B (en) | Detection method, device, equipment and storage medium of safety controller | |
| CN104751881A (en) | flash memory burning method | |
| CN117170753B (en) | Program processing method, program processing device, vehicle, and storage medium | |
| CN109189328B (en) | Index table protection method suitable for NAND Flash controller | |
| KR20140136665A (en) | Calibration apparatus and method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |