CN108598167A - Silicon ldmos transistor on a kind of insulating layer with a variety of part buried layers - Google Patents
Silicon ldmos transistor on a kind of insulating layer with a variety of part buried layers Download PDFInfo
- Publication number
- CN108598167A CN108598167A CN201810410509.1A CN201810410509A CN108598167A CN 108598167 A CN108598167 A CN 108598167A CN 201810410509 A CN201810410509 A CN 201810410509A CN 108598167 A CN108598167 A CN 108598167A
- Authority
- CN
- China
- Prior art keywords
- buried layer
- silicon
- layer
- type
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 197
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 196
- 239000010703 silicon Substances 0.000 title claims abstract description 196
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 74
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 74
- 239000001301 oxygen Substances 0.000 claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 239000002210 silicon-based material Substances 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- -1 source region Substances 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 41
- 230000005684 electric field Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 9
- 230000007423 decrease Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 238000011161 development Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses silicon ldmos transistors on a kind of insulating layer with a variety of part buried layers.It is full oxygen buried layer on substrate layer of the present invention；It is silicon film on full oxygen buried layer；Source region and silicon body are located at silicon film side, and source region is located at the top of silicon film；Drift region, drain region, part oxygen buried layer, part P-type silicon buried layer and part N-type silicon buried layer are located at the silicon film other side, and drain region is located at the top of silicon film；Region between drain region, part oxygen buried layer, part P-type silicon buried layer and part N-type silicon buried layer is drift region；Part P-type silicon buried layer is located above the oxygen buried layer of part, and part oxygen buried layer length is more than part P-type silicon buried layer length；Raceway groove is provided by the silicon body between source region and drift region；Device top layer includes gate oxide, extension oxide layer, source electrode, gate electrode and drain electrode；Gate oxide is located above raceway groove；Extension oxide layer is located above drift region；Gate oxide is all covered by gate electrode.The breakdown voltage and on-resistance properties of the present invention is more superior.
Description
Technical field
The invention belongs to semiconductor high-voltage power integrated circuit devices fields, and in particular to one kind is based on silicon on insulating layer
(Silicon-On-Insulator, SOI) substrate, and there is part P-type silicon buried layer (Partial Buried P simultaneously
Layer, PBPL), part N-type silicon buried layer (Partial Buried N Layer, PBNL) and part oxygen buried layer (Partial
Buried Oxide Layer, PBOX) lateral double diffusion metal oxide semiconductor (Lateral Double-diffused
Metal-Oxide-Semiconductor, LDMOS) transistor, i.e., silicon LDMOS is brilliant on the insulating layer with a variety of part buried layers
Body pipe (Hybrid Multiple Partial Buried Layers SOI LDMOS), english abbreviation HMPBLSOI LDMOS.
Background technology
With the development of semiconductor process technique and power integrated circuit, need of the society to high-power semiconductor devices
Ask increasing, the requirement to its performance is also higher and higher, and therefore, the performance for improving its associated high voltage high power device is very heavy
It wants.And LDMOS have the advantages that compared with conventional MOS device it is very much, such as：Gain is big, work efficiency is high, the linearity is good, opens
Pass transfer characteristic is good and heat conductivility is good.In addition, on insulating layer silicon (SOI) technology compared with traditional junction isolation technology,
It has huge advantage of ideal isolation and low current leakage, this influence for high-voltage switch gear performance is very big.Thus SOI's
LDMOS is improved in technical foundation, the performances such as breakdown voltage and conducting resistance of device will be more superior, high to improving
It presses high power device performance and promotes the development of semiconductor power integrated circuit that there is positive effect.
Invention content
It is a kind of with height the purpose of the present invention is being provided for the development of High voltage power device and large scale integrated circuit
Silicon ldmos transistor on the insulating layer of breakdown voltage, low on-resistance and high driving ability.
The present invention includes substrate layer, full oxygen buried layer, silicon film and device top layer；The substrate layer is arranged in bottom, mixes
Miscellany type is p-type, doped silicon material；It is full oxygen buried layer above substrate layer, full oxygen buried layer uses silica；Above full oxygen buried layer
For silicon film；The silicon film includes source region, silicon body, drift region, drain region, part oxygen buried layer, part P-type silicon buried layer and part
N-type silicon buried layer；Part oxygen buried layer uses earth silicon material, source region, silicon body, drift region, drain region, part P-type silicon buried layer and portion
It is silicon materials to divide N-type silicon buried layer all；Silicon body surrounds source region, and source region and silicon body are located at silicon film side, and source region is located at silicon film
Top；Drift region, drain region, part oxygen buried layer, part P-type silicon buried layer and part N-type silicon buried layer are located at the silicon film other side, and leak
Area is located at the top of silicon film；Region between drain region, part oxygen buried layer, part P-type silicon buried layer and part N-type silicon buried layer is drift
Area；Part oxygen buried layer and part N-type silicon buried layer are located above full oxygen buried layer, and part oxygen buried layer is more close than part N-type silicon buried layer
Silicon body is arranged；Interface of the part N-type silicon buried layer far from silicon body is aligned with the homonymy interface of drift region；Part P-type silicon buried layer is located at
Above the oxygen buried layer of part, part oxygen buried layer length is more than part P-type silicon buried layer length；Raceway groove is by the silicon between source region and drift region
Body provides；Part oxygen buried layer and part P-type silicon buried layer are aligned close to the interface of silicon body with the homonymy interface of drift region；Part N-type
Silicon buried layer doping concentration is more than drift doping concentration.The doping type in source region and drain region is N-type；Silicon body doping type is p-type；
Drift region doping type is N-type.The device top layer includes gate oxide, extension oxide layer, source electrode, gate electrode and electric leakage
Pole；Gate oxide is located above raceway groove, using silica；Extension oxide layer is located above drift region, using silica；Grid
Oxide layer is all covered by gate electrode；Source electrode is located above source region, and drain electrode is located above drain region.
The substrate and source electrode is all grounded.
The substrate layer grows 40 μm, and doping concentration is 4 × 1014cm-3；Full oxygen buried layer thickness is 2 μm；Silicon fiml layer thickness
It is 2 μm；Source region and the length in drain region are 5 μm, and doping concentration is 1 × 1020cm-3；Silicon body doping concentration is 1 × 1017cm-3；Drift
It is 28 μm close to the distance between interface of silicon body that area, which is moved, close to the interface of silicon body and drain region；A length of 2 μm of raceway groove；Gate oxidation thickness
40nm；Extension oxidation thickness 80nm；The length of silicon body is 7 μm；Part oxygen buried layer thickness is 0.6 μm, and length is 15 μm；Part P
Thickness, length and the concentration of type silicon buried layer are respectively 0.4 μm, 7 μm and 1 × 1015cm-3；The thickness of part N-type silicon buried layer, length
It it is respectively 0.2 μm, 16 μm and 1 × 10 with concentration17cm-3；Drift doping concentration is 9 × 1015cm-3。
The thickness in the source region and drain region is 0.2 μm, and gate oxide grows 2 μm, and extension oxide layer grows 29 μm.
The invention has the advantages that：
1, part oxygen buried layer reduces Introgression area area, P-type silicon buried layer meeting assisted depletion drift region, and N-type silicon
Capability exchange compromise is had between buried layer and drift region.This three results in drift region concentration and increases, and then electric current increases, and reduces
Conducting resistance (On-resistance, the R of deviceon)。
2, a variety of part buried layers can introduce more higher electric field spikes and improve cross so as to improve field distribution
To breakdown voltage.Meanwhile higher electric field can be introduced in full oxygen buried layer, then improve longitudinal breakdown voltage.Therefore, it carries
High the breakdown voltage of device (Breakdown Voltage, BV).
3, the present invention is optimized to the further performances of high pressure SOI LDMOS, and one is provided for high voltage integrated circuit design
A new selection.This has good facilitation for the development of High voltage power device and associated high voltage integrated circuit.
The present invention is identical in the length of source-drain area, channel region, drift region and substrate, material, doping type and doping concentration, silicon film
Thickness is identical, and oxygen buried layer thickness is identical, and under conditions of all insulation oxide material parameters are all consistent, oxygen is buried with double step types
Silicon LDMOS (Buried on layer LDMOS (Buried Oxide Double Step LDMOS), the insulating layer with N-type silicon buried layer
N-type Layer Silicon-on-Insulator LDMOS) and insulating layer with mixing portion P/N silicon buried layers on silicon
LDMOS is compared, and the performances such as breakdown voltage and conducting resistance of device are more superior.
Description of the drawings
For the ease of narration, by silicon ldmos transistor, double stepped oxygen buried layers on the insulating layer with N-type silicon buried layer
Silicon ldmos transistor and the present invention are with a variety of portions on ldmos transistor, the insulating layer with mixing portion P/N silicon buried layers
The ldmos transistor of silicon on the insulating layer of buried layer is divided to be abbreviated as respectively：BNLSOI, BODS SOI, Type-A SOI and
HMPBLSOI。
Fig. 1 is the structure chart of the present invention；
Fig. 2-1 is for the electric field strength of the embodiment of the present invention 1 and other three kinds of structures with lengthwise position variation by origin O
Curve graph；
Fig. 2-2 is the partial enlarged view at square dotted line frame in Fig. 2-1；
The curve that Fig. 3 changes by origin O with lengthwise position for the voltage of the embodiment of the present invention 1 and other three kinds of structures
Figure；
The song that Fig. 4-1 changes for the silicon fiml upper surface electric field of the embodiment of the present invention 1 and other three kinds of structures with lateral position
Line chart；
Fig. 4-2 is the partial enlarged view at square dotted line frame in Fig. 4-1；
The song that Fig. 5 changes for the silicon film upper surface potential of the embodiment of the present invention 1 and other three kinds of structures with lateral position
Line chart；
Fig. 6 is that the length of changing section oxygen buried layer and drift doping concentration are electric to device breakdown in the embodiment of the present invention 2
The influence schematic diagram of pressure；
Fig. 7 is that the thickness of changing section oxygen buried layer and drift doping concentration are electric to device breakdown in the embodiment of the present invention 3
The influence schematic diagram of pressure；
Fig. 8 is to change influence schematic diagram of the P-type silicon buried layer doping concentration to device electric breakdown strength in the embodiment of the present invention 4；
Fig. 9 be the embodiment of the present invention 5 in changing section P-type silicon buried layer length and drift doping concentration to device breakdown
The influence schematic diagram of voltage；
Figure 10 is that the thickness of changing section P-type silicon buried layer and drift doping concentration hit device in the embodiment of the present invention 6
Wear the influence schematic diagram of voltage；
The length and doping concentration of changing section P-type silicon buried layer are to device electric breakdown strength in Figure 11 embodiment of the present invention 7
Influence schematic diagram；
Figure 12 is that the thickness of changing section N-type silicon buried layer and drift doping concentration hit device in the embodiment of the present invention 8
Wear the influence schematic diagram of voltage；
Figure 13 is that the length of changing section N-type silicon buried layer and drift doping concentration hit device in the embodiment of the present invention 9
Wear the influence schematic diagram of voltage；
Figure 14 be the embodiment of the present invention 10 in changing section N-type silicon buried layer doping concentration and drift doping concentration to device
The influence schematic diagram of part breakdown voltage；
Figure 15 is the relational graph of the breakdown voltage and conducting resistance of the embodiment of the present invention 11 and other three kinds of structures.
Specific implementation mode
Below in conjunction with drawings and examples, the invention will be further described.
As shown in Figure 1, silicon ldmos transistor (HMPBL SOI) on a kind of insulating layer with a variety of part buried layers, including
Substrate layer 14, full oxygen buried layer 8, silicon film and device top layer；Substrate layer 14 is arranged in bottom, and doping type is p-type, doping concentration
It is 4 × 1014cm-3Silicon materials, substrate layer grow 40 μm；Substrate layer 14 above be full oxygen buried layer 8, full oxygen buried layer 8 use thickness for
2 μm of silica；Full oxygen buried layer 8 is silicon film above, and thickness is 2 μm；Silicon film include source region 1, silicon body 2, drift region 3,
Drain region 4, part oxygen buried layer 5, part P-type silicon buried layer 6 and part N-type silicon buried layer 7；Part oxygen buried layer 5 uses earth silicon material,
Source region 1, silicon body 2, drift region 3, drain region 4, part P-type silicon buried layer 6 and part N-type silicon buried layer 7 are all silicon materials；Silicon body 2 surrounds
Source region 1, source region 1 and silicon body 2 are located at silicon film side, and source region 1 is located at the top of silicon film；Oxygen, is partly buried at drain region 4 in drift region 3
Layer 5, part P-type silicon buried layer 6 and part N-type silicon buried layer 7 are located at the silicon film other side, and drain region 4 is located at the top of silicon film；Drain region
4, the region between part oxygen buried layer 5, part P-type silicon buried layer 6 and part N-type silicon buried layer 7 is drift region 3；5 He of part oxygen buried layer
Part N-type silicon buried layer 7 is located above full oxygen buried layer 8, and part oxygen buried layer 5 is arranged than part N-type silicon buried layer 7 close to silicon body 2；Portion
Point interface of the N-type silicon buried layer 7 far from silicon body 2 is aligned with the homonymy interface of drift region 3；Part P-type silicon buried layer 6 is located at part and buries oxygen
Above layer 5, oxygen buried layer 5 length in part is more than 6 length of part P-type silicon buried layer；Part oxygen buried layer 5 and part P-type silicon buried layer 6 are close
The interface of silicon body 2 is aligned with the homonymy interface of drift region 3；N-type silicon buried layer 7 doping concentration in part is more than drift doping concentration.
Raceway groove is provided by the silicon body 2 between source region and drift region, a length of 2 μm of raceway groove.Source region 1 and the length in drain region 4 are 5 μm of (this realities
It is 0.2 μm to apply thickness in example), doping type is N-type, and doping concentration is 1 × 1020cm-3；2 doping type of silicon body is p-type, is mixed
Miscellaneous a concentration of 1 × 1017cm-3；Drift region 3 is 28 close to the distance between interface of silicon body 2 close to the interface of silicon body 2 and drain region 4
μm, doping type is N-type.Device top layer includes gate oxide 9, extension oxide layer 10, source electrode 11, gate electrode 12 and drain electrode
13；Gate oxide 9 is located above raceway groove, using the silica of thick 40nm (2 μm of length in the present embodiment)；Extend oxide layer 10
Above drift region, using the silica of thick 80nm (29 μm of length in the present embodiment)；Gate oxide 9 is all covered by gate electrode 12
Lid；Source electrode 11 is located above source region 1, and drain electrode 13 is located above drain region 4.The present invention has the insulating layer of a variety of part buried layers
Ldmos transistor (HMPBLSOI) performance of upper silicon is obtained based on three-dimensional Sentaurus TCAD software analog studies,
And substrate 14 and source electrode 11 are all grounded in analog simulation research.
If length direction is lateral position X, thickness direction is lengthwise position Y, the outside longitudinal direction interface top point of silicon body 2
For origin O, each embodiment is specifically addressed below.
Embodiment 1：The length of the silicon body 2 of HMPBL SOI is 7 μm；Oxygen buried layer 5 thickness in part is 0.6 μm, and length is 15 μ
m；Thickness, length and the concentration of part P-type silicon buried layer 6 are respectively 0.4 μm, 7 μm and 1 × 1015cm-3；Part N-type silicon buried layer 7
Thickness, length and concentration are respectively 0.2 μm, 16 μm and 1 × 1017cm-3；Drift doping concentration is 9 × 1015cm-3；
The ldmos transistor (HMPBL SOI) of silicon on insulating layer with a variety of part buried layers, electric field strength is (by origin O
Rise) with lengthwise position variation curve graph as shown in Fig. 2-1 and 2-2, it is seen then that compare Type-A SOI, BODS SOI and BNL
SOI introduces higher electric field in full oxygen buried layer, to reach higher breakdown voltage, also, due to part oxygen buried layer 5
Introducing, reached electric field strength more higher than Type-A SOI.
As shown in figure 3, the full oxygen buried layer of HMPBL SOI assumes responsibility for the voltage V of 400VI, than Type-ASOI, BODS SOI
Distinguish more 50V, 150V and 200V with the voltage that the full oxygen buried layer of BNL SOI is undertaken, therefore, in four kinds of structures, HMPBL
The breakdown voltage of SOI is maximum；Silicon film assumes responsibility for voltage VS。
As shown in Fig. 4-1 and 4-2, upper surface (face for crossing origin O) electric field of HMPBL SOI will produce three " protrusions ",
These three " protrusions " have dragged down source, the electric field strength at drain electrode, reduce surface field (REducedSURface Field,
RESURF) effect is also stronger, to improve device electric breakdown strength.Three " protrusion " Producing reasons are as follows：(1) in part p-type
Two side areas doping type is or not silicon buried layer and longitudinal interface D1 (i.e. lateral position is longitudinal interface at 14 μm) of drift region
It is same to cause；(2) longitudinal interface D2 (i.e. lateral position is longitudinal interface at 22 μm) both sides of part oxygen buried layer 5 and drift region
Region dielectric constant difference causes；(3) (i.e. lateral position is 24 μm to longitudinal interface D3 of part N-type silicon buried district and drift region
Longitudinal interface at place) there are concentration differences to cause for two side areas doping.And the upper surface electric field of BNL SOI is without protrusion, BODS
Only there are one raised (longitudinal interface B) for the upper surface electric field of SOI, and only there are two protrusions for the upper surface electric field of Type-A SOI
(longitudinal interface C1 and C2).
As shown in figure 5, in silicon film upper surface, compared with other three kinds of structures, Potential Distributing has more preferable HMPBL SOI
The linearity, therefore, the RESURF effects of HMPBL SOI are also stronger, to reach higher breakdown voltage.
Embodiment 2：Lateral position of the changing section oxygen buried layer 5 far from 2 that interface of silicon body (is denoted as xPBOX, that is, keep
Part oxygen buried layer 5 is constant close to the lateral position at 2 that interface of silicon body, and the length of changing section oxygen buried layer 5) and drift region
Doping concentration, remaining parameter are identical as the parameter of embodiment 1；
As shown in fig. 6, working as xPBOXWhen constant, with the increase of drift doping concentration, breakdown voltage is all after first increasing
Reduce；With xPBOXIncrease, each xPBOXAfter corresponding breakdown voltage first increases with the peak value of drift doping concentration change curve
Reduce, best part oxygen buried layer length is 15 μm, i.e. xPBOX=22 μm.
Embodiment 3：The thickness of changing section oxygen buried layer (is denoted as tPBOX) and drift doping concentration, remaining parameter with
The parameter of embodiment 1 is identical；
As shown in fig. 7, working as tPBOXWhen constant, with the increase of drift doping concentration, breakdown voltage is all after first increasing
Reduce；With tPBOXIncrease, each xPBOXAfter corresponding breakdown voltage first increases with the peak value of drift doping concentration change curve
Reduce, the thickness of best part oxygen buried layer is 0.6 μm.
Embodiment 4：Drift doping concentration (is denoted as Ndr) it is 9 × 1015cm-3, the doping of changing section P-type silicon buried layer
Concentration, remaining parameter are identical as the parameter of embodiment 1；
As shown in figure 8, in figure, tPBPLFor the thickness of part P-type silicon buried layer, xBPFor part P-type silicon buried layer far from silicon body 2 that
The lateral position at a interface；When the doping concentration of part P-type silicon buried layer is less than 1 × 1015cm-3When, with the increasing of doping concentration
Add, breakdown voltage increases；When the doping concentration of part P-type silicon buried layer is more than 4 × 1015cm-3When, with the increase of doping concentration,
Breakdown voltage reduces；When the doping concentration of part P-type silicon buried layer is located at 1 × 1015cm-3With 4 × 1015cm-3Between when, with mixing
The increase of miscellaneous concentration, breakdown voltage remain unchanged.This is because the doping concentration when part P-type silicon buried layer is less than 1 × 1015cm-3
When, drift region cannot be completely depleted, and when the doping concentration of part P-type silicon buried layer is more than 4 × 1015cm-3When, part P-type silicon is buried
Layer cannot be completely depleted, when the doping concentration of part P-type silicon buried layer is located at 1 × 1015cm-3With 4 × 1015cm-3Between when,
RESURF conditions are met, so under constant drift doping concentration, breakdown voltage remains unchanged.
Embodiment 5：Lateral position of the changing section P-type silicon buried layer far from 2 that interface of silicon body (is denoted as xBP, that is, keep
Part P-type silicon buried layer is constant close to the lateral position at 2 that interface of silicon body, and the length of changing section P-type silicon buried layer) and drift
Area's doping concentration, remaining parameter are identical as the parameter of embodiment 1；
As shown in figure 9, NPBPLFor the doping concentration of part P-type silicon buried layer；Work as xBPWhen constant, with drift doping concentration
Increase, breakdown voltage is all first increases and then decreases；With xBPIncrease, each xBPCorresponding breakdown voltage is adulterated with drift region
The peak value first increases and then decreases of concentration curve, best part oxygen buried layer length is 7 μm, i.e. xBP=14 μm.
Embodiment 6：The thickness of changing section P-type silicon buried layer (is denoted as tPBPL) and drift doping concentration, remaining parameter
It is identical as the parameter of embodiment 1；
As shown in Figure 10, work as tPBPLWhen constant, with the increase of drift doping concentration, breakdown voltage is all after first increasing
Reduce；With tPBPLIncrease, each tPBPLAfter corresponding breakdown voltage first increases with the peak value of drift doping concentration change curve
Reduce, best part oxygen buried layer thickness is 0.4 μm.
Embodiment 7：Drift doping concentration (is denoted as Ndr) it is 9 × 1015cm-3, only change xBPWith part P-type silicon buried layer
Doping concentration (is denoted as NPBPL), remaining parameter is identical as the parameter of embodiment 1；
As shown in figure 11, work as NPBPLWhen constant, with xBPIncrease, breakdown voltage is all first increases and then decreases；With
NPBPLIncrease, each NPBPLCorresponding breakdown voltage is with xBPThe peak value first increases and then decreases of change curve；Also, work as NPBPLFor 5 ×
1015cm-3、1×1016cm-3When, with xBPChange, breakdown voltage can reach 400V.But work as NPBPLMore than 1 × 1016cm-3When, such as 3 × 1016cm-3, breakdown voltage reduces, this is because excessive NPBPLDestroy RESURF, xBPChange no longer shadow
Ring the variation of breakdown voltage.
Embodiment 8：The thickness and drift doping concentration of changing section N-type silicon buried layer, remaining parameter and embodiment 1
Parameter is identical；
Embodiment 9：The length and drift doping concentration of changing section N-type silicon buried layer, remaining parameter and embodiment 1
Parameter is identical；
Embodiment 10：The doping concentration and drift doping concentration of changing section N-type silicon buried layer, remaining parameter with implement
The parameter of example 1 is identical；
Embodiment 8,9 and 10 is respectively as shown in Figure 12,13 and 14, Tu12Zhong, LPBNLFor the length of part N-type silicon buried layer,
NPBNLThe doping concentration of part N-type silicon buried layer；In Figure 13, tPBNLFor the thickness of part N-type silicon buried layer；As it can be seen that with part N-type
The increase of the length, thickness and any parameter of doping concentration of silicon buried layer, breakdown voltage federation first increases and then decreases；But work as drift
When shifting area's concentration is excessive, breakdown voltage can decline to a great extent, and curve becomes in alignment.This is because excessive drift region is dense
Degree can destroy the condition of RESURF effects, and N-type silicon buried layer in part no longer has regulating power to breakdown voltage at this time.
Example 11：All parameters are identical as the parameter of embodiment 1, compare the breakdown voltage and conducting resistance of four kinds of structures
Relationship.
As shown in figure 15, it is seen then that the attainable maximum breakdown voltages of HMPBL SOI (430V), than Type-A SOI, BODS
SOI and BNL SOI are higher by 11%, 55.2% and 86% respectively, device quality factor (Figure-of-merit) highest.
Claims (4)
1. silicon ldmos transistor on a kind of insulating layer with a variety of part buried layers, including substrate layer, full oxygen buried layer, silicon film
With device top layer, it is characterised in that：The substrate layer is arranged in bottom, and doping type is p-type, doped silicon material；Substrate layer
It is full oxygen buried layer above, full oxygen buried layer uses silica；It is silicon film above full oxygen buried layer；The silicon film includes source
Area, silicon body, drift region, drain region, part oxygen buried layer, part P-type silicon buried layer and part N-type silicon buried layer；Part oxygen buried layer uses two
Silica material, source region, silicon body, drift region, drain region, part P-type silicon buried layer and part N-type silicon buried layer are all silicon materials；Silicon body
Source region is surrounded, source region and silicon body are located at silicon film side, and source region is located at the top of silicon film；Oxygen, is partly buried at drain region in drift region
Layer, part P-type silicon buried layer and part N-type silicon buried layer are located at the silicon film other side, and drain region is located at the top of silicon film；Drain region, portion
It is drift region to divide the region between oxygen buried layer, part P-type silicon buried layer and part N-type silicon buried layer；Part oxygen buried layer and part N-type silicon
Buried layer is located above full oxygen buried layer, and part oxygen buried layer is arranged than part N-type silicon buried layer close to silicon body；Part N-type silicon buried layer is remote
Interface from silicon body is aligned with the homonymy interface of drift region；Part P-type silicon buried layer is located above the oxygen buried layer of part, part oxygen buried layer
Length is more than part P-type silicon buried layer length；Raceway groove is provided by the silicon body between source region and drift region；Part oxygen buried layer and part P
Type silicon buried layer is aligned close to the interface of silicon body with the homonymy interface of drift region；Part N-type silicon buried layer doping concentration is more than drift region
Doping concentration；The doping type in source region and drain region is N-type；Silicon body doping type is p-type；Drift region doping type is N-type；It is described
Device top layer include gate oxide, extension oxide layer, source electrode, gate electrode and drain electrode；Gate oxide is located above raceway groove,
Using silica；Extension oxide layer is located above drift region, using silica；Gate oxide is all covered by gate electrode；
Source electrode is located above source region, and drain electrode is located above drain region.
2. silicon ldmos transistor on a kind of insulating layer with a variety of part buried layers according to claim 1, feature exist
In：The substrate and source electrode is all grounded.
3. silicon ldmos transistor on a kind of insulating layer with a variety of part buried layers according to claim 1 or 2, special
Sign is：The substrate layer grows 40 μm, and doping concentration is 4 × 1014cm-3；Full oxygen buried layer thickness is 2 μm；Silicon fiml layer thickness is
2μm；Source region and the length in drain region are 5 μm, and doping concentration is 1 × 1020cm-3；Silicon body doping concentration is 1 × 1017cm-3；Drift
Area is 28 μm close to the distance between interface of silicon body close to the interface of silicon body and drain region；A length of 2 μm of raceway groove；Gate oxidation thickness
40nm；Extension oxidation thickness 80nm；The length of silicon body is 7 μm；Part oxygen buried layer thickness is 0.6 μm, and length is 15 μm；Part P
Thickness, length and the concentration of type silicon buried layer are respectively 0.4 μm, 7 μm and 1 × 1015cm-3；The thickness of part N-type silicon buried layer, length
It it is respectively 0.2 μm, 16 μm and 1 × 10 with concentration17cm-3；Drift doping concentration is 9 × 1015cm-3。
4. silicon ldmos transistor on a kind of insulating layer with a variety of part buried layers according to claim 3, feature exist
In：The thickness in the source region and drain region is 0.2 μm, and gate oxide grows 2 μm, and extension oxide layer grows 29 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810410509.1A CN108598167B (en) | 2018-05-02 | 2018-05-02 | Silicon-on-insulator LDMOS transistor with multiple partial buried layers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810410509.1A CN108598167B (en) | 2018-05-02 | 2018-05-02 | Silicon-on-insulator LDMOS transistor with multiple partial buried layers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108598167A true CN108598167A (en) | 2018-09-28 |
| CN108598167B CN108598167B (en) | 2021-02-09 |
Family
ID=63620489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810410509.1A Active CN108598167B (en) | 2018-05-02 | 2018-05-02 | Silicon-on-insulator LDMOS transistor with multiple partial buried layers |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108598167B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112713193A (en) * | 2020-12-30 | 2021-04-27 | 杭州电子科技大学温州研究院有限公司 | Trench LDMOS transistor with convex extended buried oxide region |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101488524A (en) * | 2009-02-27 | 2009-07-22 | 东南大学 | High voltage N type SOI MOS transistor |
| CN101599507A (en) * | 2009-06-10 | 2009-12-09 | 苏州博创集成电路设计有限公司 | The lateral double-diffused metal-oxide-semiconductor transistor of N type silicon-on-insulator |
| CN105097936A (en) * | 2015-07-06 | 2015-11-25 | 深港产学研基地 | Silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (LDMOS) power device |
| US20170250259A1 (en) * | 2016-02-25 | 2017-08-31 | Renesas Electronics Corporation | Semiconductor device and manufacturing method of semiconductor device |
-
2018
- 2018-05-02 CN CN201810410509.1A patent/CN108598167B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101488524A (en) * | 2009-02-27 | 2009-07-22 | 东南大学 | High voltage N type SOI MOS transistor |
| CN101599507A (en) * | 2009-06-10 | 2009-12-09 | 苏州博创集成电路设计有限公司 | The lateral double-diffused metal-oxide-semiconductor transistor of N type silicon-on-insulator |
| CN105097936A (en) * | 2015-07-06 | 2015-11-25 | 深港产学研基地 | Silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (LDMOS) power device |
| US20170250259A1 (en) * | 2016-02-25 | 2017-08-31 | Renesas Electronics Corporation | Semiconductor device and manufacturing method of semiconductor device |
Non-Patent Citations (3)
| Title |
|---|
| MEYSAM ZAREIEE ET AL: "A novel high breakdown voltage LDMOS by protruded silicon dioxide at the drift region", 《JOURNAL OF COMPUTATIONAL ELECTRONICS》 * |
| QIAN WANG ET AL: "A novel partial SOI EDMOS (>800 V) with a buried N-type layer on the double step buried oxide", 《SUPERLATTICES AND MICROSTRUCTURES》 * |
| 刘华振等: "部分ＰＮ埋层的高压ＳＯＩ ＬＤＭＯＳ研究", 《杭州电子科技大学学报》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112713193A (en) * | 2020-12-30 | 2021-04-27 | 杭州电子科技大学温州研究院有限公司 | Trench LDMOS transistor with convex extended buried oxide region |
| CN112713193B (en) * | 2020-12-30 | 2023-05-02 | 杭州电子科技大学温州研究院有限公司 | Trench LDMOS transistor with convex type extended buried oxide region |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108598167B (en) | 2021-02-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20020053695A1 (en) | Split buried layer for high voltage LDMOS transistor | |
| CN101969050B (en) | Silicon integrated high-current N type combined semiconductor device on insulator | |
| CN1520616A (en) | Power semiconductor devices having laterally extending base shielding regions that inhibit base reach through and methodds of forming same | |
| CN101969074A (en) | High voltage lateral double diffused MOSFET element | |
| CN110137248A (en) | A kind of LDMOS device of resistant to total dose effect | |
| CN103915506A (en) | Double-gate LDMOS device with longitudinal NPN structure | |
| CN114050187A (en) | Integrated trench gate power semiconductor transistor with low characteristic on-resistance | |
| CN107863379A (en) | A kind of N-type LDMOS structure with field plate supplementary doping area | |
| Wu et al. | Investigation of the stepped split protection gate L-Trench SOI LDMOS with ultra-low specific on-resistance by simulation | |
| CN112002755A (en) | Novel LDMOS device structure and preparation method and performance thereof | |
| CN208028069U (en) | Novel two-sided step buried oxide SOI LDMOS with buried structure | |
| CN101980364B (en) | Thin-layer SOI composite power device | |
| CN103325835A (en) | SOI power LDMOS device provided with junction type field plate | |
| CN105789270A (en) | VDMOS device with variable dielectric side | |
| CN108598167A (en) | Silicon ldmos transistor on a kind of insulating layer with a variety of part buried layers | |
| CN109698196B (en) | Power semiconductor device | |
| CN117059667A (en) | Double-channel SOI-LDMOS transistor | |
| CN101976670A (en) | Silicon-on-insulator integrated great-current P-type combined semiconductor device | |
| Yang et al. | An ultra-low specific on-resistance double-gate trench SOI LDMOS with P/N pillars | |
| CN207705201U (en) | T-RESURF LDMOS with novel electrode structure | |
| CN112466955B (en) | Thin-layer SOI-LDMOS device with in-vivo conductive channel | |
| CN102738229B (en) | Structure of power transistor and method for manufacturing power transistor | |
| CN107359192A (en) | A kind of lateral high-voltage device | |
| CN105932062B (en) | It is a kind of with the SOI LDMOS device for burying oxygen field plate | |
| CN110504321A (en) | Silicon ldmos transistor on a kind of insulating layer with PN column |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |