CN108598096A - Tft array substrate and preparation method thereof - Google Patents
Tft array substrate and preparation method thereof Download PDFInfo
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- CN108598096A CN108598096A CN201810622177.3A CN201810622177A CN108598096A CN 108598096 A CN108598096 A CN 108598096A CN 201810622177 A CN201810622177 A CN 201810622177A CN 108598096 A CN108598096 A CN 108598096A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Abstract
A kind of tft array substrate of present invention offer and preparation method thereof.The source electrode of the tft array substrate, drain electrode, first grid and second grid are both formed on insulating layer, it is generally aligned in the same plane, therefore the light shield with along with may be used while making source electrode, drain electrode, first grid and second grid, to save production cost and production time, and an equivalent capacity can be formed between first grid and source electrode and between second grid and drain electrode, by adjusting the distance between first grid and source electrode and the distance between second grid and drain electrode, effectively the threshold voltage to TFT devices and subthreshold swing it can carry out regulation and control appropriate, improve TFT device electric properties.
Description
Technical field
The present invention relates to display technology fields more particularly to a kind of tft array substrate and preparation method thereof.
Background technology
With the development of display technology, the planes such as liquid crystal display (Liquid Crystal Display, LCD) display dress
It sets because having many advantages, such as that high image quality, power saving, fuselage is thin and has a wide range of application, and is widely used in mobile phone, TV, a number
The various consumer electrical products such as word assistant, digital camera, laptop, desktop computer, become the master in display device
Stream.
Liquid crystal display device on existing market is largely backlight liquid crystal display comprising liquid crystal display panel and
Backlight module (backlight module).The operation principle of liquid crystal display panel is put in the parallel glass substrate of two panels
Liquid crystal molecule is set, there are many tiny electric wires vertically and horizontally for two panels glass substrate centre, and liquid crystal is controlled whether by being powered
The light of backlight module is transmitted generation picture by molecular changes direction.
Compared to traditional TFT materials screen, active matrix organic light-emitting diode (Active Matrix Organic
Light Emitting Diode, AMOLED) AMOLED screen is because of its fast response time, self-luminous, display effect it is excellent and
The advantages of more low power consumption and the favor for increasingly obtaining user.And active matrix liquid crystal shows (Active Matrix
Liquid Crystal Display, AMLCD) because it stablizes with antivibration, anti-electromagnetic interference, image quality, adaptive temperature range is wide
And it is widely used in military affairs, telecommunications, electric power, oil, chemical industry, metallurgy, machinery, numerical control, medical treatment, traffic, instrument and meter, aerospace
And all kinds of field control monitoring etc..However, traditional single gated device structure is because of its lower mobility, to
Application in terms of the large area resolution ratio such as AMOLED screen and AMLCD is restricted.
In order to meet the high-resolution requirement of large area, generally use double gate device structure is to improve mobility, double grid
Pole device architecture is for single gated device structure, since its top-gated and bottom gate be not in a plane, when manufacturing
One of light shield can be used, production cost is high, and the production time is long more.
Invention content
The purpose of the present invention is to provide a kind of tft array substrate, the light shield with along with can be used to make source electrode, leakage simultaneously
Pole, first grid and second grid improve TFT device electric properties to save production cost and production time.
Another object of the present invention is to provide a kind of production methods of tft array substrate, can use the light shield with along with
Source electrode, drain electrode, first grid and second grid are made simultaneously, to save production cost and production time, improves TFT device electricity
Performance.
To achieve the above object, present invention firstly provides a kind of tft array substrate, including underlay substrate, it is set to the lining
Conductive layer on substrate, the insulating layer on the conductive layer, the active layer on the insulating layer, be set to it is described absolutely
In edge layer and respectively with the source electrode and drain electrode of two end in contact of the active layer and on the insulating layer and it is located at source
The first grid and second grid of pole and drain electrode periphery；
The first grid and second grid respectively by the first via through the insulating layer and the second via with lead
Electric layer contacts；
The source electrode, drain electrode, first grid and second grid use the light shield with along with to make simultaneously.
The tft array substrate further includes the covering active layer, insulating layer, source electrode, drain electrode, first grid and second gate
The protective layer of pole, and the pixel electrode on the protective layer；The pixel electrode passes through through the of the protective layer
Three vias and drain contact.
The material of the conductive layer is one or more of molybdenum, copper and aluminium；The thickness of the conductive layer isThe material of the insulating layer is the combination of one or both of silica and silicon nitride；The insulating layer
Thickness is
The material of the active layer is IGZO；The thickness of the active layer is less than
The source electrode, drain electrode, first grid and second grid material be one or more in aluminium, copper, molybdenum, titanium；
The source electrode, drain electrode, first grid and second grid thickness be
The material of the protective layer is the combination of one or both of silica and silicon nitride；The thickness of the protective layer
ForThe material of the pixel electrode is ITO.
The active layer includes channel region and is located at the source contact area and drain contact region of channel region both sides；Institute
Source electrode is stated to contact with source contact area；The drain electrode is contacted with drain contact region.
The distance between the first grid and source electrode are less than the width of the channel region；The second grid and drain electrode
Between distance be less than the channel region width.
The width of the channel region is 3-5um.
The present invention provides a kind of production method of tft array substrate, includes the following steps：
Step S1, one underlay substrate is provided, conduction is sequentially formed on the underlay substrate using physical vaporous deposition
Layer and insulating layer；
Step S2, it is deposited on the insulating layer using physical vaporous deposition and forms oxide semiconductor layer, pass through Huang
Light, etch process to the oxide semiconductor layer carry out patterned process, obtain be located at the insulating layer on active layer and
Through the insulating layer and it is located at the first via and the second via of the active layer both sides；
Step S3, a metal layer is deposited on the insulating layer and active layer, is passed through with along with using yellow light, etching processing procedure
Light shield to the metal layer carry out patterned process, formed be located at the insulating layer on and respectively with two end in contact of the active layer
Source electrode and drain electrode, and on the insulating layer and be located at the first grid and second gate of source electrode and drain electrode periphery
Pole；The first grid and second grid pass through the first via and the second via and conductive layer contact respectively；
Step S4, it is formed using chemical vapour deposition technique and covers the active layer, insulating layer, source electrode, drain electrode, first grid
And the protective layer of second grid；
Step S5, using lithographic process, borehole, formation run through the protective layer and expose drain electrode on the protective layer
Third via；Transparency conducting layer is deposited on the protective layer, patterned process is carried out to the transparency conducting layer, forms picture
Plain electrode, and the pixel electrode is made annealing treatment；The pixel electrode is in contact via third via with the drain electrode.
The material of the conductive layer is one or more of molybdenum, copper and aluminium；The thickness of the conductive layer isThe material of the insulating layer is the combination of one or both of silica and silicon nitride；The insulating layer
Thickness is
The material of the active layer is IGZO；The thickness of the active layer is less than
The source electrode, drain electrode, first grid and second grid material be one or more in aluminium, copper, molybdenum, titanium；
The source electrode, drain electrode, first grid and second grid thickness be
The material of the protective layer is the combination of one or both of silica and silicon nitride；The thickness of the protective layer
ForThe material of the pixel electrode is ITO；
The temperature of the annealing is 200-450 DEG C.
The active layer includes channel region and is located at the source contact area and drain contact region of channel region both sides；Institute
Source electrode is stated to contact with source contact area；The drain electrode is contacted with drain contact region；
The distance between the first grid and source electrode are less than the width of the channel region；The second grid and drain electrode
Between distance be less than the channel region width；The width of the channel region is 3-5um.
Beneficial effects of the present invention：The source electrode of tft array substrate of the present invention, drain electrode, first grid and second grid are equal
It is formed on insulating layer, that is, is generally aligned in the same plane, therefore the light shield with along with may be used while making source electrode, drain electrode, the first grid
Pole and second grid, to save production cost and production time, and between first grid and source electrode and second grid and leakage
An equivalent capacity can be formed between pole, by adjusting the distance between first grid and source electrode and second grid and drain electrode
The distance between, effectively the threshold voltage to TFT devices and subthreshold swing regulation and control appropriate can be carried out, improve TFT devices
Part electric property.The present invention tft array substrate production method, can use with along with light shield and meanwhile make source electrode, drain electrode,
First grid and second grid, to save production cost and production time, and between first grid and source electrode and second gate
An equivalent capacity can be formed between pole and drain electrode, by adjusting the distance between first grid and source electrode and second grid
The distance between drain electrode effectively the threshold voltage to TFT devices and subthreshold swing can carry out regulation and control appropriate, improve
TFT device electric properties.
Description of the drawings
For further understanding of the features and technical contents of the present invention, it please refers to below in connection with the detailed of the present invention
Illustrate and attached drawing, however, the drawings only provide reference and explanation, is not intended to limit the present invention.
In attached drawing,
Fig. 1 is the structural schematic diagram of the tft array substrate of the present invention；
Fig. 2 is the flow chart of the production method of the tft array substrate of the present invention；
Fig. 3 is the schematic diagram of the production method step S1 of the tft array substrate of the present invention；
Fig. 4 is the schematic diagram of the production method step S2 of the tft array substrate of the present invention；
Fig. 5 is the schematic diagram of the production method step S3 of the tft array substrate of the present invention；
Fig. 6 is the schematic diagram of the production method step S4 of the tft array substrate of the present invention；
Fig. 7 is the schematic diagram of the production method step S5 of the tft array substrate of the present invention.
Specific implementation mode
Further to illustrate the technological means and its effect of the invention taken, below in conjunction with the preferred implementation of the present invention
Example and its attached drawing are described in detail.
Referring to Fig. 1, the present invention provides a kind of tft array substrate, including underlay substrate 10, it is set to the underlay substrate 10
On conductive layer 20, the insulating layer 30 on the conductive layer 20, the active layer 40 on the insulating layer 30, be set to institute
It states on insulating layer 30 and respectively with the source electrode 51 of 40 liang of end in contact of the active layer and drain electrode 52 and set on the insulating layer 30
Go up and be located at the first grid 53 and second grid 54 of 52 periphery of source electrode 51 and drain electrode；
The first grid 53 and second grid 54 pass through the first via 31 and second through the insulating layer 30 respectively
Via 32 is contacted with conductive layer 20；
The source electrode 51, drain electrode 52, first grid 53 and second grid 54 use the light shield with along with to make simultaneously.
It should be noted that the source electrode 51 of the present invention, drain electrode 52, first grid 53 and second grid 54 are both formed in insulation
It on layer 30, that is, is generally aligned in the same plane, therefore the light shield with along with may be used while making source electrode 51, drain electrode 52, first grid 53
And second grid 54, to save production cost and production time, and between first grid 53 and source electrode 51 and second grid
An equivalent capacity can be formed between 54 and drain electrode 52, by adjusting the distance between first grid 53 and source electrode 51 and the
The distance between two grids 54 and drain electrode 52 can effectively the threshold voltage to TFT devices and subthreshold swing carry out suitably
Regulation and control, improve TFT device electric properties.
Specifically, the tft array substrate further include the covering active layer 40, insulating layer 30, source electrode 51, drain electrode 52,
The protective layer 60 of first grid 53 and second grid 54, and the pixel electrode 70 on the protective layer 60；The pixel
Electrode 70 is contacted by the third via 61 through the protective layer 60 with drain electrode 52.
Specifically, the material of the conductive layer 20 is one or more of molybdenum, copper and aluminium, i.e., conductive layer 20 can be
Individual one layer of metal film layer, or the composite metal film layer of various metals film layer combination；The conductive layer 20
Thickness beThe material of the insulating layer 30 is the combination of one or both of silica and silicon nitride, i.e.,
Insulating layer 30 can be individual silicon oxide layer or silicon nitride layer, or silicon oxide layer and silicon nitride layer are formed compound
Layer；The thickness of the insulating layer 30 is
Specifically, the material of the active layer 40 is indium gallium zinc (IGZO)；The thickness of the active layer 40 is less than
Specifically, the source electrode 51, drain electrode 52, first grid 53 and second grid 54 material be aluminium, copper, molybdenum, titanium
In it is one or more；The source electrode 51, drain electrode 52, first grid 53 and second grid 54 thickness be
Specifically, the material of the protective layer 60 is the combination of one or both of silica and silicon nitride, that is, protect
Layer 60 can be individual silicon oxide layer or silicon nitride layer, or the composite layer that silicon oxide layer and silicon nitride layer are formed；Institute
The thickness for stating protective layer 60 isThe material of the pixel electrode 70 is tin indium oxide (ITO).
Specifically, the active layer 40 includes channel region 41 and the source contact area 42 for being located at 41 both sides of channel region
With drain contact region 43；The source electrode 51 is contacted with source contact area 42；The drain electrode 52 is contacted with drain contact region 43.
Preferably, the distance between the first grid 53 and source electrode 51 are less than the width of the channel region 41；Described
The distance between two grids 54 and drain electrode 52 are less than the width of the channel region 41, are conducive to improve TFT device electric properties.
Preferably, the width of the channel region 41 is 3-5um.
Referring to Fig. 2, it is based on above-mentioned tft array substrate, the present invention also provides a kind of production method of tft array substrate,
Include the following steps：
Step S1, referring to Fig. 3, a underlay substrate 10 is provided, using physical vaporous deposition in the underlay substrate 10
On sequentially form conductive layer 20 and insulating layer 30；
Step S2, it is partly led referring to Fig. 4, being deposited on the insulating layer 30 using physical vaporous deposition and forming oxide
Body layer carries out patterned process to the oxide semiconductor layer by yellow light, etch process, obtains being located at the insulating layer 30
On active layer 40 and through the insulating layer 30 and be located at the first via 31 and the second mistake of 40 both sides of the active layer
Hole 32；
Step S3, referring to Fig. 5, depositing a metal layer on the insulating layer 30 and active layer 40, yellow light, etching are utilized
Processing procedure by with along with light shield to the metal layer carry out patterned process, formed be located at the insulating layer 30 on and respectively with institute
Source electrode 51 and the drain electrode 52 of 40 liang of end in contact of active layer are stated, and on the insulating layer 30 and is located at source electrode 51 and leakage
The first grid 53 and second grid 54 of 52 periphery of pole；The first grid 53 and second grid 54 pass through the first via 31 respectively
It is contacted with conductive layer 20 with the second via 32；
Step S4, the active layer 40, insulating layer 30, source electrode are covered referring to Fig. 6, being formed using chemical vapour deposition technique
51, drain electrode 52, the protective layer 60 of first grid 53 and second grid 54；
Step S5, referring to Fig. 7, borehole, formation run through the protective layer on the protective layer 60 using lithographic process
60 and expose drain electrode 52 third via 61；Transparency conducting layer is deposited on the protective layer 60, to the transparency conducting layer
Patterned process is carried out, forms pixel electrode 70, and make annealing treatment to the pixel electrode 70；The pixel electrode 70 passes through
It is in contact with the drain electrode 52 by third via 61.
It should be noted that the present invention is by using the light shield with along with while making source electrode 51, drain electrode 52, first grid 53
And second grid 54, so that source electrode 51, drain electrode 52, first grid 53 and second grid 54 is both formed on insulating layer 30, that is, is located at
Same plane, to save production cost and production time, and between first grid 53 and source electrode 51 and second grid 54 with
An equivalent capacity can be formed between drain electrode 52, by adjusting the distance between first grid 53 and source electrode 51 and second gate
The distance between pole 54 and drain electrode 52 effectively the threshold voltage to TFT devices and subthreshold swing can carry out tune appropriate
Control improves TFT device electric properties.
Specifically, the tft array substrate further include the covering active layer 40, insulating layer 30, source electrode 51, drain electrode 52,
The protective layer 60 of first grid 53 and second grid 54, and the pixel electrode 70 on the protective layer 60；The pixel
Electrode 70 is contacted by the third via 61 through the protective layer 60 with drain electrode 52.
Specifically, the temperature of the annealing is 200-450 DEG C.
Specifically, the material of the conductive layer 20 is one or more of molybdenum, copper and aluminium, i.e., conductive layer 20 can be
Individual one layer of metal film layer, or the composite metal film layer of various metals film layer combination；The conductive layer 20
Thickness beThe material of the insulating layer 30 is the combination of one or both of silica and silicon nitride, i.e.,
Insulating layer 30 can be individual silicon oxide layer or silicon nitride layer, or silicon oxide layer and silicon nitride layer are formed compound
Layer；The thickness of the insulating layer 30 is
Specifically, the material of the active layer 40 is indium gallium zinc；The thickness of the active layer 40 is less than
Specifically, the source electrode 51, drain electrode 52, first grid 53 and second grid 54 material be aluminium, copper, molybdenum, titanium
In it is one or more；The source electrode 51, drain electrode 52, first grid 53 and second grid 54 thickness be
Specifically, the material of the protective layer 60 is the combination of one or both of silica and silicon nitride, that is, protect
Layer 60 can be individual silicon oxide layer or silicon nitride layer, or the composite layer that silicon oxide layer and silicon nitride layer are formed；Institute
The thickness for stating protective layer 60 isThe material of the pixel electrode 70 is tin indium oxide.
Specifically, the active layer 40 includes channel region 41 and the source contact area 42 for being located at 41 both sides of channel region
With drain contact region 43；The source electrode 51 is contacted with source contact area 42；The drain electrode 52 is contacted with drain contact region 43.
Preferably, the distance between the first grid 53 and source electrode 51 are less than the width of the channel region 41；Described
The distance between two grids 54 and drain electrode 52 are less than the width of the channel region 41, are conducive to improve TFT device electric properties.
In conclusion source electrode, drain electrode, first grid and the second grid of the tft array substrate of the present invention are both formed in absolutely
It in edge layer, that is, is generally aligned in the same plane, therefore the light shield with along with may be used while making source electrode, drain electrode, first grid and second
Grid, to save production cost and production time, and between first grid and source electrode and between second grid and drain electrode
An equivalent capacity can be formed, by adjust between the distance between first grid and source electrode and second grid and drain electrode away from
From effectively the threshold voltage to TFT devices and subthreshold swing capable of carrying out regulation and control appropriate, improve TFT device electrical property
Energy.The production method of the tft array substrate of the present invention can use the light shield with along with to make source electrode, drain electrode, first grid simultaneously
And second grid, to save production cost and production time, and between first grid and source electrode and second grid and drain electrode
Between can form an equivalent capacity, pass through and adjust the distance between first grid and source electrode and second grid and drain electrode
Between distance, effectively the threshold voltage to TFT devices and subthreshold swing can carry out regulation and control appropriate, improve TFT devices
Electric property.
The above for those of ordinary skill in the art can according to the technique and scheme of the present invention and technology
Other various corresponding change and deformations are made in design, and all these change and distortions should all belong to the appended right of the present invention
It is required that protection domain.
Claims (10)
1. a kind of tft array substrate, which is characterized in that including underlay substrate (10), be set to leading on the underlay substrate (10)
Electric layer (20), the active layer (40) being set on the insulating layer (30), is set the insulating layer (30) being set on the conductive layer (20)
In on the insulating layer (30) and respectively with the source electrode (51) of (40) two end in contact of the active layer and drain electrode (52) and be set to
On the insulating layer (30) and be located at source electrode (51) and drain (52) periphery first grid (53) and second grid (54)；
The first grid (53) and second grid (54) respectively by run through the insulating layer (30) the first via (31) and
Second via (32) is contacted with conductive layer (20)；
The source electrode (51), drain electrode (52), first grid (53) and second grid (54) use the light shield with along with to make simultaneously.
2. tft array substrate as described in claim 1, which is characterized in that further include the covering active layer (40), insulating layer
(30), the protective layer (60) of source electrode (51), drain electrode (52), first grid (53) and second grid (54), and it is set to the guarantor
Pixel electrode (70) on sheath (60)；The pixel electrode (70) is by running through the third via (61) of the protective layer (60)
It is contacted with drain electrode (52).
3. tft array substrate as described in claim 1, which is characterized in that the material of the conductive layer (20) is molybdenum, copper and aluminium
One or more of；The thickness of the conductive layer (20) isThe material of the insulating layer (30) is oxidation
The combination of one or both of silicon and silicon nitride；The thickness of the insulating layer (30) is
The material of the active layer (40) is IGZO；The thickness of the active layer (40) is less than
The source electrode (51), drain electrode (52), first grid (53) and second grid (54) material be in aluminium, copper, molybdenum, titanium
It is one or more；The source electrode (51), drain electrode (52), first grid (53) and second grid (54) thickness be
4. tft array substrate as claimed in claim 2, which is characterized in that the material of the protective layer (60) be silica and
The combination of one or both of silicon nitride；The thickness of the protective layer (60) isThe pixel electrode
(70) material is ITO.
5. tft array substrate as described in claim 1, which is characterized in that the active layer (40) include channel region (41) with
And it is located at the source contact area (42) and drain contact region (43) of channel region (41) both sides；The source electrode (51) connects with source electrode
Touch area (42) contact；The drain electrode (52) contacts with drain contact region (43).
6. tft array substrate as claimed in claim 5, which is characterized in that between the first grid (53) and source electrode (51)
Distance be less than the channel region (41) width；The distance between the second grid (54) and drain electrode (52) are less than the ditch
The width in road area (41).
7. tft array substrate as claimed in claim 5, which is characterized in that the width of the channel region (41) is 3-5um.
8. a kind of production method of tft array substrate, which is characterized in that include the following steps：
One underlay substrate (10) step S1, is provided, is sequentially formed on the underlay substrate (10) using physical vaporous deposition
Conductive layer (20) and insulating layer (30)；
Step S2, it is deposited on the insulating layer (30) using physical vaporous deposition and forms oxide semiconductor layer, pass through Huang
Light, etch process carry out patterned process to the oxide semiconductor layer, obtain being located at active on the insulating layer (30)
Layer (40) and the first via (31) and the second mistake for running through the insulating layer (30) and being located at the active layer (40) both sides
Hole (32)；
Step S3, a metal layer is deposited on the insulating layer (30) and active layer (40), is passed through using yellow light, etching processing procedure same
One of light shield to the metal layer carry out patterned process, formed be located at the insulating layer (30) on and respectively with the active layer
The source electrodes (51) of (40) two end in contact and drain electrode (52), and on the insulating layer (30) and be located at source electrode (51) and
The first grid (53) and second grid (54) of drain electrode (52) periphery；The first grid (53) and second grid (54) lead to respectively
It crosses the first via (31) and the second via (32) is contacted with conductive layer (20)；
Step S4, it is formed using chemical vapour deposition technique and covers the active layer (40), insulating layer (30), source electrode (51), drain electrode
(52), the protective layer (60) of first grid (53) and second grid (54)；
Step S5, using lithographic process, borehole, formation run through the protective layer (60) and expose on the protective layer (60)
The third via (61) of drain electrode (52)；Transparency conducting layer is deposited on the protective layer (60), the transparency conducting layer is carried out
Patterned process forms pixel electrode (70), and is made annealing treatment to the pixel electrode (70)；The pixel electrode (70)
It is in contact with the drain electrode (52) via third via (61).
9. the production method of tft array substrate as claimed in claim 8, which is characterized in that the material of the conductive layer (20)
For one or more of molybdenum, copper and aluminium；The thickness of the conductive layer (20) isThe insulating layer (30)
Material be one or both of silica and silicon nitride combination；The thickness of the insulating layer (30) is
The material of the active layer (40) is IGZO；The thickness of the active layer (40) is less than
The source electrode (51), drain electrode (52), first grid (53) and second grid (54) material be in aluminium, copper, molybdenum, titanium
It is one or more；The source electrode (51), drain electrode (52), first grid (53) and second grid (54) thickness be
The material of the protective layer (60) is the combination of one or both of silica and silicon nitride；The protective layer (60)
Thickness isThe material of the pixel electrode (70) is ITO；
The temperature of the annealing is 200-450 DEG C.
10. the production method of tft array substrate as claimed in claim 8, which is characterized in that the active layer (40) includes ditch
Road area (41) and source contact area (42) and drain contact region (43) for being located at channel region (41) both sides；The source electrode
(51) it is contacted with source contact area (42)；The drain electrode (52) contacts with drain contact region (43)；
The distance between the first grid (53) and source electrode (51) are less than the width of the channel region (41)；The second grid
(54) it is less than width of the channel region (41) with drain electrode the distance between (52)；The width of the channel region (41) is 3-5um.
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