CN108566349B - High-speed low-jitter analog equalizer - Google Patents
High-speed low-jitter analog equalizer Download PDFInfo
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- CN108566349B CN108566349B CN201810115193.3A CN201810115193A CN108566349B CN 108566349 B CN108566349 B CN 108566349B CN 201810115193 A CN201810115193 A CN 201810115193A CN 108566349 B CN108566349 B CN 108566349B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03878—Line equalisers; line build-out devices
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
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Abstract
The invention discloses a high-speed low-jitter analog equalizer, which consists of 2 load networks, 2 equalizing circuits, a jitter removing circuit and a feedback circuit. The high-frequency equalization circuit and the low-frequency equalization circuit are in a serial connection structure, and two zero points and four poles are generated, so that the difference between the high-frequency gain and the low-frequency gain is increased, and a good equalization effect can be formed on a channel with larger attenuation. The debounce circuit and the low-frequency equalization circuit are in a parallel connection structure, and the output signal of the high-frequency equalization circuit compensates the signal passing through the low-frequency equalization circuit through the debounce circuit, so that zero-crossing jitter of the output signal of the low-frequency equalization circuit is reduced. The feedback circuit takes the output of the low-frequency equalization circuit as input, and the output compensates the output of the high-frequency equalization circuit, so that zero jitter of the differential signal is reduced. The invention has the characteristics of high equalization rate, remarkable compensation to the strong attenuation channel and small jitter of the output signal.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a high-speed low-jitter analog equalizer.
Background
Because of the ever-higher requirements on transmission data rate, the traditional transmission line, coaxial cable and other media have dielectric loss and other non-ideal characteristics, which can seriously attenuate high-frequency components in signals, further generate intersymbol interference, cause waveform distortion, seriously affect the integrity of transmission signals, cause error judgment of a later-stage circuit, lead to the rising of the error rate of a system and limit the transmission distance and the transmission rate of the signals.
In order to reduce the bit error rate of the signal when deciding, an equalizer having a compensation function for the high-frequency signal is generally added in the high-speed serial interface circuit. However, the conventional analog equalizer compensates for high-speed signals in different transmission channels by adjusting the gain of low-frequency components or the gain of high-frequency components in the signals, and this single adjustment manner easily causes jitter in the signal equalization process, which cannot achieve a good equalization effect.
Disclosure of Invention
The invention aims to solve the problems that the existing equalizer has low equalization efficiency on a strong attenuation channel, the equalized data rate is low and zero-crossing jitter of an output equalization signal is obvious, and provides a high-speed low-jitter analog equalizer.
In order to solve the problems, the invention is realized by the following technical scheme:
a high-speed low-jitter analog equalizer is composed of 2 load networks, 2 equalizing circuits, 1 jitter removing circuit and 1 feedback circuit. The structures of the 2 load networks, namely the high-frequency load network and the low-frequency load network are the same, and the structures of the 2 equalizing circuits, namely the high-frequency equalizing circuit and the low-frequency equalizing circuit, are the same. One input end of the high-frequency load network is connected with the output end von of the high-frequency balancing circuit. The other input end of the high-frequency load network is connected with the output end voph of the high-frequency balancing circuit. One input end of the low-frequency load network is connected with the output end von of the low-frequency equalizing circuit. The other input end of the low-frequency load network is connected with the output end vopl of the low-frequency balancing circuit. The input terminal vinh of the high-frequency equalization circuit is connected to the equalization input signal vin, and the input terminal viph of the high-frequency equalization circuit is connected to the equalization input signal vip. The output end von of the low-frequency equalization circuit is connected with the equalization output signal von, and the output end vopl of the low-frequency equalization circuit is connected with the equalization output signal vop. The output end von of the high-frequency equalizing circuit is connected with the input end vinl of the low-frequency equalizing circuit, and the output end voph of the high-frequency equalizing circuit is connected with the input end vipl of the low-frequency equalizing circuit. Input terminal vin of debounce circuit aux The output end von of the high-frequency equalization circuit is connected with the input end vip of the debounce circuit aux The output terminal voph of the high-frequency equalization circuit is connected. Output terminal von of debounce circuit aux The output end von of the low-frequency equalization circuit and the output end vop of the debounce circuit are connected aux The output terminal vopl of the low-frequency equalization circuit is connected. Input terminal vin of feedback circuit fb The input end vip of the feedback circuit is connected with the output end von of the low-frequency equalization circuit fb The output terminal vopl of the low-frequency equalization circuit is connected. Output terminal von of feedback circuit fb Low frequency connectionInput terminal vipl of the balance circuit and output terminal vop of the feedback circuit fb The input terminal vinl of the low-frequency equalization circuit is connected.
In the scheme, the high-frequency equalization circuit comprises MOS tubes M1-M5, a feedback resistor R5 and a feedback capacitor C5. The grid electrode of the MOS tube M1 forms an input end vinh of the high-frequency equalization circuit, and the drain electrode of the MOS tube M1 forms an output end von of the high-frequency equalization circuit. The source electrode of the MOS tube M1, one end of the feedback resistor R5, one end of the feedback capacitor C5, the drain electrode of the MOS tube M3 and the drain electrode of the MOS tube M4 are connected. The grid electrode of the MOS tube M2 forms an input end viph of the high-frequency equalizing circuit, and the drain electrode of the MOS tube M2 forms an output end voph of the high-frequency equalizing circuit. The source electrode of the MOS tube M2, the other end of the feedback resistor R5, the other end of the feedback capacitor C5, the source electrode of the MOS tube M3 and the drain electrode of the MOS tube M5 are connected. The gate of the MOS transistor M3 is connected with the control signal vch. The source electrode of the MOS tube M4 and the source electrode of the MOS tube M5 are grounded, and the grid electrode of the MOS tube M4 and the grid electrode of the MOS tube M5 are connected with external bias voltage Vb.
In the above scheme, the output terminal von of the high-frequency equalization circuit is connected to the input terminal viph of the high-frequency equalization circuit through the decoupling capacitor C1. The output voph of the high-frequency equalization circuit is connected to the input vinh of the high-frequency equalization circuit via a decoupling capacitor C2.
In the scheme, the low-frequency equalization circuit comprises MOS tubes M6-M10, a feedback resistor R6 and a feedback capacitor C6. The grid electrode of the MOS tube M6 forms an input end vinl of the low-frequency equalization circuit, and the drain electrode of the MOS tube M6 forms an output end von of the low-frequency equalization circuit. The source electrode of the MOS tube M6, one end of the feedback resistor R6, one end of the feedback capacitor C6, the drain electrode of the MOS tube M8 and the drain electrode of the MOS tube M9 are connected. The gate of the MOS tube M7 forms an input end vipl of the low-frequency equalizing circuit, and the drain of the MOS tube M7 forms an output end vopl of the low-frequency equalizing circuit. The source electrode of the MOS tube M7, the other end of the feedback resistor R6, the other end of the feedback capacitor C6, the source electrode of the MOS tube M8 and the drain electrode of the MOS tube M10 are connected. The gate of the MOS transistor M8 is connected with a control signal vcl. The source electrode of the MOS tube M9 and the source electrode of the MOS tube M10 are grounded, and the grid electrode of the MOS tube M9 and the grid electrode of the MOS tube M10 are connected with external bias voltage Vb.
In the above scheme, the output terminal von of the low-frequency equalization circuit is connected to the input terminal vipl of the low-frequency equalization circuit through the decoupling capacitor C3. The output terminal vopl of the low-frequency equalization circuit is connected to the input terminal vinl of the low-frequency equalization circuit via a decoupling capacitor C4.
In the scheme, the high-frequency load network comprises inductors L1-L2 and resistors R1-R2. The inductor L1 is connected in series with the resistor R1, the other end of the inductor L1 is connected with a power supply, and the other end of the resistor R1 forms one input end of the high-frequency load network. The inductor L2 is connected in series with the resistor R2, the other end of the inductor L2 is connected with a power supply, and the other end of the resistor R2 forms the other input end of the high-frequency load network.
In the scheme, the low-frequency load network comprises inductors L3-L4 and resistors R3-R4. The inductor L3 is connected in series with the resistor R3, the other end of the inductor L3 is connected with a power supply, and the other end of the resistor R3 forms one input end of the low-frequency load network. The inductor L4 is connected in series with the resistor R4, the other end of the inductor L4 is connected with a power supply, and the other end of the resistor R4 forms the other input end of the low-frequency load network.
In the above scheme, the jitter removing circuit comprises MOS transistors M11-M14. The grid electrode of the MOS tube M11 forms an input end vin of the jitter removing circuit aux The drain electrode of the MOS tube M11 forms an output end von of the debounce circuit aux . The source electrode of the MOS tube M11, the source electrode of the MOS tube M12, the drain electrode of the MOS tube M13 and the drain electrode of the MOS tube M14 are connected. The gate of MOS transistor M12 forms the input terminal vip of the debounce circuit aux The drain electrode of the MOS tube M12 forms an output end vop of the jitter removing circuit aux . The sources of the MOS tube M13 and the MOS tube M14 are grounded. The gates of the MOS transistor M13 and the MOS transistor M14 are connected with an external bias voltage Vb.
In the scheme, the feedback circuit consists of MOS tubes M15-M18. The grid electrode of the MOS tube M15 forms an input end vin of a feedback circuit fb The drain electrode of the MOS tube M15 forms an output end von of the feedback circuit fb . The source electrode of the MOS tube M15, the source electrode of the MOS tube M16, the drain electrode of the MOS tube M17 and the drain electrode of the MOS tube M18 are connected. The grid electrode of the MOS tube M16 forms an input end vip of a feedback circuit fb The drain electrode of the MOS tube M16 forms an output end vop of the feedback circuit fb . The source of the MOS transistor M17 and the source of the MOS transistor M18 are grounded. The grid electrode of the MOS tube M17 and the grid electrode of the MOS tube M18 are connected with an externally applied bias voltage Vb.
In the scheme, the MOS transistors M1-M18 are all NMOS transistors with standard voltage of 1.8V.
Compared with the prior art, the invention has the following characteristics:
1. being able to equalize higher transmission rate data, it is possible to provide a gain difference of 15dB or more for data having a transmission rate of 12.5Gbps.
2. The high-frequency equalization circuit and the low-frequency equalization circuit are connected in series, so that the equalization capacity of a high-attenuation channel is improved.
3. Decoupling capacitance is introduced, load capacitance of the equalization circuit is reduced, and frequency points where poles are located are increased.
4. A debounce circuit is introduced to reduce jitter in the signal equalization process.
Drawings
Fig. 1 is a schematic circuit diagram of a high-speed low-jitter analog equalizer.
FIG. 2 is a graph of the amplitude-frequency curve simulation results of the present invention.
FIG. 3 is a waveform equalizing effect diagram of the present invention; wherein (a) is an input signal; (b) is an output signal.
Detailed Description
The invention will be further described in detail below with reference to specific examples and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the invention more apparent. In the examples, directional terms such as "upper", "lower", "middle", "left", "right", "front", "rear", and the like are merely directions with reference to the drawings. Accordingly, the directions of use are merely illustrative and not intended to limit the scope of the invention.
A high-speed low-jitter analog equalizer is shown in fig. 1, and consists of 2 load networks, namely a high-frequency load network and a low-frequency load network, 2 equalizing circuits, namely a high-frequency equalizing circuit and a low-frequency equalizing circuit, 1 jitter removing circuit and 1 feedback circuit.
The high-frequency equalization circuit comprises MOS tubes M1-M5, a feedback resistor R5 and a feedback capacitor C5. The MOS tube M1 and the MOS tube M2 are differential pair amplifying tubes, a parallel network formed by the feedback resistor R5, the feedback capacitor C5 and the MOS tube M3 is a negative feedback network of a differential pair, and the MOS tube M4 and the MOS tube M5 are differential pair tail current tubes. The drain electrode of the MOS tube M1 forms an output end von of the high-frequency equalizing circuit, the grid electrode of the MOS tube M1 forms an input end vinh of the high-frequency equalizing circuit, and the source electrode of the MOS tube M1, one end of the feedback resistor R5, one end of the feedback capacitor C5, the drain electrode of the MOS tube M3 and the drain electrode of the MOS tube M4 are connected; the drain electrode of the MOS tube M2 forms an output end voph of the high-frequency equalizing circuit, the grid electrode of the MOS tube M2 forms an input end vip of the high-frequency equalizing circuit, and the source electrode of the MOS tube M2, the other end of the feedback resistor R5, the other end of the feedback capacitor C5, the source electrode of the MOS tube M3 and the drain electrode of the MOS tube M5 are connected; the grid electrode of the MOS tube M3 is connected with a control signal vch; the source electrode of the MOS tube M4 and the source electrode of the MOS tube M5 are grounded, and the grid electrode of the MOS tube M4 and the grid electrode of the MOS tube M5 are connected with external bias voltage Vb. In addition, the output von h and voph of the high-frequency equalizing circuit are respectively connected with the input end viph and vinh of the high-frequency equalizing circuit through decoupling capacitors C1 and C2 so as to reduce load capacitance and increase the frequency point where the generating pole is located.
The low-frequency equalization circuit comprises MOS tubes M6-M10, a feedback resistor R6 and a feedback capacitor C6. The MOS tube M6 and the MOS tube M7 are differential pair amplifying tubes, a parallel network formed by the feedback resistor R6, the feedback capacitor C6 and the MOS tube M8 is a negative feedback network of a differential pair, and the MOS tube M9 and the MOS tube M10 are differential pair tail current tubes. The drain electrode of the MOS tube M6 forms an output end von of the low-frequency equalizing circuit, the grid electrode of the MOS tube M6 forms an input end vinl of the low-frequency equalizing circuit, and the source electrode of the MOS tube M6, one end of the feedback resistor R6, one end of the feedback capacitor C6, the drain electrode of the MOS tube M8 and the drain electrode of the MOS tube M9 are connected; the drain electrode of the MOS tube M7 forms an output end vopl of the low-frequency equalizing circuit, the grid electrode of the MOS tube M7 forms an input end vipl of the low-frequency equalizing circuit, and the source electrode of the MOS tube M7, the other end of the feedback resistor R6, the other end of the feedback capacitor C6, the source electrode of the MOS tube M8 and the drain electrode of the MOS tube M10 are connected; the grid electrode of the MOS tube M8 is connected with a control signal vcl; the source electrode of the MOS tube M9 and the source electrode of the MOS tube M10 are grounded, and the grid electrode of the MOS tube M9 and the grid electrode of the MOS tube M10 are connected with external bias voltage Vb. In addition, the output von l and vopl of the low-frequency equalizing circuit are respectively connected with the input terminal vipl and vinl of the low-frequency equalizing circuit through decoupling capacitors C3 and C4, so that the load capacitance is reduced, and the frequency point where the generating pole is located is increased.
The high frequency load network includes inductances L1-L2 and resistances R1-R2. The inductor L1 is connected with the resistor R1 in series, the other end of the inductor L1 is connected with a power supply, and the other end of the resistor R1 is connected with one output von of the high-frequency equalizing circuit; the inductor L2 is connected in series with the resistor R2, the other end of the inductor L2 is connected with a power supply, and the other end of the resistor R2 is connected with the other output von of the high-frequency equalizing circuit.
The low frequency load network includes inductors L3-L4 and resistors R3-R4. The inductor L3 is connected with the resistor R3 in series, the other end of the inductor L3 is connected with a power supply, and the other end of the resistor R3 is connected with one output von of the low-frequency equalizing circuit; the inductor L4 is connected in series with the resistor R4, the other end of the inductor L4 is connected with a power supply, and the other end of the resistor R4 is connected with the other output vopl of the low-frequency equalization circuit.
The feedback circuit consists of MOS transistors M15-M18. The MOS tube M15 and the MOS tube M16 are differential pair tubes with feedback amplification function, and the MOS tube M17 and the MOS tube M18 are differential tail current tubes. The drain electrode of the MOS tube M15 is connected with the output end von of the feedback circuit fb The method comprises the steps of carrying out a first treatment on the surface of the The grid electrode of the MOS tube M15 is connected with the input end vin of the feedback circuit fb The method comprises the steps of carrying out a first treatment on the surface of the The source electrode of the MOS tube M15, the source electrode of the MOS tube M16, the drain electrode of the MOS tube M17 and the drain electrode of the MOS tube M18 are connected; the drain electrode of the MOS tube M16 is connected with the other output end vop of the feedback circuit fb The method comprises the steps of carrying out a first treatment on the surface of the The grid electrode of the MOS tube M16 is connected with the other input end vip of the feedback circuit fb The method comprises the steps of carrying out a first treatment on the surface of the The source electrode of the MOS tube M17 and the source electrode of the MOS tube M18 are grounded; the grid electrode of the MOS tube M17 and the grid electrode of the MOS tube M18 are connected with an externally applied bias voltage Vb.
The jitter removing circuit comprises MOS transistors M11-M14. The MOS tube M11 and the MOS tube M12 play a role in eliminating the differential pair tubes of jitter, and the MOS tube M13 and the MOS tube M14 are differential tail current tubes. The drain electrode of the MOS tube M11 is connected with the output end von of the jitter removing circuit aux The method comprises the steps of carrying out a first treatment on the surface of the The gate of the MOS transistor M11 is connected to the input terminal vin of the jitter removing circuit aux The method comprises the steps of carrying out a first treatment on the surface of the The source electrode of the MOS tube M11, the source electrode of the MOS tube M12, the drain electrode of the MOS tube M13 and the drain electrode of the MOS tube M14 are connected; the drain electrode of the MOS tube M12 is connected with the other output end vop of the q-jitter removing circuit aux The method comprises the steps of carrying out a first treatment on the surface of the The gate of the MOS transistor M12 is connected to the other input terminal vip of the jitter removing circuit aux The method comprises the steps of carrying out a first treatment on the surface of the Sources of the MOS tube M13 and the MOS tube M14 are grounded; the gates of the MOS transistor M13 and the MOS transistor M14 are connected with an external bias voltage Vb.
Input ends vinh and vip of the high-frequency balancing circuit are respectively connected with balanced input signals vin and vip, and outputs von h and voph of the high-frequency balancing circuit and the high-frequency load network are connected with the input of the low-frequency balancing circuitThe outputs von h and voph of the high-frequency equalization circuit are connected to the input vip and vin of the high-frequency equalization circuit via decoupling capacitors C1 and C2, respectively. The output von and vopl of the low-frequency equalizing circuit and the output von and vop of the low-frequency load network are connected with equalizing output signals von and vop, and the output von and vopl of the low-frequency equalizing circuit are connected with the input end vipl of the low-frequency equalizing circuit through decoupling capacitors C3 and C4 respectively. Input vin of debounce circuit aux And vip aux Respectively connected with the outputs von h and voph of the high-frequency equalization circuit and the output von of the debounce circuit aux With vop aux The outputs von and vopl of the low frequency equalizing circuit are connected respectively. Input vin of feedback circuit fb And vip fb Respectively connected with the output terminals von and vopl of the low-frequency equalization circuit and the output terminal von of the feedback circuit fb With vop fb The input terminals vipl and vinl of the low-frequency equalization circuit are connected respectively. In the preferred embodiment of the invention, the MOS transistors M1-M18 are all NMOS transistors with standard voltage of 1.8V.
The 2 equalization circuits have the same structure, namely, each equalization circuit consists of a differential pair with capacitive resistance negative feedback, and the differential pair generates a zero point on the left side of a complex frequency domain and generates two poles due to the negative feedback effect of the capacitive resistance; the position of the zero point is related to the sizes of the feedback resistor and the feedback capacitor, and when the gain curve passes through the zero point, the gain rises, so that the compensation effect on the channel attenuation after the zero point can be realized. In the invention, a structure that a high-frequency equalization circuit and a low-frequency equalization circuit are connected in series is adopted, the whole equalization circuit can generate two zero points and four poles, the gain curve can rise with the slope of +40dB/dec after passing through the two zero points, the values of a feedback resistor and a feedback capacitor are reasonably adjusted, the position relation between the zero points and the poles is changed, the gain difference between the high frequency and the low frequency can be improved, and the equalization capacity of a high-loss channel is improved. Meanwhile, due to the existence of the decoupling capacitor, the load capacitance of the two equalization circuits is reduced, and then the frequency point where the pole is located is increased, so that signals with higher transmission rate can be equalized. The 2 load networks have the same structure, and the balancing circuits and the corresponding load networks are connected in series, namely, the high-frequency balancing circuit is connected in series with the high-frequency load network, and the low-frequency balancing circuit is connected in series with the low-frequency load network. The output signal of the high-frequency equalization circuit compensates the signal passing through the low-frequency equalization circuit through the jitter removing circuit, so that zero-crossing jitter of the output signal of the low-frequency equalization circuit is reduced. The feedback circuit takes the output of the low-frequency equalization circuit as input, and the output compensates the output of the high-frequency equalization circuit, so that zero jitter of the differential signal is reduced. The invention has the characteristics of high equalization rate, remarkable compensation to the strong attenuation channel and small jitter of the output signal.
For the high-speed low-jitter analog equalizer shown in fig. 1, a 0.18um CMOS process design is adopted, and the amplitude-frequency curve of the equalizer shown in fig. 2 and the waveform equalization effect diagram shown in fig. 3 are obtained through simulation. Simulation results show that the gain difference between the high frequency and the low frequency can reach 20dB, the high frequency signal component of the high attenuation channel signal can be well compensated, and the balanced data transmission rate can reach 12.5Gbps.
It should be noted that, although the examples described above are illustrative, this is not a limitation of the present invention, and thus the present invention is not limited to the above-described specific embodiments. Other embodiments, which are apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein, are considered to be within the scope of the invention as claimed.
Claims (10)
1. The high-speed low-jitter analog equalizer is characterized by comprising 2 load networks, 2 equalizing circuits, 1 jitter removing circuit and 1 feedback circuit; the 2 load networks, namely the high-frequency load network and the low-frequency load network, have the same structure; the 2 equalization circuits, namely the high-frequency equalization circuit and the low-frequency equalization circuit, have the same structure, are all composed of differential pairs with capacitance and resistance negative feedback, and the differential pairs generate a zero point on the left side of a complex frequency domain and generate two poles;
one input end of the high-frequency load network is connected with an output end von of the high-frequency balancing circuit; the other input end of the high-frequency load network is connected with the output end voph of the high-frequency balancing circuit; one input end of the low-frequency load network is connected with an output end von of the low-frequency equalizing circuit; the other input end of the low-frequency load network is connected with the output end vopl of the low-frequency equalizing circuit;
the input end vinh of the high-frequency equalization circuit is connected with the equalization input signal vin, and the input end viph of the high-frequency equalization circuit is connected with the equalization input signal vip;
the output end von of the low-frequency equalization circuit is connected with the equalization output signal von, and the output end vopl of the low-frequency equalization circuit is connected with the equalization output signal vop;
the output end von of the high-frequency equalizing circuit is connected with the input end vinl of the low-frequency equalizing circuit, and the output end voph of the high-frequency equalizing circuit is connected with the input end vipl of the low-frequency equalizing circuit;
input terminal vin of debounce circuit aux The output end von of the high-frequency equalization circuit is connected with the input end vip of the debounce circuit aux The output end voph of the high-frequency equalization circuit is connected; output terminal von of debounce circuit aux The output end von of the low-frequency equalization circuit and the output end vop of the debounce circuit are connected aux The output terminal vopl of the low-frequency equalization circuit is connected;
input terminal vin of feedback circuit fb The input end vip of the feedback circuit is connected with the output end von of the low-frequency equalization circuit fb The output terminal vopl of the low-frequency equalization circuit is connected; output terminal von of feedback circuit fb The input end vipl of the low-frequency equalization circuit is connected, and the output end vop of the feedback circuit fb The input terminal vinl of the low-frequency equalization circuit is connected.
2. The high-speed low-jitter analog equalizer of claim 1, wherein the high-frequency equalization circuit comprises MOS transistors M1-M5, a feedback resistor R5 and a feedback capacitor C5;
the grid electrode of the MOS tube M1 forms an input end vinh of the high-frequency equalization circuit, and the drain electrode of the MOS tube M1 forms an output end von of the high-frequency equalization circuit;
the source electrode of the MOS tube M1, one end of the feedback resistor R5, one end of the feedback capacitor C5, the drain electrode of the MOS tube M3 and the drain electrode of the MOS tube M4 are connected;
the grid electrode of the MOS tube M2 forms an input end viph of the high-frequency equalization circuit, and the drain electrode of the MOS tube M2 forms an output end voph of the high-frequency equalization circuit;
the source electrode of the MOS tube M2, the other end of the feedback resistor R5, the other end of the feedback capacitor C5, the source electrode of the MOS tube M3 and the drain electrode of the MOS tube M5 are connected;
the grid electrode of the MOS tube M3 is connected with a control signal vch; the source electrode of the MOS tube M4 and the source electrode of the MOS tube M5 are grounded, and the grid electrode of the MOS tube M4 and the grid electrode of the MOS tube M5 are connected with external bias voltage Vb.
3. A high-speed low-jitter analog equalizer according to claim 1 or 2, wherein the output von of the high-frequency equalizing circuit is connected to the input viph of the high-frequency equalizing circuit via a decoupling capacitor C1; the output voph of the high-frequency equalization circuit is connected to the input vinh of the high-frequency equalization circuit via a decoupling capacitor C2.
4. The high-speed low-jitter analog equalizer of claim 1, wherein the low-frequency equalization circuit comprises MOS transistors M6-M10, a feedback resistor R6 and a feedback capacitor C6;
the grid electrode of the MOS tube M6 forms an input end vinl of the low-frequency equalization circuit, and the drain electrode of the MOS tube M6 forms an output end von of the low-frequency equalization circuit;
the source electrode of the MOS tube M6, one end of the feedback resistor R6, one end of the feedback capacitor C6, the drain electrode of the MOS tube M8 and the drain electrode of the MOS tube M9 are connected;
the grid electrode of the MOS tube M7 forms an input end vipl of the low-frequency equalizing circuit, and the drain electrode of the MOS tube M7 forms an output end vopl of the low-frequency equalizing circuit;
the source electrode of the MOS tube M7, the other end of the feedback resistor R6, the other end of the feedback capacitor C6, the source electrode of the MOS tube M8 and the drain electrode of the MOS tube M10 are connected;
the grid electrode of the MOS tube M8 is connected with a control signal vcl; the source electrode of the MOS tube M9 and the source electrode of the MOS tube M10 are grounded, and the grid electrode of the MOS tube M9 and the grid electrode of the MOS tube M10 are connected with external bias voltage Vb.
5. A high-speed low-jitter analog equalizer according to claim 1 or 4, wherein the output von of the low-frequency equalizing circuit is connected to the input vpl of the low-frequency equalizing circuit via a decoupling capacitor C3; the output terminal vopl of the low-frequency equalization circuit is connected to the input terminal vinl of the low-frequency equalization circuit via a decoupling capacitor C4.
6. A high-speed low-jitter analog equalizer according to claim 1, wherein the high-frequency load network comprises inductors L1-L2 and resistors R1-R2; the inductor L1 is connected with the resistor R1 in series, the other end of the inductor L1 is connected with a power supply, and the other end of the resistor R1 forms one input end of a high-frequency load network; the inductor L2 is connected in series with the resistor R2, the other end of the inductor L2 is connected with a power supply, and the other end of the resistor R2 forms the other input end of the high-frequency load network.
7. A high-speed low-jitter analog equalizer according to claim 1, wherein the low-frequency load network comprises inductors L3-L4 and resistors R3-R4; the inductor L3 is connected with the resistor R3 in series, the other end of the inductor L3 is connected with a power supply, and the other end of the resistor R3 forms an input end of the low-frequency load network; the inductor L4 is connected in series with the resistor R4, the other end of the inductor L4 is connected with a power supply, and the other end of the resistor R4 forms the other input end of the low-frequency load network.
8. The high-speed low-jitter analog equalizer of claim 1, wherein the debounce circuit comprises MOS transistors M11-M14;
the grid electrode of the MOS tube M11 forms an input end vin of the jitter removing circuit aux The drain electrode of the MOS tube M11 forms an output end von of the debounce circuit aux ；
The source electrode of the MOS tube M11, the source electrode of the MOS tube M12, the drain electrode of the MOS tube M13 and the drain electrode of the MOS tube M14 are connected;
the gate of MOS transistor M12 forms the input terminal vip of the debounce circuit aux The drain electrode of the MOS tube M12 forms an output end vop of the jitter removing circuit aux ；
Sources of the MOS tube M13 and the MOS tube M14 are grounded; the gates of the MOS transistor M13 and the MOS transistor M14 are connected with an external bias voltage Vb.
9. The high-speed low-jitter analog equalizer of claim 1, wherein the feedback circuit is composed of MOS transistors M15-M18;
the grid electrode of the MOS tube M15 forms an input end vin of a feedback circuit fb The drain electrode of the MOS tube M15 forms an output end von of the feedback circuit fb ；
The source electrode of the MOS tube M15, the source electrode of the MOS tube M16, the drain electrode of the MOS tube M17 and the drain electrode of the MOS tube M18 are connected;
the grid electrode of the MOS tube M16 forms an input end vip of a feedback circuit fb The drain electrode of the MOS tube M16 forms an output end vop of the feedback circuit fb ；
The source electrode of the MOS tube M17 and the source electrode of the MOS tube M18 are grounded; the grid electrode of the MOS tube M17 and the grid electrode of the MOS tube M18 are connected with an externally applied bias voltage Vb.
10. The high-speed low-jitter analog equalizer of claim 1, wherein the MOS transistors M1-M18 are all NMOS transistors with standard voltage of 1.8V.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103746671A (en) * | 2014-01-24 | 2014-04-23 | 南京邮电大学 | Equalizing filter with high gain and wide compensation range |
| CN106209709A (en) * | 2016-07-15 | 2016-12-07 | 中国电子科技集团公司第五十八研究所 | A kind of linear equalizer being applicable to HSSI High-Speed Serial Interface |
| CN106656883A (en) * | 2016-12-22 | 2017-05-10 | 桂林电子科技大学 | Low-frequency gain band-wise adjustable linear equalizer |
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| US9520872B2 (en) * | 2014-12-23 | 2016-12-13 | Qualcomm Incorporated | Linear equalizer with variable gain |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103746671A (en) * | 2014-01-24 | 2014-04-23 | 南京邮电大学 | Equalizing filter with high gain and wide compensation range |
| CN106209709A (en) * | 2016-07-15 | 2016-12-07 | 中国电子科技集团公司第五十八研究所 | A kind of linear equalizer being applicable to HSSI High-Speed Serial Interface |
| CN106656883A (en) * | 2016-12-22 | 2017-05-10 | 桂林电子科技大学 | Low-frequency gain band-wise adjustable linear equalizer |
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