CN108549181A - A kind of array substrate, display device and test method - Google Patents
A kind of array substrate, display device and test method Download PDFInfo
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- CN108549181A CN108549181A CN201810385802.7A CN201810385802A CN108549181A CN 108549181 A CN108549181 A CN 108549181A CN 201810385802 A CN201810385802 A CN 201810385802A CN 108549181 A CN108549181 A CN 108549181A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136254—Checking; Testing
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- Crystallography & Structural Chemistry (AREA)
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Abstract
A kind of array substrate, display device and test method, the array substrate include：First signal wire and second signal line, first signal wire and the second signal line are disconnected from each other, and first signal wire and the second signal line are coupled to the different location of same grid line.Array substrate provided in this embodiment provides independent two independent signal wires for same grid line, realizes the detection to grid line virtual connection.
Description
Technical field
The present invention relates to electronic technology, espespecially a kind of array substrate, display device and test method.
Background technology
LCD (Liquid Crystal Display, liquid crystal display) is the display equipment of planar ultra-thin, it is by a fixed number
The colour or monochrome pixels of amount form.Liquid crystal display is with thin film transistor (TFT) (Thin Film Transistor, TFT) at present
Based on liquid crystal display, manufacturing process can be roughly divided into three parts：Thin film transistor (TFT) array (TFT Array) prepares and coloured silk
Prepared by color filter, prepared by liquid crystal display assembling (LC Cell Assembly), LCD MODULE (Liquid
Crystal Module, LCM) it prepares.Liquid crystal display panel needs to carry out multiple check problems during making, one of them
Critically important check problem is exactly that the liquid crystal cell completed to cutting is tested (Cell Test), to confirm that liquid crystal cell whether there is
Defect.Cell Test abbreviation ET, for liquid crystal display panel do not attach driving chip and input show signal flexible PCB it
Preceding progress.The test process makes its pixel that color be presented, then passes through defects detection before this to liquid crystal display panel input test signal
Device observes whether each pixel is good, this process is known as lighting test (Light-on Test) one by one.
It is higher and higher to the characteristic and durability requirements of product as display field develops, functionality can not occur
It is bad, such as X-line (bright line), the problems such as Open (broken string).Currently, LCD products are difficult effectively to intercept this during ET lightings
Badness causes rear end module goods, materials and equipments to waste.More very, bad products flow into client and cause serious loss.
Invention content
A present invention at least embodiment provides a kind of array substrate panel and display device, test method, realizes to not
Good detection.
In order to reach the object of the invention, a present invention at least embodiment provides a kind of array substrate, including：First signal
Line and second signal line, first signal wire and the second signal line are disconnected from each other, and first signal wire and described
Second signal line is coupled to the different location of same grid line.
A present invention at least embodiment provides a kind of display device, including the array substrate described in any embodiment.
A present invention at least embodiment provides a kind of test method of above-mentioned array substrate, including：
First voltage signal is provided to first signal wire, provides to the second signal line and believes with the first voltage
Number opposite polarity second voltage signal.
Compared with the relevant technologies, the array substrate that one embodiment of the invention provides includes the first signal wire and second signal
Line, first signal wire and the second signal line are disconnected from each other, and first signal wire and the second signal line coupling
It is connected to the different location of same grid line.Array substrate provided in this embodiment provides independent two independent letters for same grid line
Number line realizes the detection to grid line virtual connection.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.The purpose of the present invention and other advantages can be by specification, rights
Specifically noted structure is realized and is obtained in claim and attached drawing.
Description of the drawings
Attached drawing is used for providing further understanding technical solution of the present invention, and a part for constitution instruction, with this
The embodiment of application technical solution for explaining the present invention together, does not constitute the limitation to technical solution of the present invention.
Fig. 1 be Gate (grid) normally with the schematic diagram of virtual connection；
Fig. 2 is ET pad (testing weld pad) cabling schematic diagram in the related technology；
Fig. 3 is a kind of structure chart of GOA circuits in the related technology；
Fig. 4 is the array substrate schematic diagram that one embodiment of the invention provides；
Fig. 5 is the array substrate schematic diagram that another embodiment of the present invention provides；
Fig. 6 a are the array substrate schematic diagram that another embodiment of the present invention provides；
Fig. 6 b are the array substrate schematic diagram that another embodiment of the present invention provides；
Fig. 7 a are the array substrate schematic diagram that another embodiment of the present invention provides；
Fig. 7 b are the array substrate schematic diagram that another embodiment of the present invention provides；
Fig. 7 c are the array substrate schematic diagram that another embodiment of the present invention provides；
Fig. 8 is the GOA circuit diagrams that one embodiment of the invention provides；
Fig. 9 is the GOA circuit diagrams that one embodiment of the invention provides；
Figure 10 is the test method flow chart that one embodiment of the invention provides.
Specific implementation mode
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention
Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application
Feature mutually can arbitrarily combine.
Step shown in the flowchart of the accompanying drawings can be in the computer system of such as a group of computer-executable instructions
It executes.Also, although logical order is shown in flow charts, and it in some cases, can be with suitable different from herein
Sequence executes shown or described step.
Unless otherwise defined, the technical term or scientific terminology that the disclosure uses should be tool in fields of the present invention
There is the ordinary meaning that the personage of general technical ability is understood." first ", " second " and the similar word used in the disclosure is simultaneously
It does not indicate that any sequence, quantity or importance, and is used only to distinguish different component parts." comprising " or "comprising" etc.
Similar word means to occur the element before the word, and either object covers the element or object for appearing in the word presented hereinafter
And its it is equivalent, and it is not excluded for other elements or object.The similar word such as " connection " or " connected " is not limited to physics
Or mechanical connection, but may include electrical connection, either directly or indirectly."upper", "lower",
"left", "right" etc. is only used for indicating relative position relation, and after the absolute position for being described object changes, then the relative position is closed
System may also correspondingly change.
Fig. 1 be Gate (grid) normally with the schematic diagram of virtual connection.As shown in Figure 1, in normal product such as Fig. 1 shown in (a) figure.It is different
The connection that normal product occurs during processing procedure as (b) figure is irised out in Fig. 1 is abnormal, seemingly connects like disconnected, virtual connection state, such product is past
Toward cannot effectively be intercepted in process stage, deleterious effect is generated to client.
It, can be by inputting opposite polarity signal in same grid line so that in the position of circuit virtual connection for above-mentioned bad
It sets and heat condition occurs and burn, carry out lighting test again later, since virtual connection position has disconnected, corresponding pixel unit can not
It lights, to realize that detection circuit virtual connection situation, detection are bad.
Fig. 2 is panel (panel) ET pad (testing weld pad) cabling schematic diagram in the related technology.In the related technology, it uses
GOA (Gate Driver On Array, array substrate gate driving) technology, array substrate is produced on by gate driving circuit
On.AA is viewing area in Fig. 2, and the viewing area both sides AA are provided with GOA circuit (not shown).GOA circuits provide gate driving for TFT
Signal.GOA drivings include two kinds, bilateral GOA drivings and unilateral GOA drivings.Wherein, bilateral driving refers to corresponding a line grid line,
Left and right sides tool drives it there are one GOA unit, and unilateral driving, which refers to that only there are one GOA units, carries out a line grid line
Driving, for example, the GOA unit of side drives odd-numbered line grid line, the GOA unit of the other side to drive even number line grid line.Such as Fig. 2 institutes
Show, is that GOA unit applies VGH voltages and VGL voltages, wherein VGH (high level) and VGL are (low by VGH cablings and VGL cablings
Level) be respectively TFT cut-in voltage and shutdown voltage.In the related technology, effect is driven in order to reach lighting and GOA,
When ET lightings, VGH, VGL give signal on one side.Fig. 3 is a kind of structure chart of GOA circuits in the related technology.In circuit shown in Fig. 3,
Can be drawn high by Reset signals, whole GOA output signals (such as OUTPUT_N) are become into VGL signals, but due to left side and
VGH the or VGL signals of right side input are consistent, therefore when cannot achieve ET lightings, left side GOA unit and the output of right side GOA unit
Opposite gate drive signal is to same grid line, therefore, it is bad can not to detect grid line virtual connection in the related technology.
Embodiment one
As shown in figure 4, the present embodiment provides a kind of array substrates 40, including：First signal wire 401 and second signal line
402, first signal wire 401 and the second signal line 402 are disconnected from each other, and first signal wire 401 and described
Binary signal line 402 is coupled to the different location of same grid line 403.
For example, first signal wire 401 and the second signal line 402 are coupled to the different location of same grid line 403
Including：First signal wire 401 and the second signal line 402 are coupled to the both ends of same grid line 403.
It should be noted that only showing a grid line in figure, there is a plurality of grid line in array substrate 40, remaining grid line is similar,
No longer illustrate herein.
In the present embodiment, the signal wire being disconnected from each other by two is coupled to same grid line, can pass through this two bars
Line is embodied as same grid line and inputs opposite polarity unlike signal respectively, if the grid line, there are virtual connection, the position of virtual connection goes out
Existing heat condition is simultaneously burnt, and exposes that this is bad, carries out lighting test again later, since virtual connection position has disconnected, corresponding picture
Plain unit can not be lighted, to realize that detection circuit virtual connection situation, detection are bad.
In one embodiment, first signal wire 401 is connected with testing weld pad 404, and the second signal line 402 connects
There is testing weld pad 405.Testing weld pad is for facilitating to 402 input signal of the first signal wire 401 and second signal line.Testing weld pad
404 and testing weld pad 405 can be arranged directly on its connection signal wire end, signal can also be connected to by a lead
Line is convenient for the layout of testing weld pad.Testing weld pad 404 and testing weld pad 405 are such as circular pad or square pads, when
So, or other shapes, the application are not construed as limiting this.
Embodiment two
As shown in figure 5, in the present embodiment, on the basis of Fig. 4, wrapped between first signal wire 401 and the grid line 403
The first GOA circuits 406 are included, the first signal wire 401 is coupled to grid line 403, first signal wire by the first GOA circuits 406
401 are coupled to the driving signal input (such as VGH, VGL input terminal) of the first GOA circuits 406, the first GOA electricity
The driving signal output end on road 406 is coupled to one end of the grid line 403, the second signal line 402 and the grid line 403 it
Between include the 2nd GOA circuits 407, second signal line 402 is coupled to grid line 403 by the 2nd GOA circuits 407, second letter
Number line 402 is coupled to the driving signal input (such as VGH, VGL input terminal) of the 2nd GOA circuits 407, and described second
The driving signal output end of GOA circuits 407 is coupled to the other end of the grid line 403.The program can be applied to bilateral GOA and drive
In the case of dynamic.
In one embodiment, the first signal wire 401 can use existing gate drive signal line, first signal wire
401 be such as the first high level drive signal line (such as signal wire for inputting VGH signals) and the first low level driving letter
At least one number line (such as signal wire for inputting VGL signals), the first high level drive signal line and described first
Low level drive signal line is coupled to the driving signal input of the first GOA circuits, and the second signal line 402 is such as
At least one second high level drive signal line and the second low level drive signal line, the second high level drive signal line and
The second low level drive signal line is coupled to the driving signal input of the 2nd GOA circuits.
Embodiment three
As shown in Figure 6 a, in the present embodiment, on the basis of Fig. 4, between first signal wire 401 and the grid line 403
Including the first GOA circuits 406, first signal wire 401 is coupled to the driving signal input of the first GOA circuits 406
(such as VGH, VGL input terminal), the driving signal output end of the first GOA circuits 406 is coupled to the one of the grid line 403
End, the second signal line 402 are coupled to the other end of the grid line by switching circuit 408.The program can be applied to list
In the case of side GOA drivings.When switching circuit 408 is connected, the grid line is connected with the second signal line 402, switching circuit 408
When disconnection, the grid line is disconnected with the second signal line 402.As shown in Figure 6 b, the switching circuit 408 is such as a crystal
Pipe, grid line 403 and second signal line 403 are connected to the both ends of the transistor.It should be noted that it is merely illustrative herein,
Other switching circuits can be used as needed.
In one embodiment, first signal wire 401 includes that the first high level drive signal line and the first low level are driven
At least one dynamic signal wire, the first high level drive signal line for input high level signal to the first GOA circuits,
The first low level drive signal line is for input low level signal to the first GOA circuits.First high level drives
Dynamic signal wire and the first low level drive signal line are coupled to the driving signal input of the first GOA circuits.It is described
Second signal line 402 is such as at least one the second high level drive signal line and the second low level drive signal line, described the
The drive signal that two high level drive signal lines and the second low level drive signal line are coupled to the 2nd GOA circuits is defeated
Enter end.
Example IV
VGL, VGH ET pad are changed to both sides input mode in this programme, design is turned off in IC offsides.In this way,
The VGH and VGL of both sides GOA can individually be controlled.
As shown in Figure 7a, in the present embodiment, by outside Panel point lamp driver normal configurations, adding in the Gate lines other side
Power up signal input function, (circled is shown in such as Fig. 7 a) is disconnected by existing VGH lines, VGL lines, increases VGH on right side
Pad and VGL pad provide different signals to be embodied as left and right GOA.After increasing this structure, when product E T, side input is normal
Point modulating signal, the other side inputs opposite polarity signals, by inputting opposite polarity signal on Gate lines, in circuit virtual connection
There is heat condition and burns in position, to realize that detection circuit virtual connection situation, detection are bad.I.e. in the embodiment, the first letter
Number line is VGH line 701a and VGL the line 702a in left side, and second signal line is VGH line 703a and VGL the line 704a on right side, and,
VGH line 701a and VGH lines 703a is disconnected from each other, and VGL line 702a and VGL line lines 704a is disconnected from each other.
In another embodiment, as shown in Figure 7b, only existing VGH lines can be disconnected, at left and right sides of existing VGL lines
Connection is kept, increases VGH pad (not increasing VGL pad) on right side, different signals is provided to be embodied as left and right GOA.I.e. should
In embodiment, the first signal wire is the VGH line 701b in left side, and second signal line is the VGH line 703b on right side, and, VGH lines 701b
It is disconnected from each other with VGH lines 703b.VGH signals can be applied on the VGH pad of VGH lines 701b connections, in the 703b connections of VGH lines
VGH pad on apply VGL signals so that there is heat condition and burns in the position of grid line virtual connection.
In another embodiment, as shown in Figure 7 c, only existing VGL lines can be disconnected, at left and right sides of existing VGH lines
Connection is kept, increases VGL pad (not increasing VGH pad) on right side, different signals is provided to be embodied as left and right GOA.I.e. should
In embodiment, the first signal wire is the VGL line 702c in left side, and second signal line is the VGL line 704c on right side, and, VGL lines 702c
It is disconnected from each other with VGL lines 704c.VGH signals can be applied on the VGL pad of VGL lines 702c connections, in the 704c connections of VGL lines
VGL pad on apply VGL signals so that there is heat condition and burns in the position of grid line virtual connection.
It is illustrated with scheme shown in Fig. 7 a.As shown in figure 8, to side GOA, when Reset signals are high, in VGL
Pad applies VGL signals (low level signal), and GOA circuits export VGL signals to Gate lines by OUTPUT_N.As shown in figure 9,
To other side GOA, such as：When Reset signals provide, VGH signals (high level signal) are provided to the GOA, the side by VGL pad
GOA exports VGH signals to Gate lines by OUTPUT_N, at this point, the signal polarity at Gate lines both ends it is opposite (one is VGL, one
A is VGH).And when Gate lines or so offer unlike signal, virtual connection position is equivalent at one electric herein similar to high resistance position
Resistance.According to Joule's law：Joule heat Q=I2RT, resistance R is bigger, and heat Q is bigger, to which the virtual connection part of Gate lines is broken
The problems such as road, effective detection line badness in ET lightings, prevents client's point from function badness occur and leading to dotted line, reparation.
And regular link no problem, Gate lines are not in fever and burn abnormal problem.Such design is suitable for bilateral GOA driving productions
Product improve Gate open badness.It should be noted that the VGL input terminals of GOA circuits can also be VGH inputs in Fig. 8, Fig. 9
End, i.e. the two share the input terminal.It should be noted that GOA circuits shown in Fig. 8 and Fig. 9 are only to illustrate, the application does not make this
It limits.Other GOA circuits are also applicable in the application.
It should be noted that the application is not limited to be also suitable using the array substrate of GOA technologies, other array substrates.
Embodiment five
It, can be by one of left side VGH signal wires and VGL signal wires as the first letter for unilateral driving GOA products
Number line regard one of right side VGH signal wires and VGL signal wires as second signal line, one end connection GOA circuits of grid line
The other end of driving signal output end, grid line is coupled to second signal line by switching circuit.For example, left side GOA is odd-numbered line
Grid line provides drive signal, and when right side GOA provides drive signal for even number line grid line, second signal line is connected by switching circuit
To the right end of odd-numbered line grid line, the left end of even number line grid line.At this point it is possible to provide VGL signals in grid line side, the other side provides
VGH signals, for example, side provides VGL signals by GOA circuits, the other side directly provides VGH signals by second signal line
(at this point, the control signal EN Touch of switching circuit are drawn high, VGH signals are provided by VGH pad or VGL pad), according to
Joule's law：Joule heat Q=I2RT, resistance R is bigger, and heat Q is bigger, and virtual connection part Gate lines or so, which provide positive negative signal, to be occurred
Open circuit, and then intercept bad.
Embodiment six
The present embodiment provides a kind of display device, which includes the array substrate that any of the above-described embodiment provides.
One example of the display device is liquid crystal display device.
The display device can be any product or component with display function, such as mobile phone, tablet computer, TV
Machine, display, laptop, Digital Frame and navigator.
Embodiment seven
As shown in Figure 10, the present embodiment provides a kind of test method of the array substrate described in any of the above-described embodiment, packets
It includes：
Step 1001, to first signal wire provide first voltage signal, to the second signal line provide with it is described
The opposite second voltage signal of first voltage signal polarity.
In the present embodiment, by applying opposite polarity voltage signal on same grid line so that burn simultaneously virtual connection position
It disconnects, to which exposure is bad.
Wherein, first voltage signal and second voltage signal can be VGH signals and VGL signals respectively, need to illustrate
It is that merely illustrative herein, first voltage signal and second voltage signal can also be other opposite polarity voltage signals, specifically
Value can be obtained by testing.
In one embodiment, to first signal wire provide first voltage signal, to the second signal line provide with
Further include step 1002 after the opposite second voltage signal of the first voltage signal polarity：Carry out lighting test.Pass through step
After rapid 1001 make virtual connection position disconnect, then apply lighting test signal, carries out lighting test.Specific lighting test method is herein
It repeats no more.
By taking scheme shown in Fig. 7 a as an example, illustratively test method.Apply VGH signals on VGH lines 701a, then left side
GOA exports VGH signals to grid line, applies VGL signals on VGL lines 704a, then right side GOA output VGL signals to grid line, this
When, grid line both sides are applied with VGH signals and VGL signals respectively, if grid line, there are virtual connection, the position of virtual connection at this time is sent out
Enthusiasm condition simultaneously burns to disconnect.Then following lighting test is carried out：Apply VGH signals on VGH lines 701a, in VGH lines
Apply VGH signals on 703a, later, applies VGL signals on VGL lines 702a, apply VGL signals on VGL lines 704a.
By taking scheme shown in Fig. 7 b as an example, apply VGH signals on VGH lines 701b, then left side GOA exports VGH signals to grid
Line applies VGL signals on VGH lines 703b, then right side GOA exports VGL signals to grid line, at this point, grid line both sides apply respectively
VGH signals and VGL signals, if grid line, there are virtual connection, the position of virtual connection at this time heat condition occurs and burns to disconnected
It opens.Then following lighting test is carried out：Apply VGH signals on VGH lines 701b, applies VGH signals on VGH lines 703b, it
Afterwards, apply VGL signals on VGL lines 702b.
By taking scheme shown in Fig. 7 c as an example, apply VGH signals on VGL lines 702c, then left side GOA exports VGH signals to grid
Line applies VGL signals on VGL lines 704c, then right side GOA exports VGL signals to grid line, at this point, grid line both sides apply respectively
VGH signals and VGL signals, if grid line, there are virtual connection, the position of virtual connection at this time heat condition occurs and burns to disconnected
It opens.Then following lighting test is carried out：Apply VGH signals on VGH lines 701c, later, applies VGL letters on VGL lines 702c
Number, apply VGL signals on VGL lines 704c.
There is the following to need to illustrate：
(1) attached drawing of the embodiment of the present invention relate only to the present embodiments relate to structure, other structures can refer to
It is commonly designed.
(2) for clarity, in the attached drawing of embodiment for describing the present invention, the thickness in layer or region is amplified
Or reduce, i.e., these attached drawings are not drawn according to actual ratio.It is appreciated that ought such as layer, film, region or substrate etc
When element is referred to as being located at "above" or "below" another element, which " direct " can be located at "above" or "below" another element, or
Person may exist intermediary element.
(3) in the absence of conflict, the feature in the embodiment of the present invention and embodiment can be combined with each other to obtain
New embodiment.
Although disclosed herein embodiment it is as above, the content only for ease of understanding the present invention and use
Embodiment is not limited to the present invention.Technical staff in any fields of the present invention is taken off not departing from the present invention
Under the premise of the spirit and scope of dew, any modification and variation, but the present invention can be carried out in the form and details of implementation
Scope of patent protection, still should be subject to the scope of the claims as defined in the appended claims.
Claims (10)
1. a kind of array substrate, including：First signal wire and second signal line, first signal wire and the second signal line
It is disconnected from each other, and first signal wire and the second signal line are coupled to the different location of same grid line.
2. array substrate as described in claim 1, which is characterized in that first signal wire and second signal line coupling
Include to the different location of same grid line：First signal wire and the second signal line are coupled to the both ends of same grid line.
3. array substrate as described in claim 1, which is characterized in that include the between first signal wire and the grid line
Array basal plate gate driving circuit, first signal wire are coupled to the driving of the first array substrate gate driving circuit
The driving signal output end of signal input part, the first array substrate gate driving circuit is coupled to one end of the grid line,
Include the second array substrate gate driving circuit between the second signal line and the grid line, the second signal line is coupled to
The driving signal input of the second array substrate gate driving circuit, the drive of the second array substrate gate driving circuit
Dynamic signal output end is coupled to the other end of the grid line.
4. array substrate as claimed in claim 3, which is characterized in that first signal wire includes the first high level driving letter
At least one number line and the first low level drive signal line, the first high level drive signal line and first low level are driven
Dynamic signal wire is coupled to the driving signal input of the first array substrate gate driving circuit, the first high level driving
Signal wire is for input high level signal to the first array substrate gate driving circuit, first low level drive signal
For line for input low level signal to the first array substrate gate driving circuit, the second signal line includes the second high electricity
At least one flat drive signal line and the second low level drive signal line, the second high level drive signal line and described second
Low level drive signal line is coupled to the driving signal input of the second array substrate gate driving circuit, and described second is high
Level drive signal line is for input high level signal to people's array substrate gate driving circuit, second low level
Drive signal line is for input low level signal to the second array substrate gate driving circuit.
5. array substrate as described in claim 1, which is characterized in that include the between first signal wire and the grid line
Array basal plate gate driving circuit, first signal wire are coupled to the driving of the first array substrate gate driving circuit
The driving signal output end of signal input part, the first array substrate gate driving circuit is coupled to one end of the grid line,
The second signal line is coupled to the other end of the grid line by a switching circuit.
6. array substrate as claimed in claim 5, which is characterized in that first signal wire includes the first high level driving letter
At least one number line and the first low level drive signal line, the first high level drive signal line and first low level are driven
Dynamic signal wire is coupled to the driving signal input of the array substrate gate driving circuit, the first high level drive signal
Line is used for input high level signal to the first array substrate gate driving circuit, the first low level drive signal line
In input low level signal to the first array substrate gate driving circuit.
7. the array substrate as described in claim 1 to 6 is any, which is characterized in that first signal wire is connected with test weldering
Disk, the second signal line are connected with testing weld pad.
8. a kind of display device, which is characterized in that include the array substrate as described in claim 1 to 7 is any.
9. a kind of test method of array substrate as described in claim 1 to 7 is any, including：
First voltage signal is provided to first signal wire, is provided and the first voltage pickup electrode to the second signal line
The opposite second voltage signal of property.
10. test method as claimed in claim 9, which is characterized in that first voltage signal is provided to first signal wire,
After the second voltage signal opposite with the first voltage signal polarity is provided to the second signal line, further include：It carries out
Lighting test.
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| CN201810385802.7A CN108549181A (en) | 2018-04-26 | 2018-04-26 | A kind of array substrate, display device and test method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113421888A (en) * | 2021-06-18 | 2021-09-21 | 上海中航光电子有限公司 | Array substrate and display panel |
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Application publication date: 20180918 |