CN108520870A - A kind of power device packaging structure - Google Patents
A kind of power device packaging structure Download PDFInfo
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- CN108520870A CN108520870A CN201810338518.4A CN201810338518A CN108520870A CN 108520870 A CN108520870 A CN 108520870A CN 201810338518 A CN201810338518 A CN 201810338518A CN 108520870 A CN108520870 A CN 108520870A
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- electrode piece
- elastic electrode
- elastic
- power semiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a kind of power device packaging structures, the encapsulating structure includes electric pole plate, power semiconductor chips, lower electrode plate, the power semiconductor chips are between the electric pole plate and lower electrode plate, it is characterized in that, the encapsulating structure further includes the first elastic electrode piece and/or the second elastic electrode piece, the first elastic electrode piece is between the electric pole plate and the power semiconductor chips, and the second elastic electrode piece is between the lower electrode plate and the power semiconductor chips.The problem of stress concentration that parts machining tolerance range is come has been effectively relieved in the encapsulating structure, can reduce the stress of encapsulating structure chips under the premise of ensureing well conducting, effectively improve the reliability of power device package；Simultaneously because the elastic electrode piece has been wiped by elastic conduction or other materials with favorable elasticity and electric conductivity are made, moreover it is possible to improve the conductive force to chip.
Description
Technical field
The present invention relates to semiconductor applications encapsulating structure more particularly to power device packaging structures.
Background technology
In recent years, rigidity crimping is packaged into the predominant package mode for large power semiconductor device, rigidity crimping encapsulation
It is mainly in direct contact the front and the back side of chip by upper and lower two metal molybdenum sheets, reduces metal molybdenum sheet and chip electricity by applying external force
Contact resistance between pole.Rigidity crimping encapsulation is realized has good contact between device surface area and package surface area
Compact design, the device after encapsulation can realize two-sided cooling, and not have lead connection between device, can avoid lead
The problem of connecting caused heat fatigue and desoldering caused to fail, so as to avoid the problem of short circuit, the envelope occur when component failure
Dress is also convenient for series redundancy design, installation succinctly, has many advantages, such as that parasitic parameter is small.
Since semiconductor chip itself easily damages under mechanical force, meanwhile, the film in semiconductor processes
Material deforms upon under stress to cause electrology characteristic to change, such as under stress ruler occurs for a capacitance
Very little variation may result in capacitance and change, and therefore, when semiconductor chip packaging should avoid excessive stresses from being applied to core as possible
On piece.Although rigidity crimping encapsulation have the advantages that it is above-mentioned, rigidity crimping encapsulation process in the materials such as chip, electrode slice are added
Work required precision is high, and rigid material inevitably introduces machining tolerance, and the difference strained in encapsulation process will be led
Stress distribution non-uniform phenomenon is caused, so as to cause current unevenness so that individual chip is damaged because current or voltage is excessively concentrated.
Invention content
During middle power semiconductor device package for the above-mentioned prior art
The phenomenon that power that rigid material machining tolerance is brought, electricity are unevenly distributed, provides a kind of power device packaging structure, to improve encapsulation
Reliability.
In order to solve the above technical problems, the present invention provides a kind of power device packaging structure, including electric pole plate, power
Semiconductor device chip, lower electrode plate, the power semiconductor chips between the electric pole plate and lower electrode plate,
It is characterized in that, the encapsulating structure further includes the first elastic electrode piece and/or the second elastic electrode piece, the first elasticity electricity
Pole piece between the electric pole plate and the power semiconductor chips, the second elastic electrode piece be located at it is described under
Between electrode plate and the power semiconductor chips.
Optionally, the first elastic electrode piece or the second elastic electrode piece include conductive elastomer.
Optionally, the power of the surface area and contact of the first elastic electrode piece or the second elastic electrode piece
The surface area of semiconductor device chip is identical.
Optionally, the encapsulating structure includes the support construction being located at around the power semiconductor chips.
Optionally, in the state of not applying encapsulation pressure, there is seam between the support construction and the electric pole plate
Gap.
Optionally, the depth in the gap is the compressible depth of maximum less than or equal to the first elastic electrode piece.
Optionally, the thickness of the thickness of the first elastic electrode piece or the second elastic electrode piece be 0.5mm~
3mm。
Optionally, the thickness of the thickness of the first elastic electrode piece or the second elastic electrode piece is 1mm.
Optionally, the thickness of the first elastic electrode piece is more than or equal to the thickness of the second elastic electrode piece
Optionally, the support construction is rigidity supporting structure.
The power device packaging structure of the present invention, by power semiconductor chip and powering between pole piece or power half
Between conductor chip and lower electrode slice, or elasticity electricity is set between power semiconductor chip and top electrode, lower electrode simultaneously
Pole piece shifts excessive strain under the premise of ensureing sufficiently conducting by the elastic electrode piece, parts machining has been effectively relieved
The problem of stress concentration that tolerance range is come, can reduce the stress of encapsulating structure chips under the premise of ensureing well conducting, have
Effect improves the reliability of power device package；Simultaneously because the elastic electrode piece be wiped by elastic conduction or other have it is good
The material of elasticity and electric conductivity is made, moreover it is possible to improve the conductive force to chip.
Description of the drawings
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art are briefly described, it should be apparent that, in being described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, other drawings may also be obtained based on these drawings.
Fig. 1 is the encapsulating structure cross-sectional structure schematic diagram when embodiment of the present invention one does not apply encapsulation power；
Fig. 2 is the encapsulating structure cross-sectional structure schematic diagram when embodiment of the present invention one applies encapsulation power；
Fig. 3 is the encapsulating structure cross-sectional structure schematic diagram when embodiment of the present invention two applies encapsulation power；
Fig. 4 embodiment of the present invention three applies encapsulating structure cross-sectional structure schematic diagram when encapsulation power.
Specific implementation mode
Technical scheme of the present invention is clearly and completely described below in conjunction with attached drawing, it is clear that described implementation
Example is a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill
The every other embodiment that personnel are obtained without making creative work, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that term "center", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" be based on the orientation or positional relationship shown in the drawings, merely to
Convenient for the description present invention and simplify description, do not indicate or imply the indicated device or element must have a particular orientation,
With specific azimuth configuration and operation, therefore it is not considered as limiting the invention.In addition, term " first ", " second ",
" third " is used for description purposes only, and is not understood to indicate or imply relative importance.
As long as in addition, technical characteristic involved in invention described below different embodiments non-structure each other
It can be combined with each other at conflict.
Embodiment 1
Embodiment 1 provides a kind of power device packaging structure, and Fig. 1, which show the encapsulating structure and do not apply external force, to be sealed
Cross-sectional structure schematic diagram when dress, as shown in Figure 1, a kind of power device packaging structure, including power semiconductor chips
1, electric pole plate 2, lower electrode plate 3, elastic electrode piece 4 and support construction 5.
The power semiconductor chips 1 are square sheet, which is located at the electric pole plate 2
Between lower electrode plate 3, which is made frame by support construction 5 and surrounds.The power semiconductor chip can be IGBT
Vertical type semiconductor device other than chip or igbt chip, e.g., silicon-based diode, gallium nitride diode, two pole of silicon carbide
Pipe, thyristor, MOSFET etc..The electric pole plate 2 and lower electrode plate 3 can be metal materials, and can also be includes electrode figure
The substrate of shape, such as pcb board or deposited copper ceramic wafer (DBC).Reflow soldering process or other welderings may be used in the power semiconductor chip
Technique is connect to be arranged on lower electrode plate 3.
It is provided with elastic electrode piece 4 between the power semiconductor chip 1 and the electric pole plate 2, wherein the elastic electrode piece
4 can be formed in whole surface of the power semiconductor chip towards the electric pole plate, can also be that the semiconductor core is unilateral
To in the most surfaces of the electric pole plate, which can be elastic conducting material, such as elastic conduction rubber,
It can be made of other materials with favorable elasticity and electric conductivity.The elastic electrode piece 4 can be adhered to the power semiconductor
It on device, can also only be placed only on the power semiconductor, pressure and the power semiconductor pressure when passing through encapsulation
It is connected together.
For elastic electrode piece made of selection elastic conducting material, deformation quantity is bigger, corresponding elastic electrode piece
Thickness it is bigger, but correspondingly, electric conductivity can be deteriorated, therefore, in practical applications, the thickness of the elastic electrode piece according to
Actual needs takes into account the demand to deformation quantity demand and conductive capability to select suitable thickness, specifically, can select elasticity
The thickness of electrode slice is the thickness of 0.5~3mm, preferably 1mm thickness.The support construction 5 can be supported by rigid insulating material, should
Support construction has the function of being electrically insulated and fixes the chip, but also can play the role of bearing excessive strain when encapsulation.
As shown in Figure 1, in the state of not applying encapsulation pressure, there is gap between the support construction 5 and the electric pole plate；Fig. 2 institutes
It is shown as the encapsulating structure cross-sectional structure schematic diagram when embodiment of the present invention applies encapsulation power, applies pressure 6 on electric pole plate
When to the power semiconductor device package, which is compressed under outer stress, is compressed to concordant with frame
When, excessive strain is born by rigid border, does not have gap at the end of encapsulation between the support construction 5 and the electric pole plate.
Specifically, the depth in the gap can select the compressible depth of maximum less than or equal to the elastic electrode piece,
At the end of gap depth selection both ensure that encapsulation, the support construction 5, the elastic electrode piece upper surface and the top electrode 1 are tight
Contiguity is touched, and be ensure that the power semiconductor chip is preferably sealed, is protected the chip not affected by environment；The gap is deep simultaneously
The selection of degree allow elastic electrode piece thickness according to encapsulation when apply pressure and elastic electrode piece deformability,
Its electric conductivity is taken into account, is selected in a larger range, to obtain preferable power, electricity uniformly, and conductive capability
Preferably, the preferable encapsulating structure of leakproofness.
The embodiment between top electrode and power semiconductor chip by being arranged elastic electrode piece, the elastic electrode piece energy
Excessive strain is shifted under the premise of enough ensureing sufficiently conducting in pressure encapsulation process, parts machining tolerance range has been effectively relieved
The problem of stress concentration come, can reduce the stress of encapsulating structure chips, effective protection under the premise of ensureing well conducting
Chip is not damaged because of local pressure, effectively improves the reliability of power device package；Simultaneously because the elastic electrode piece be by
Elastic conduction has been wiped or other materials with favorable elasticity and electric conductivity are made, moreover it is possible to improve the conductive force to chip.
Embodiment 2
Embodiment 2 provides a kind of power device packaging structure, the embodiment 2 and embodiment 1 difference lies in：Elastic electricity
Pole piece is arranged between lower electrode plate 3 and power semiconductor chips.
Fig. 3 illustrates cross-sectional structure schematic diagram when encapsulating structure application external force is packaged, as shown in figure 3,
The encapsulating structure of power semiconductor part includes power semiconductor chips 1, electric pole plate 2, lower electrode plate 3, elastic electrode
Piece 4, support construction 5.
The elastic electrode piece 4 can be formed in the whole surface of the power semiconductor chip 1 towards the lower electrode plate,
Can be in most surfaces of the semiconductor chip towards the lower electrode plate, which can be elastic conduction material
Material, such as elastic conduction rubber, can also be made of other materials with favorable elasticity and electric conductivity.
Elastic electrode piece is arranged between the power semiconductor chip and the lower electrode plate to apply pressure to the work(
When rate semiconductor chip is packaged, buffering can be formed between the power semiconductor chip and the lower electrode plate, is avoided down
Electrode plate is to the stress rupture of the power semiconductor power semiconductor chip.
Embodiment 3
Fig. 4 is encapsulating structure cross-sectional structure schematic diagram when embodiment three applies encapsulation power, as shown in figure 4, embodiment 3
Provide a kind of power device packaging structure, the embodiment 3 and embodiment 1 difference lies in：It is partly led with power in electric pole plate 2
It is provided with the first elastic electrode piece 4 between body device chip 1, is arranged between lower electrode plate 3 and power semiconductor core, 1
There is the second elastic electrode piece 7.Wherein, the thickness of the first elastic electrode piece and the second elastic electrode piece is taken into account according to actual needs
Demand to deformation quantity demand and conductive capability selects suitable thickness.Specifically, the first elastic electrode piece and the second elasticity
Electrode slice can select the thickness of elastic electrode piece for the thickness of 0.5~3mm, preferably 1mm thickness.
Further, the thickness of the thickness of the first elastic electrode piece 4 and the second elastic electrode piece 7 can select different thickness
Degree.Such as, the thickness of the first elastic electrode piece 4 can select the thickness more than or equal to the second elastic electrode piece 7, so that encapsulation
When the first elastic electrode piece avoid larger encapsulation stress to be applied on chip with relatively large deformation quantity；Second elasticity
The thickness of electrode slice 7 is relatively small, to obtain relatively good electric conductivity, improves the electrical characteristics of device.
The encapsulating structure of the embodiment is both provided with bullet in power semiconductor chips relative to the surface of upper and lower electrode
Property electrode slice, effectively reduces the stress of the semiconductor device chip upper and lower surface in encapsulating structure, further increases encapsulating structure
Power, electric uniformity, improve package reliability.
Obviously, the above embodiments are merely examples for clarifying the description, and does not limit the embodiments.It is right
For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of variation or
It changes.There is no necessity and possibility to exhaust all the enbodiments.And it is extended from this it is obvious variation or
It changes still within the protection scope of the invention.
Claims (10)
1. a kind of power device packaging structure, including electric pole plate, power semiconductor chips, lower electrode plate, the power
Semiconductor device chip is between the electric pole plate and lower electrode plate, which is characterized in that the encapsulating structure further includes
One elastic electrode piece and/or the second elastic electrode piece, the first elastic electrode piece are located at the electric pole plate and the power
Between semiconductor device chip, the second elastic electrode piece is located at the lower electrode plate and the power semiconductor chips
Between.
2. power device packaging structure according to claim 1, it is characterised in that：The first elastic electrode piece or described
Second elastic electrode piece includes conductive elastomer.
3. power device packaging structure according to claim 1 or 2, it is characterised in that：The first elastic electrode piece or
The surface area of the second elastic electrode piece is identical as the surface area of the power semiconductor chips of contact.
4. power device packaging structure according to claim 1 or 2, it is characterised in that：The encapsulating structure includes being located at
Support construction around the power semiconductor chips.
5. power device packaging structure according to claim 4, it is characterised in that：In the state for not applying encapsulation pressure
Under, there is gap between the support construction and the electric pole plate.
6. power device packaging structure according to claim 5, it is characterised in that：The depth in the gap is to be less than or wait
In the compressible depth of maximum of the first elastic electrode piece.
7. power device packaging structure according to claim 1 or 2, it is characterised in that：The first elastic electrode piece
The thickness of thickness or the second elastic electrode piece is 0.5mm~3mm.
8. power device packaging structure according to claim 1 or 2, it is characterised in that：The first elastic electrode piece
The thickness of thickness or the second elastic electrode piece is 1mm.
9. power device packaging structure according to claim 1 or 2, it is characterised in that：The first elastic electrode piece
Thickness is more than or equal to the thickness of the second elastic electrode piece.
10. power device packaging structure according to claim 1 or 2, it is characterised in that：The support construction is that rigidity is propped up
Support structure.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810338518.4A CN108520870B (en) | 2018-04-16 | 2018-04-16 | Power device packaging structure |
| PCT/CN2018/101196 WO2019080618A1 (en) | 2017-10-24 | 2018-08-17 | Insulated gate bipolar transistor structure and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810338518.4A CN108520870B (en) | 2018-04-16 | 2018-04-16 | Power device packaging structure |
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| Publication Number | Publication Date |
|---|---|
| CN108520870A true CN108520870A (en) | 2018-09-11 |
| CN108520870B CN108520870B (en) | 2020-05-15 |
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ID=63429381
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810338518.4A Active CN108520870B (en) | 2017-10-24 | 2018-04-16 | Power device packaging structure |
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| Country | Link |
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| CN (1) | CN108520870B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110556349A (en) * | 2019-09-29 | 2019-12-10 | 全球能源互联网研究院有限公司 | Power type semiconductor device packaging structure |
| CN111406788A (en) * | 2020-04-24 | 2020-07-14 | 珠海格力电器股份有限公司 | Thawing device and refrigerator |
| WO2021056604A1 (en) * | 2019-09-29 | 2021-04-01 | 全球能源互联网研究院有限公司 | Preparation process of power type semiconductor device package structure |
| CN112992795A (en) * | 2019-12-17 | 2021-06-18 | 株洲中车时代半导体有限公司 | Crimping type IGBT sub-module structure and crimping type IGBT device |
| CN113140524A (en) * | 2021-03-31 | 2021-07-20 | 南瑞联研半导体有限责任公司 | Semiconductor module structure |
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| CN107731696A (en) * | 2017-09-13 | 2018-02-23 | 全球能源互联网研究院有限公司 | A kind of power chip method for packing and structure |
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| CN103563075A (en) * | 2011-06-16 | 2014-02-05 | 富士电机株式会社 | Semiconductor unit and semiconductor device using same |
| CN103380495A (en) * | 2012-01-11 | 2013-10-30 | 松下电器产业株式会社 | Pressure contact type semiconductor device and method for fabricating same |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110556349A (en) * | 2019-09-29 | 2019-12-10 | 全球能源互联网研究院有限公司 | Power type semiconductor device packaging structure |
| WO2021056604A1 (en) * | 2019-09-29 | 2021-04-01 | 全球能源互联网研究院有限公司 | Preparation process of power type semiconductor device package structure |
| CN112992795A (en) * | 2019-12-17 | 2021-06-18 | 株洲中车时代半导体有限公司 | Crimping type IGBT sub-module structure and crimping type IGBT device |
| CN112992795B (en) * | 2019-12-17 | 2024-04-19 | 株洲中车时代半导体有限公司 | Crimping type IGBT sub-module structure and crimping type IGBT device |
| CN111406788A (en) * | 2020-04-24 | 2020-07-14 | 珠海格力电器股份有限公司 | Thawing device and refrigerator |
| CN113140524A (en) * | 2021-03-31 | 2021-07-20 | 南瑞联研半导体有限责任公司 | Semiconductor module structure |
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| CN108520870B (en) | 2020-05-15 |
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