CN108512207B - Electrostatic protection circuit - Google Patents
Electrostatic protection circuit Download PDFInfo
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- CN108512207B CN108512207B CN201810346902.9A CN201810346902A CN108512207B CN 108512207 B CN108512207 B CN 108512207B CN 201810346902 A CN201810346902 A CN 201810346902A CN 108512207 B CN108512207 B CN 108512207B
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- 230000008878 coupling Effects 0.000 claims abstract description 12
- 238000010168 coupling process Methods 0.000 claims abstract description 12
- 238000005859 coupling reaction Methods 0.000 claims abstract description 12
- 230000003071 parasitic effect Effects 0.000 claims abstract description 7
- 230000009471 action Effects 0.000 claims abstract description 6
- 230000005669 field effect Effects 0.000 claims description 9
- 230000000740 bleeding effect Effects 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 abstract description 16
- 102000004213 Neuropilin-2 Human genes 0.000 description 12
- 108090000770 Neuropilin-2 Proteins 0.000 description 12
- 238000010586 diagram Methods 0.000 description 9
- 102000004207 Neuropilin-1 Human genes 0.000 description 7
- 108090000772 Neuropilin-1 Proteins 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 238000007599 discharging Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/041—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage using a short-circuiting device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Disclosed is an electrostatic protection circuit including: the discharge unit is connected with the signal end and discharges energy to the signal end according to the trigger signal; a trigger unit for providing the trigger signal; the trigger unit comprises a first transistor, the first transistor is conducted under the action of parasitic capacitance coupling between a first end and a control end of the first transistor to provide starting current, the first end of the first transistor is connected with the signal end, and when the first transistor is conducted, the trigger unit provides the trigger signal according to the starting current. When the device is designed, a mask layer arranged aiming at the high-voltage capacitor can be omitted, so that the number of masks is reduced, the design cost of the circuit is further reduced, and the design efficiency of the circuit is improved.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to an electrostatic protection circuit.
Background
The electrostatic Discharge (ESD) phenomenon refers to a Discharge and transfer phenomenon of electric charges between a chip and an external object. ESD events occur when a large amount of charge is discharged in a short time, thereby generating energy much higher than the endurance capacity of the chip, and thus may cause the chip to temporarily fail or even permanently break down in its function. In the chip manufacturing process, an anti-static bracelet or an anti-static clothing can be adopted to reduce the damage of the ESD phenomenon. After the chip is manufactured, because the difference of the using environment of the chip is large, an ESD phenomenon is easily generated between the chip and an external object, so that the chip is influenced by electrostatic discharge. Therefore, an electrostatic protection circuit is generally provided in the chip to provide an electrostatic discharge path, so that the chip itself has an electrostatic protection function, thereby improving reliability and a service life of the chip.
Modern electronic products (such as smart phones, notebook computers, tablet computers, LED displays, and the like) usually include high-speed data ports (such as HDMI, USB, DVI, and the like) mounted on a Printed Circuit Board (PCB), and these high-speed data ports are widely protected by electrostatic protection circuits. The electrostatic protection circuit can be designed as a discrete device or can be directly integrated in the chip. Fig. 1 shows a schematic diagram of a prior art ESD protection circuit, when an ESD pulse arrives, a transistor N1 is triggered by a resistor R1 and a capacitor C1, when a transistor N1 is turned on, a current flows through the resistor R2 to trigger a transistor N2, and finally, a transistor N2 is used to discharge most of ESD energy. In order to effectively discharge the ESD pulse, the RC time constant is usually designed to be 10ns-10ms, so the capacitor C1 needs to be set as a high-voltage capacitor, that is, a separate mask layer is needed to form the capacitor C1 during device design, which greatly increases the design cost and reduces the chip design efficiency.
Disclosure of Invention
In view of the above, an objective of the present invention is to provide an electrostatic protection circuit, which further reduces the design cost of the circuit and improves the design efficiency of the circuit.
According to the present invention, there is provided an electrostatic protection circuit comprising: the release unit is connected with the signal end and used for releasing energy to the signal end according to the trigger signal; a trigger unit for providing the trigger signal; the trigger unit comprises a first transistor, the first transistor is conducted under the action of parasitic capacitance coupling between a first end and a control end of the first transistor to provide starting current, the first end of the first transistor is connected with the signal end, and when the first transistor is conducted, the trigger unit provides the trigger signal according to the starting current.
Preferably, the trigger unit further includes a first resistor connected between the second terminal and the control terminal of the first transistor.
Preferably, the trigger unit further includes: the 1 st to N-stage trigger circuits, the 1 st stage trigger circuit generates the 1 st stage output current according to the starting current, the 2 nd to N-stage trigger circuits generate the 2 nd to N-stage output currents according to the 1 st to N-1 stage output currents respectively, and N is a non-zero natural number; and a conversion circuit generating the trigger signal according to the output current of the nth stage.
Preferably, at least one stage of the trigger circuit is used for amplifying the starting current or the output current of the trigger circuit of the previous stage.
Preferably, each stage of the flip-flop circuit includes: the input end receives the starting current or the corresponding output current; the output end provides the output current of the current stage; a control end of the second transistor is connected with the input end, a first end of the second transistor is connected with the signal end, and a second end of the second transistor is connected with the output end; and a second resistor connected between the input terminal and the output terminal.
Preferably, the conversion circuit includes a third resistor, a first terminal of the third resistor is connected to the output terminal of the nth stage trigger circuit to provide the trigger signal, and a second terminal of the third resistor receives a reference ground voltage.
Preferably, the bleeding unit includes a third transistor, a first terminal of the third transistor is connected to the signal terminal, a second terminal of the third transistor receives the reference ground voltage, and a control terminal of the third transistor receives the trigger signal.
Preferably, the electrostatic protection circuit further includes a diode, an anode of the diode is connected to the control terminal of the third transistor, and a cathode of the diode is connected to the first terminal of the third transistor.
Preferably, the first transistor is a triode and/or a field effect transistor.
Preferably, the second transistor is a triode and/or a field effect transistor.
Preferably, the signal terminal is used for receiving a high level voltage.
The electrostatic protection circuit provided by the invention has the beneficial effects that: the ESD circuit comprises a trigger unit, a signal end, a base electrode, a field effect transistor and a coupling capacitor, wherein the coupling capacitor between the collector electrode and the base electrode of the triode or between the drain electrode and the grid electrode of the field effect transistor is used for replacing a high-voltage capacitor to generate starting current, the trigger unit generates a trigger signal according to the starting current, and when the trigger signal is effective, the discharge unit is started to form an energy discharge path from the signal end to the ground so as to discharge ESD energy. The electrostatic protection circuit provided by the invention can be quickly started when ESD pulse occurs at the signal end, so that the internal circuit of the chip is prevented from being damaged. Meanwhile, the high-voltage capacitor is replaced by the coupling capacitor between the collector and the base of the triode or between the drain and the grid of the field effect transistor, and a mask layer arranged aiming at the high-voltage capacitor can be omitted during device design, so that the number of masks is reduced, the design cost of the circuit is further reduced, and the design efficiency of the circuit is improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a circuit schematic of a prior art electrostatic protection circuit.
Fig. 2 is a schematic structural diagram of an electrostatic protection circuit according to an embodiment of the present invention.
Fig. 3 shows a circuit diagram of an electrostatic protection circuit according to a first embodiment of the present invention.
Fig. 4 shows a circuit diagram of an electrostatic protection circuit according to a second embodiment of the present invention.
Fig. 5 shows a circuit diagram of an electrostatic protection circuit according to a third embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
It should be understood that in the following description, a "circuit" refers to a conductive loop formed by at least one element or sub-circuit through an electrical or electromagnetic connection. When an element or circuit is "connected to" another element or element/circuit is "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that no intervening elements are present between the two.
Fig. 2 is a schematic structural diagram of an electrostatic protection circuit according to an embodiment of the present invention. As shown in fig. 2, the electrostatic protection circuit 200 includes a trigger unit 230 and a bleeding unit 220 connected between the signal terminal 210 and ground.
Specifically, the trigger unit 230 includes at least one stage of a trigger circuit 231, a conversion circuit 232, and a first transistor 233. As shown in fig. 2, the first transistor 233 has a first terminal connected to the signal terminal 210 and a second terminal connected to an input terminal of the flip-flop circuit 231 connected thereto. The first transistor 233 is turned on by a parasitic capacitive coupling between a first terminal and a control terminal thereof to supply a start-up current to the trigger circuit 231. The trigger unit 230 further includes a first resistor R1, and the first resistor R1 is connected between the second terminal and the control terminal of the first transistor 233.
In addition, the trigger unit 230 includes stage 1 trigger circuits 231 to nth trigger circuits 231, N being a non-zero natural number. Each stage of the trigger circuit 231 includes an input terminal for receiving the start-up current or the output current of the previous stage of the trigger circuit 231, and an output terminal for providing the output current of the current stage. For example, the input terminal of the 1 st stage trigger circuit 231 receives the start current to generate the output current of the 1 st stage according to the start current, and the 2 nd to N th stage trigger circuits 231 generate the output currents of the 2 nd to N th stages according to the output currents of the 1 st to N-1 stage trigger circuits 231, respectively. The converting circuit 232 is connected to the nth stage trigger circuit 231, generates a trigger signal according to the output current of the nth stage, and the bleeding unit 220 bleeds energy from the signal terminal 210 according to the trigger signal.
In addition, in the embodiment of the present invention, the specific number N of stages of the trigger circuit 231 included in the trigger unit 230 is determined according to the starting current output by the first transistor and the starting voltage required by the bleeder unit, and when N is higher, the circuit is more complex, which increases the layout area and increases the cost, so that a person skilled in the art can select the number N of stages of the trigger circuit 231 included in the trigger unit 230 according to the specific circuit condition. In some implementations, the number of stages N is preferably 1 or 2.
In the following embodiments, the principle of the electrostatic protection circuit according to the present invention will be described by taking N equal to 1 as an example.
Fig. 3 shows a circuit diagram of an electrostatic protection circuit according to a first embodiment of the present invention. As shown in fig. 3, the first transistor 233 may be implemented by a transistor NPN1, a collector of the transistor NPN1 is connected to the signal terminal 210, a base is connected to a first terminal of the first resistor R1, an emitter is connected to a second terminal of the first resistor R1, and a node between the emitter of the transistor NPN1 and the first resistor R1 is used to provide a start-up current.
The trigger circuit 231 includes a transistor NPN2 and a second resistor R2, a collector of the transistor NPN2 is connected to the signal terminal 210, a base is connected to a node between an emitter of the transistor NPN1 and the first resistor R1 to receive the start-up current, and the emitter is used for providing the output current of the stage. A second resistor R2 is connected between the base and emitter of the transistor NPN 2.
In addition, the switching circuit 232 in fig. 1 may be implemented by a third resistor R3, a first end of the third resistor R3 is connected to a node between the emitter of the transistor NPN2 and the second resistor R2, and a second end of the third resistor R3 is grounded.
As shown in fig. 3, the bleeder unit 220 comprises a third transistor N3, a first terminal of the third transistor N3 is connected to the signal terminal 210, a second terminal thereof is grounded, and a control terminal thereof is connected to a first terminal of a third resistor for receiving the trigger signal.
When an ESD pulse occurs at the signal terminal 210, the voltage between the base and the emitter of the transistor NPN1 is raised by the first resistor R1 due to the parasitic capacitance coupling between the collector and the base of the transistor NPN1, so that the transistor NPN1 is turned on and provides a start-up current. The start-up current flows through the second resistor R2 in the trigger circuit 231, so that the voltage between the base and the emitter of the transistor NPN2 is higher than the turn-on voltage of the transistor NPN2, and the transistor NPN2 turns on and generates the output current of this stage. The output current provided by the transistor NPN2 flows through the third resistor R3, thereby generating a trigger signal at the first terminal of the third resistor R3, which raises the voltage of the control terminal of the third transistor N3, so that the third transistor N3 is turned on to form an energy discharge path from the signal terminal 210 to ground, thereby discharging the ESD energy from the signal terminal 210.
In addition, a diode D1 may be further included between the control terminal and the first terminal of the third transistor N3, an anode of the diode D1 is connected to the control terminal of the third transistor N3, and a cathode is connected to the first terminal of the third transistor N3, so as to prevent an overvoltage between the first terminal of the third transistor N1 and the ground.
Specifically, the third transistor N3 may be implemented by an N-type MOS transistor, where a control terminal of the third transistor N3 is a gate of the MOS transistor, a first terminal is a drain of the MOS transistor, and a second terminal is a source of the MOS transistor.
Fig. 4 is a schematic circuit diagram of an electrostatic protection circuit according to a second embodiment of the present invention, which is different from the electrostatic protection circuit according to the first embodiment shown in fig. 3 in that: the first transistor 233 is an N-type fet N1, a drain of the fet N1 is connected to the signal terminal 210, a gate thereof is connected to a first terminal of the first resistor R1, and a source thereof is connected to a second terminal of the first resistor R1 for providing a start-up current.
In addition, the structures and connection relations of the trigger circuit 231, the converting circuit 232, the diode D1 and the bleeding unit 220 are the same as those of the first embodiment shown in fig. 3, and are not described herein again.
In the second embodiment as shown in fig. 4, when the ESD pulse occurs at the signal terminal 210, the voltage between the gate and the source of the fet N1 is raised by the first resistor R1 due to the parasitic capacitance coupling between the drain and the gate of the fet N1, so that the fet N1 is turned on and provides the starting current. Then, a start current flows through the second resistor R2, so that the voltage between the base and the emitter of the transistor NPN2 is higher than the turn-on voltage of the transistor NPN2, and the transistor NPN2 turns on and provides the output current of the present stage. The output current provided by the transistor NPN2 flows through the third resistor R3, thereby generating a trigger signal at the first end of the third resistor R3, which raises the voltage of the gate of the third transistor N3, so that the third transistor N3 is turned on to form an energy discharge path from the signal terminal 210 to ground, thereby discharging the ESD energy from the signal terminal 210.
Fig. 5 shows a circuit schematic diagram of an electrostatic protection circuit according to a third embodiment of the present invention, and compared with the second embodiment shown in fig. 4, the electrostatic protection circuit according to the third embodiment of the present invention is different in that the trigger circuit 231 includes an N-type fet N2 and a second resistor R2, a first end and a second end of the second resistor R2 are respectively connected to the gate and the source of the fet N2, the drain of the fet N2 is connected to the signal terminal 210, a first end of the second resistor R2 is connected to a second end of the first resistor R1 to receive the start current, so that the second resistor R2 can provide the gate-source voltage of the fet N2 to control the on and off of the fet N2 according to the start current, and the source of the fet N2 provides the output current of this stage.
In addition, the structures and connection relations of the first transistor 233, the first resistor R1, the converting circuit 232, the diode D1 and the bleeding unit 220 are the same as those of the second embodiment shown in fig. 4, and are not repeated herein.
In the third embodiment as shown in fig. 5, when the ESD pulse occurs at the signal terminal 210, the gate-source voltage of the fet N1 is raised by the first resistor R1 due to the parasitic capacitance coupling between the drain and the gate of the fet N1, so that the fet N1 is turned on and generates a start-up current. The starting current flows through the second resistor R2, so that the gate-source voltage of the fet N2 is raised to the turn-on voltage of the fet N2, and the fet N2 turns on and generates the output current of the stage. The output current provided by the fet N2 flows through the third resistor R3, thereby generating a trigger signal at the first end of the third resistor R3, which raises the gate voltage of the third transistor N3, so that the third transistor N3 is turned on to form an energy discharge path from the signal terminal 210 to ground, thereby discharging the ESD energy from the signal terminal 210.
In summary, the ESD protection circuit provided by the present invention utilizes a coupling capacitor between a collector and a base of a triode or a drain and a gate of a field effect transistor to replace a high voltage capacitor to generate a start current, the trigger unit generates a trigger signal according to the start current, and when the trigger signal is valid, the discharge unit is turned on to form an energy discharge path from a signal terminal to ground, so as to discharge ESD energy. The electrostatic protection circuit provided by the invention can be quickly started when ESD pulse occurs at the signal end, so that the internal circuit of the chip is prevented from being damaged. Meanwhile, the high-voltage capacitor is replaced by the coupling capacitor between the collector and the base of the triode or between the drain and the grid of the field effect transistor, and a mask layer arranged aiming at the high-voltage capacitor can be omitted during device design, so that the number of masks is reduced, the design cost of the circuit is further reduced, and the design efficiency of the circuit is improved.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (11)
1. An electrostatic protection circuit, comprising:
the release unit is connected with the signal end and used for releasing energy to the signal end according to the trigger signal;
a trigger unit for providing the trigger signal;
the trigger unit comprises a first transistor, the first transistor is conducted under the action of parasitic capacitance coupling between a first end and a control end of the first transistor to provide starting current, and the first end of the first transistor is connected with the signal end;
the trigger unit further comprises at least one stage of trigger circuit and a conversion circuit, wherein the at least one stage of trigger circuit is connected with the second end of the first transistor to receive the starting current and is used for amplifying the starting current and outputting the amplified current; and the conversion circuit generates the corresponding trigger signal based on the current output by the at least one stage of trigger circuit so as to start the bleeder unit.
2. The esd protection circuit of claim 1, wherein the trigger unit further comprises a first resistor connected between the second terminal and the control terminal of the first transistor.
3. The esd protection circuit of claim 1, wherein the at least one stage of trigger circuit comprises:
the 1 st to N-stage trigger circuits, the 1 st stage trigger circuit generating the 1 st stage output current according to the starting current, the 2 nd to N-stage trigger circuits generating the 2 nd to N-stage output currents according to the 1 st to N-1 stage output currents, N is a non-zero natural number,
wherein the conversion circuit generates the trigger signal according to the output current of the Nth stage.
4. The ESD protection circuit of claim 3 wherein at least one stage of the trigger circuit is configured to amplify the start-up current or the output current of a previous stage of the trigger circuit.
5. The electrostatic protection circuit according to claim 3, wherein each stage of the trigger circuit comprises:
the input end receives the starting current or the corresponding output current;
the output end provides the output current of the current stage;
a control end of the second transistor is connected with the input end, a first end of the second transistor is connected with the signal end, and a second end of the second transistor is connected with the output end; and
a second resistor connected between the input terminal and the output terminal.
6. The ESD protection circuit of claim 5 wherein the switching circuit comprises a third resistor, a first terminal of the third resistor is connected to the output terminal of the Nth stage trigger circuit to provide the trigger signal, and a second terminal of the third resistor receives a reference ground voltage.
7. The ESD protection circuit of claim 1, wherein the bleeding unit comprises a third transistor, a first terminal of the third transistor is connected to the signal terminal, a second terminal of the third transistor receives a reference ground voltage, and a control terminal of the third transistor receives the trigger signal.
8. The esd protection circuit of claim 7, further comprising a diode, an anode of the diode being coupled to the control terminal of the third transistor, and a cathode of the diode being coupled to the first terminal of the third transistor.
9. The ESD protection circuit of claim 1 wherein the first transistor is a triode and/or a field effect transistor.
10. The ESD protection circuit of claim 5 wherein the second transistor is a triode and/or a field effect transistor.
11. The ESD protection circuit of claim 1 wherein the signal terminal is configured to receive a high level voltage.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810346902.9A CN108512207B (en) | 2018-04-18 | 2018-04-18 | Electrostatic protection circuit |
| TW108106307A TWI696258B (en) | 2018-04-18 | 2019-02-25 | Electrostatic protection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810346902.9A CN108512207B (en) | 2018-04-18 | 2018-04-18 | Electrostatic protection circuit |
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| Publication Number | Publication Date |
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| CN108512207A CN108512207A (en) | 2018-09-07 |
| CN108512207B true CN108512207B (en) | 2020-01-24 |
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| CN201810346902.9A Active CN108512207B (en) | 2018-04-18 | 2018-04-18 | Electrostatic protection circuit |
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| CN (1) | CN108512207B (en) |
| TW (1) | TWI696258B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112968437B (en) * | 2021-04-01 | 2022-07-08 | 长鑫存储技术有限公司 | Electrostatic protection circuit and electrostatic protection network of chip |
| CN112865058A (en) * | 2021-04-12 | 2021-05-28 | 上海传泰电子科技有限公司 | High-voltage peak bleeder circuit |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2005235947A (en) * | 2004-02-18 | 2005-09-02 | Fujitsu Ltd | Electrostatic discharge protective circuit |
| CN201332098Y (en) * | 2008-12-08 | 2009-10-21 | 惠州市正源微电子有限公司 | ESD protecting circuit of depletion type pHEMT chips |
| CN102025135B (en) * | 2009-09-17 | 2013-08-14 | 上海宏力半导体制造有限公司 | ESD protective device |
| US8804290B2 (en) * | 2012-01-17 | 2014-08-12 | Texas Instruments Incorporated | Electrostatic discharge protection circuit having buffer stage FET with thicker gate oxide than common-source FET |
| CN107565537B (en) * | 2017-09-29 | 2019-09-20 | 广州慧智微电子有限公司 | A kind of esd protection circuit and method |
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2018
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| Publication number | Publication date |
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| CN108512207A (en) | 2018-09-07 |
| TW201944572A (en) | 2019-11-16 |
| TWI696258B (en) | 2020-06-11 |
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Effective date of registration: 20200305 Address after: 210042 302, Xuanwu Road, 7, Xuanwu Road, Xuanwu District, Nanjing, Jiangsu, China, 7 Patentee after: Silergy Semiconductor Technology (Hangzhou) Ltd. Address before: 310012 Wensanlu Road, Hangzhou Province, No. 90 East Software Park, science and technology building A1501 Patentee before: Silergy Semiconductor Technology (Hangzhou) Ltd. |
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Address after: 210042 302, Xuanwu Road, 7, Xuanwu Road, Xuanwu District, Nanjing, Jiangsu, China, 7 Patentee after: Nanjing Sili Microelectronics Technology Co., Ltd Address before: 210042 302, Xuanwu Road, 7, Xuanwu Road, Xuanwu District, Nanjing, Jiangsu, China, 7 Patentee before: Silergy Semiconductor Technology (Hangzhou) Ltd. |