CN108511332A - 半导体基材直接结合的方法 - Google Patents

半导体基材直接结合的方法 Download PDF

Info

Publication number
CN108511332A
CN108511332A CN201810167581.6A CN201810167581A CN108511332A CN 108511332 A CN108511332 A CN 108511332A CN 201810167581 A CN201810167581 A CN 201810167581A CN 108511332 A CN108511332 A CN 108511332A
Authority
CN
China
Prior art keywords
plasma
base material
binder course
sicn
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201810167581.6A
Other languages
English (en)
Other versions
CN108511332B (zh
Inventor
彭澜
金淳旭
E·贝内
G·P·拜尔
E·斯利克斯
R·米勒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Interuniversitair Microelektronica Centrum vzw IMEC
Original Assignee
Interuniversitair Microelektronica Centrum vzw IMEC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Interuniversitair Microelektronica Centrum vzw IMEC filed Critical Interuniversitair Microelektronica Centrum vzw IMEC
Publication of CN108511332A publication Critical patent/CN108511332A/zh
Application granted granted Critical
Publication of CN108511332B publication Critical patent/CN108511332B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185Joining of semiconductor bodies for junction formation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185Joining of semiconductor bodies for junction formation
    • H01L21/187Joining of semiconductor bodies for junction formation by direct bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32Processing objects by plasma generation
    • H01J2237/33Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334Etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082Radio frequency generated discharge
    • H01J37/32091Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082Radio frequency generated discharge
    • H01J37/321Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29075Plural core members
    • H01L2224/2908Plural core members being stacked
    • H01L2224/29082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29186Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/29187Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009Pre-treatment of the bonding area
    • H01L2224/8001Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H01L2224/80013Plasma cleaning
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80909Post-treatment of the bonding area
    • H01L2224/80948Thermal treatments, e.g. annealing, controlled cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009Pre-treatment of the layer connector or the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009Pre-treatment of the layer connector or the bonding area
    • H01L2224/8301Cleaning the layer connector, e.g. oxide removal step, desmearing
    • H01L2224/83011Chemical cleaning, e.g. etching, flux
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009Pre-treatment of the layer connector or the bonding area
    • H01L2224/83022Cleaning the bonding area, e.g. oxide removal step, desmearing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/83895Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/83896Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909Post-treatment of the layer connector or bonding area
    • H01L2224/83948Thermal treatments, e.g. annealing, controlled cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83986Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/045Carbides composed of metals from groups of the periodic table
    • H01L2924/046414th Group
    • H01L2924/04642SiC
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/059Being combinations of any of the materials from the groups H01L2924/042 - H01L2924/0584, e.g. oxynitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20Parameters
    • H01L2924/201Temperature ranges
    • H01L2924/20106Temperature range 200 C=<T<250 C, 473.15 K =<T < 523.15K
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20Parameters
    • H01L2924/201Temperature ranges
    • H01L2924/20107Temperature range 250 C=<T<300 C, 523.15K =<T< 573.15K

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

一种使第一基材与第二基材直接结合的方法,所述第一基材和第二基材包含电介质结合层,其中所述结合通过使电介质结合层互相接触形成基材组件并对该组件进行结合后退火来进行,其中两个结合层在结合之前都进行预处理,所述预处理包括按照所述的顺序进行的以下步骤:在惰性气体等离子体中的第一等离子体活化步骤,在氧等离子体中的第二等离子体活化步骤,湿表面处理,包括水洗步骤或包括暴露于含水环境,其中,两个基材上的两个电介质结合层是两个SiCO层或两个SiCN层或两个SiC层。

Description

半导体基材直接结合的方法
发明领域
本发明涉及直接结合方法,其中一个半导体基材与另一个半导体基材通过在接触表面之间形成化学键而结合。
背景技术
晶片级直接结合(通常称为'晶片-晶片(wafer to wafer)'结合)包括两个半导体晶片(通常是具有电介质结合层的硅晶片)室温下的对齐和接触,然后进行退火步骤,在该步骤期间在结合层之间形成化学键。
目前的晶片-晶片结合实践主要分为两类:
o两个晶片的表面都是毯式、平坦的未图案化电介质结合层,例如氧化硅、氮化硅或硅-碳-氧化物(低k电介质)层。
o两个晶片的表面都是平坦的图案化的电介质/金属层(称为混杂晶片结合)。主要的区域部分被电介质材料覆盖,而其它区域是金属性的,主要形成接触垫和金属线。通过上述相同的机理进行电介质区域之间的结合。金属区域重叠的位置可用于实现晶片之间的电接触。
对于这两类,在结合之前都可使用化学机械抛光(CMP)降低电介质层的粗糙度。进行表面处理,例如等离子体处理和超声或其它清洁技术。所需的结合后退火温度通常高于400℃,以实现所需的结合强度。为了降低结合方法的热预算,希望在较低的温度下获得高强度结合。这在存储器装置领域中特别重要。
在'管芯-晶片(die to wafer)'结合方法中面临同样的问题,在该方法中,半导体芯片通过直接结合与载体晶片结合。在后一个领域中,已经知道使用硅碳氮化物(SiCN)作为电介质结合层。可以参考US2013/0207268。但是,所引用的文献没有详细描述结合方法,对于可以实施的退火温度也没有给出任何信息。US2010/0211849描述了在晶片-晶片直接结合方法中SiCN作为'结合辅助膜(bonding aid film)'。但是,该方法在热预算(结合后退火温度是400℃)方面还有进一步改善的空间。
已经描述了在结合之前对电介质结合表面的各种等离子体处理。已经知道基于氮的等离子体预处理可以改善结合强度。还描述了一系列的等离子体处理。例如,文献US-A-2005/0173057描述了通过氧气下的反应性离子蚀刻(RIE)处理、然后氮气下的微波等离子体处理的对Si或SiO2表面的一系列的处理。对于特定的结合层,例如SiCN层,这些处理是不够的或不合适的,需要改进的方法来提高结合强度。
发明内容
本发明的目的在于提供一种通过基材表面上的电介质结合层之间的直接结合来结合基材的方法,其中相比于现有技术结合强度得到改善。本发明涉及依据所附权利要求的方法。
本发明的方法是一种使第一基材与第二基材直接结合的方法,所述第一基材和第二基材包含电介质结合层,其中所述结合通过使电介质结合层互相接触形成基材组件并对该组件进行结合后退火来进行,其中两个结合层在结合之前都进行预处理,该预处理包括按照所述的顺序进行的以下步骤:
·在惰性气体等离子体中的第一等离子体活化步骤,
·在氧等离子体中的第二等离子体活化步骤,
·湿表面处理,包括水洗步骤或包括暴露于含水环境,
其中,两个基材上的电介质结合层是两个SiCO层或两个SiCN层或两个SiC层。
依据一个实施方式,所述一个或两个等离子体活化步骤在电容耦合等离子体的等离子体反应器中进行。或者,所述一个或两个等离子体活化步骤可以在感应耦合等离子体的等离子体反应器中进行。依据一个优选的实施方式,在基材与等离子体之间没有主动施加DC偏置电压。
依据一个实施方式,两个等离子体活化步骤都在以下条件下进行:
·通过射频电源产生等离子体,
·压力在1.33-133.3Pa(10和1000毫托(mTorr))之间,
·RF频率在100KHz-300MHz之间,
·RF功率在50W-300W之间,
·温度低于60℃。
更优选地,两个等离子体活化步骤的RF频率都在100KH-1MHz之间。
结合后退火温度优选低于400℃,更优选在200℃-250℃之间。惰性气体可以是氩气。依据一个实施方式,湿表面处理在低于300秒的时间段内进行。该方法还可包括在第一和第二等离子体活化步骤之间的中间清洁步骤。
附图简要说明
图1比较了通过本发明方法得到的测试结果与通过现有的结合表面处理得到的结果。
发明详述
依据本发明的优选的实施方式,在结合之前对两个基片(例如是具有电介质结合层的硅晶片)进行以下的预处理步骤:
1.氩气等离子体活化,
2.任选的中间清洁步骤,优选包括至少一个水洗步骤,优选用去离子水进行,
3.氧等离子体活化,
4.湿表面处理,包括用水(优选去离子水)洗涤。或者,湿处理可包括使经过等离子体处理的表面暴露于含H2O的环境。
这些步骤按照上述顺序进行。第一步骤中的氩气可被任何其它惰性气体代替。通过相继的等离子体活化以及随后的湿表面处理可以得到优越的结合强度,本说明书中的实验数据将进一步说明这一点。
在本文中,等离子体活化表示这样一种工艺,在该工艺中基材的表面通过等离子体离子的物理溅射而被处理,但是没有明显除去基材本身的材料,即没有蚀刻基材的表面。换言之,基材没有被反应性离子蚀刻(RIE)处理。通过等离子体离子的溅射,活化步骤被设置为除去与表面化学结合的化合物(例如烃),但是不明显除去表面本身的材料。
两个等离子体步骤中的等离子体活化都可以在电容耦合等离子体(CCP)的等离子体反应器中进行,该反应器包括一组电极,其中第一电极是位于反应室内并与射频(RF)电压源连接的平面电极,第二电极是接地电极。形成反应室的外壳优选也是接地的。第二电极可通过所述形成反应室的外壳形成。要进行预处理的基材被安装在下电极上(通常安装在设计用于保持基材的卡盘上),并暴露于在电极之间通过RF电源产生的等离子体。为了实现本发明方法中的氩气或氧等离子体活化步骤,通过在反应室内产生真空并且对反应室分别提供氩气或氧气来生成等离子体。在RF功率和持续供应的Ar或O的影响下,在电极之间产生等离子体并保持。等离子体密度取决于RF功率(功率越高,密度越高)。
使用电容耦合等离子体反应器能够实现上述等离子体离子物理溅射到晶片表面而无反应性离子蚀刻。但是,所述一个或两个等离子体步骤也可以在感应耦合等离子体反应器中进行,对工艺参数进行设置以得到上述意义的表面活化。在ICP反应器中,在置于反应室外的电极之间通过RF电源产生Ar或O基等离子体,然后将这些等离子体引入待处理的基材被置于其中的反应室中。依据优选的实施方式,不在微波等离子体反应器中进行等离子体步骤。
在CCP反应器中,来自等离子体的离子在等离子体和RF供电电极之间的DC偏置电压的作用下加速飞向基材。DC偏置电压是等离子形成的结果,并受RF频率的影响。也可以通过调整RF供电电极和RF电源之间连接的网络主动将DC偏置控制在所需的值。在ICP的情况中,电容供电电极可用于控制晶片表面的偏压。但是,依据一个优选的实施方式,既不主动施加也不主动控制等离子体与待处理的基材之间的DC偏置电压。
依据优选的实施方式,RF频率最大为300MHz。更优选的是,频率在100KHz-1MHz之间。而且,RF功率优选较低,优选在50-300W之间。各等离子体步骤的处理持续时间保持较短,优选最长为1分钟。等离子体步骤在低温下进行,例如15℃-25℃,优选不高于60℃。下表总结了可在本发明方法的两个等离子体步骤中实施的等离子体参数(在CCP或ICP反应器中进行)的优选范围:
压力 10-1000毫托(1.33-133.3Pa)
RF功率 50-300W
RF频率 100kHz–300MHz
工艺时间 10-60秒
温度 <60℃
在本发明的方法中,结合层由硅碳氧化物或硅碳氮化物或碳化硅(在下文中简写为SiCO或SiCN或SiC)形成,即在两个基材上都设置SiCO或SiCN或SiC的层,通过SiCO-SiCO键或SiCN-SiCN键建立直接结合。在本文中,SiCO定义为化合物SiCyOz,其中y为0.4-1.2,z为0.2-1.0。在本文中,SiCN用通式SiCyNz定义,其中y为0.7-1.1,z为0.1-0.4。术语SiCN还包括SiCyNz:H的层,其中'H'表示与SiCN分子连接的氢原子。这可能是沉积SiCN层方法中使用的前体的结果。在本文中,SiC定义为化合物SiCy,其中y为0.4-1.4。
电介质结合层的厚度优选为10nm-1微米,更优选在50nm-150nm之间。可以以本领域已知的任何方式将电介质层沉积在基材上。它们可以直接沉积在半导体晶片上,或者沉积在之前已经沉积在晶片上的其它层上。在本发明的相继等离子体处理之前,优选通过合适的平坦化处理(优选通过化学机械抛光)对电介质结合层进行平坦化。依据已知的方法进行平坦化,并且进行到适于进行直接结合技术的平坦度。换言之,本发明不限于用于在待结合的基材上产生结合层的任何特定方法,也不受限于任何特定的平坦化方法。
如上所述,等离子体处理之间的中间清洁步骤是任选的。在氧等离子体活化之后进行的最终的湿表面处理对于在表面上产生反应性OH基团是重要的,在表面上产生反应性OH基团有益于形成强键合。最终的湿表面处理可包括依据已知实践进行的、用于在单独的清洁模块中的清洁步骤的水洗步骤或由该水洗步骤构成。除了有助于形成OH基团,水洗清洁了表面。高效清洁技术如高压清洁或兆声清洁可以被结合到水洗步骤中。不采用水洗步骤,最终的湿处理可包括使电介质结合层暴露于含水环境或由该操作构成,也能在结合表面上产生反应性OH基团。得益于等离子体活化,SiCN、SiCO或SiC表面变得高度亲水,以高亲和作用吸引水分子。除了最终的湿表面处理(包括水洗或暴露于含H2O环境)外,还可以使用替代性的清洁溶液(例如稀APM)来除去其它表面污染物。这可以在湿处理步骤之前或之后进行。依据优选的实施方式,待结合的各基材接受湿处理(加上可能的其它清洁溶液处理)的时间小于300秒,然后进行旋干处理。本发明人进行的测试已经显示,与使用N2等离子体处理时相比,使用本发明的等离子体系列处理时,水洗之后的OH基团的量明显更高。
除了形成OH基团外,本发明特定的等离子体系列处理高度有效是因为在依据本发明的方法步骤后经过等离子体处理的SiCO、SiCO或SiC表面上形成高密度的碳悬空键。在两个表面上的这些碳悬空键形成强碳碳键,从而为通过本发明方法实现的优异的结合强度作出了重要贡献。存在大量C悬空键也是之所以本发明方法能实现SiCN、SiCO和SiC结合层的高结合强度而当相同的方法应用于SiO2结合层时效果要差得多的原因。悬空键(DB)的电子自旋共振(ESR)监控已经被用来根据界面处化学键密度的变化对SiCN-SiCN和SiO2-SiO2结合强度进行比较。从氩气等离子体的等离子体活化接着氧等离子体活化之后以及洗涤之后的样品获得结合之前的初始DB密度(碳和硅悬空键)。对于SiCN,结合之前样品测得的总DB密度估计为2.4×10E14/cm2,相反,对于SiO2结合的情况,该值为0.2×10E14/cm2。在结合后,对于在200℃和250℃结合后退火,SiCN-SiCN结合样品的DB密度分别下降到1.2×10E14/cm2和0.54×10E14/cm2。对于SiO2-SiO2,实际上在退火后未检测到DB。这些结果说明在SiCN情况中碳悬空键对结合强度的重要贡献。在SiO2的情况中,因为结合之前较低的初始DB密度,悬空键效应没有对SiO2-SiO2界面处的化学键形成起到重要作用。在SiO2-SiO2结合的情况中,结合强度主要基于表面上形成的OH基团的影响。这是本发明方法之所以对含碳的结合层SiCN、SiCO和SiC的结合强度有重要的正面影响而对SiO2结合层不能产生这种正面影响的原因。以下测试结果将说明这一点。
实施例–测试结果
本发明人进行了比较测试,通过本发明方法处理了硅晶片上的平坦化SiCO和SiCN结合层,并与N2等离子体活化的预处理进行比较。还对SiO2结合层进行了比较测试。在以下条件下并在室温下,在电容耦合等离子体反应器中进行测试。湿处理步骤包括湿清洁模块中的去离子水洗涤,以及随后的旋干处理。
N2等离子体处理条件
压力 350毫托
RF功率 100W
RF频率 350kHz
工艺时间 15秒
N2流量 35sccm*
氩气等离子体处理条件
压力 350毫托
RF功率 200W
RF频率 350kHz
工艺时间 15秒
Ar流量 35sccm*
氧气等离子体处理条件
压力 350毫托
RF功率 200W
RF频率 350kHz
工艺时间 15秒
氧气流量 35sccm*
*单位sccm表示标准立方厘米/分钟,标准条件为0℃和1atm(101325Pa)
然后进行利用SiCO-SiCO结合、SiCN-SiCN结合或SiO2-SiO2结合的直接结合。结合后退火在200℃进行2-4小时,在一些情况中在210℃-250℃的较高的温度下进行,如图1的图表所示。图1显示对各个实验测得的结合强度。正方形表示在沿着X轴给出的各条件下进行的多次测量的平均值。显然,在SiCN和SiCO的情况中,与结合相同或相似退火温度施加的N2预处理相比,依据本发明的Ar-O2预处理产生更高的结合强度。重要的是,在200-250℃的温度下进行结合后退火可以得到高结合强度,即该温度低于目前常用的结合后退火温度。这意味着本发明开辟了获得优异的结合强度并结合较低的热预算的潜力。但是,较高的结合后退火温度并不排除在保护范围之外。依据一种实施方式,结合后退火温度低于400℃,更优选最高为350℃,更优选最高为250℃,更优选在200℃-250℃之间。SiO2结合层的结果证实通过本发明方法预处理的SiCN和SiCO结合层上碳悬空键的密度增加所带来的上述影响。当应用于SiO2时,与N2等离子体预处理相比,本发明方法不能导致结合强度增加。
虽然已经就附图和上述说明对本发明进行了详细说明和描述,但是这些说明和描述应认为是说明性或示例性的而并非限制性的。本领域技术人员在实践要求权利的发明中,通过对附图、说明书和所附权利要求的研究能够理解和实施所揭示实施方式的其它变体。在权利要求中,词语“包含(包括)”不排除其它要素或步骤,并且不定冠词“一个”或“一种”并不排除复数形式。某些措施在相互不同的从属权利要求中被提出的事实并不意味着这些措施的组合不能被利用。权利要求中的任意参考文献标记并不构成对范围的限制。

Claims (11)

1.一种使第一基材与第二基材直接结合的方法,所述第一基材和第二基材包含电介质结合层,其中所述结合通过使电介质结合层互相接触形成基材组件并对该组件进行结合后退火来进行,其中两个结合层在结合之前都进行预处理,所述预处理包括按照所述的顺序进行的以下步骤:
·在惰性气体等离子体中的第一等离子体活化步骤,
·在氧等离子体中的第二等离子体活化步骤,
·湿表面处理,包括水洗步骤或包括暴露于含水环境,
其中,两个基材上的两个电介质结合层是两个SiCO层或两个SiCN层或两个SiC层。
2.如权利要求1所述的方法,其特征在于,所述等离子体活化步骤中的一个或两个步骤在电容耦合等离子体的等离子体反应器中进行。
3.如权利要求1所述的方法,其特征在于,所述等离子体活化步骤中的一个或两个步骤在感应耦合等离子体的等离子体反应器中进行。
4.如前述权利要求中任一项所述的方法,其特征在于,在基材与等离子体之间不主动施加DC偏置电压。
5.如前述权利要求中任一项所述的方法,其特征在于,两个等离子体活化步骤都在以下条件下进行:
·通过射频电源产生等离子体,
·压力在1.33-133.3Pa之间,
·RF频率在100KHz-300MHz之间,
·RF功率在50W-300W之间,
·温度低于60℃。
6.如权利要求5所述的方法,其特征在于,两个等离子体活化步骤的RF频率都在100KH-1MHz之间。
7.如前述权利要求中任一项所述的方法,其特征在于,结合后退火温度低于400℃。
8.如权利要求7所述的方法,其特征在于,结合后退火温度在200℃-250℃之间。
9.如前述权利要求中任一项所述的方法,其特征在于,惰性气体是氩气。
10.如前述权利要求中任一项所述的方法,其特征在于,湿表面处理在低于300秒的时间段内进行。
11.如前述权利要求中任一项所述的方法,其特征在于,所述方法包括在第一等离子体活化步骤和第二等离子体活化步骤之间的中间清洁步骤。
CN201810167581.6A 2017-02-28 2018-02-28 半导体基材直接结合的方法 Active CN108511332B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP17158430.3 2017-02-28
EP17158430.3A EP3367425A1 (en) 2017-02-28 2017-02-28 A method for direct bonding of semiconductor substrates

Publications (2)

Publication Number Publication Date
CN108511332A true CN108511332A (zh) 2018-09-07
CN108511332B CN108511332B (zh) 2023-06-20

Family

ID=58192191

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810167581.6A Active CN108511332B (zh) 2017-02-28 2018-02-28 半导体基材直接结合的方法

Country Status (3)

Country Link
US (1) US10886252B2 (zh)
EP (2) EP3367425A1 (zh)
CN (1) CN108511332B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112885777A (zh) * 2020-01-07 2021-06-01 长江存储科技有限责任公司 金属-电介质键合方法和结构

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115602651A (zh) 2021-07-09 2023-01-13 联华电子股份有限公司(Tw) 接合半导体结构及其制作方法
CN114920468B (zh) * 2022-06-01 2023-12-05 北方夜视技术股份有限公司 一种硼硅玻璃亲水性键合方法
CN115262211B (zh) * 2022-07-15 2023-08-29 南方科技大学 一种超疏水织物及其制备方法

Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6171982B1 (en) * 1997-12-26 2001-01-09 Canon Kabushiki Kaisha Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same
US20010001707A1 (en) * 1999-05-07 2001-05-24 United Microelectronics Corp. Treatment on silicon oxynitride
US20010008226A1 (en) * 1998-07-09 2001-07-19 Hoiman Hung In-situ integrated oxide etch process particularly useful for copper dual damascene
US20030089950A1 (en) * 2001-11-15 2003-05-15 Kuech Thomas F. Bonding of silicon and silicon-germanium to insulating substrates
US20030141502A1 (en) * 2000-08-09 2003-07-31 Ziptronix Method of epitaxial-like wafer bonding at low temperature and bonded structure
US20040126993A1 (en) * 2002-12-30 2004-07-01 Chan Kevin K. Low temperature fusion bonding with high surface energy using a wet chemical treatment
CN1581497A (zh) * 2003-08-05 2005-02-16 国际商业机器公司 采用晶片键合和simox工艺的不同晶体取向自对准soi
US20050173057A1 (en) * 2003-08-29 2005-08-11 Tadatomo Suga Method for bonding substrates and method for irradiating particle beam to be utilized therefor
CN1860590A (zh) * 2003-05-19 2006-11-08 齐普特洛尼克斯公司 室温共价粘结的方法
US20070015373A1 (en) * 2005-07-13 2007-01-18 General Electric Company Semiconductor device and method of processing a semiconductor substrate
CN101548362A (zh) * 2005-01-13 2009-09-30 国际商业机器公司 具有受控的双轴应力的超低介电常数层
US20100047588A1 (en) * 2006-04-04 2010-02-25 Syohei Hata Electronic Component Union, Electronic Circuit Module Utilizing the Same, and Process for Manufacturing the Same
DE102009020163A1 (de) * 2009-05-07 2010-12-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum zwischenschichtfreien Verbinden von Substraten, Vorrichtung zur Durchführung einer Plasmabehandlung sowie deren Verwendung
US20130071580A1 (en) * 2011-09-13 2013-03-21 Applied Materials, Inc. Activated Silicon Precursors For Low Temperature Deposition
CN103168344A (zh) * 2010-11-03 2013-06-19 应用材料公司 用于沉积碳化硅和碳氮化硅膜的设备和方法
US20130270328A1 (en) * 2010-07-21 2013-10-17 Commissariat A L'energie Atomique Et Aux Ene Alt Process for direct bonding two elements comprising copper portions and portions of dielectric materials
CN103460342A (zh) * 2011-04-08 2013-12-18 Ev集团E·索尔纳有限责任公司 晶片的永久粘合方法
CN104282577A (zh) * 2013-06-24 2015-01-14 Imec公司 用于在半导体衬底上产生接触区的方法
CN104685633A (zh) * 2012-07-03 2015-06-03 Imec非营利协会 制作薄膜晶体管的方法
CN105720006A (zh) * 2014-12-18 2016-06-29 Imec 非营利协会 等离子体处理方法
US20190057897A1 (en) * 2016-03-07 2019-02-21 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8219874B2 (en) 2009-02-19 2012-07-10 Nec Laboratories America, Inc. Multi-dimensional LDPC coded modulation for high-speed optical transmission systems
FR2986904A1 (fr) 2012-02-14 2013-08-16 St Microelectronics Crolles 2 Systeme d'assemblage de puces
EP3024019A1 (en) * 2014-11-24 2016-05-25 IMEC vzw Method for direct bonding of semiconductor substrates.

Patent Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6171982B1 (en) * 1997-12-26 2001-01-09 Canon Kabushiki Kaisha Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same
US20010008226A1 (en) * 1998-07-09 2001-07-19 Hoiman Hung In-situ integrated oxide etch process particularly useful for copper dual damascene
US20010001707A1 (en) * 1999-05-07 2001-05-24 United Microelectronics Corp. Treatment on silicon oxynitride
US20030141502A1 (en) * 2000-08-09 2003-07-31 Ziptronix Method of epitaxial-like wafer bonding at low temperature and bonded structure
US20030089950A1 (en) * 2001-11-15 2003-05-15 Kuech Thomas F. Bonding of silicon and silicon-germanium to insulating substrates
US20040126993A1 (en) * 2002-12-30 2004-07-01 Chan Kevin K. Low temperature fusion bonding with high surface energy using a wet chemical treatment
CN1860590A (zh) * 2003-05-19 2006-11-08 齐普特洛尼克斯公司 室温共价粘结的方法
CN1581497A (zh) * 2003-08-05 2005-02-16 国际商业机器公司 采用晶片键合和simox工艺的不同晶体取向自对准soi
US20050173057A1 (en) * 2003-08-29 2005-08-11 Tadatomo Suga Method for bonding substrates and method for irradiating particle beam to be utilized therefor
CN101548362A (zh) * 2005-01-13 2009-09-30 国际商业机器公司 具有受控的双轴应力的超低介电常数层
US20070015373A1 (en) * 2005-07-13 2007-01-18 General Electric Company Semiconductor device and method of processing a semiconductor substrate
US20100047588A1 (en) * 2006-04-04 2010-02-25 Syohei Hata Electronic Component Union, Electronic Circuit Module Utilizing the Same, and Process for Manufacturing the Same
DE102009020163A1 (de) * 2009-05-07 2010-12-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum zwischenschichtfreien Verbinden von Substraten, Vorrichtung zur Durchführung einer Plasmabehandlung sowie deren Verwendung
US20130270328A1 (en) * 2010-07-21 2013-10-17 Commissariat A L'energie Atomique Et Aux Ene Alt Process for direct bonding two elements comprising copper portions and portions of dielectric materials
CN103168344A (zh) * 2010-11-03 2013-06-19 应用材料公司 用于沉积碳化硅和碳氮化硅膜的设备和方法
CN103460342A (zh) * 2011-04-08 2013-12-18 Ev集团E·索尔纳有限责任公司 晶片的永久粘合方法
US20140073112A1 (en) * 2011-04-08 2014-03-13 Ev Group E. Thallner Gmbh Method for permanently bonding wafers
US20130071580A1 (en) * 2011-09-13 2013-03-21 Applied Materials, Inc. Activated Silicon Precursors For Low Temperature Deposition
CN104685633A (zh) * 2012-07-03 2015-06-03 Imec非营利协会 制作薄膜晶体管的方法
CN104282577A (zh) * 2013-06-24 2015-01-14 Imec公司 用于在半导体衬底上产生接触区的方法
CN105720006A (zh) * 2014-12-18 2016-06-29 Imec 非营利协会 等离子体处理方法
US20190057897A1 (en) * 2016-03-07 2019-02-21 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
宋海兰;黄辉;崔海林;黄永清;任晓敏;: "InGaAs/Si雪崩光电二极管" *
王心心;梁庭;贾平岗;王涛龙;刘雨涛;张瑞;熊继军: "碳化硅直接键合机理及其力学性能研究" *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112885777A (zh) * 2020-01-07 2021-06-01 长江存储科技有限责任公司 金属-电介质键合方法和结构
US11798913B2 (en) 2020-01-07 2023-10-24 Yangtze Memory Technologies Co., Ltd. Metal-dielectric bonding method and structure

Also Published As

Publication number Publication date
EP3376524A1 (en) 2018-09-19
EP3367425A1 (en) 2018-08-29
US20180247914A1 (en) 2018-08-30
EP3376524B1 (en) 2021-12-15
CN108511332B (zh) 2023-06-20
US10886252B2 (en) 2021-01-05

Similar Documents

Publication Publication Date Title
CN108511332A (zh) 半导体基材直接结合的方法
US20220159820A1 (en) Plasma processing method and plasma processing apparatus
Banna et al. Inductively coupled pulsed plasmas in the presence of synchronous pulsed substrate bias for robust, reliable, and fine conductor etching
JP2002261091A (ja) 半導体装置およびその製造方法
EP1361606A1 (en) Method of producing electronic device material
CN106653532A (zh) 用于对蚀刻工艺进行先进的离子控制的方法和***
JP2002261097A (ja) 誘電体膜およびその形成方法、半導体装置、不揮発性半導体メモリ装置、および半導体装置の製造方法
JP2003051481A (ja) 半導体集積回路装置の製造方法
KR101121434B1 (ko) 반도체 장치의 제조 방법
WO2012117787A1 (en) Method of manufacturing semiconductor device
CN101606234A (zh) 蚀刻方法及存储介质
JP2003023000A (ja) 半導体装置の製造方法
KR102321315B1 (ko) 플라즈마 에칭 챔버 내에서 반도체 기판의 상부 표면을 평탄화하는 방법
JP4645167B2 (ja) フォーカスリング、プラズマエッチング装置及びプラズマエッチング方法。
JP2008060258A (ja) プラズマ処理装置およびプラズマ処理方法
US20230402427A1 (en) Heterogenous bonding layers for direct semiconductor bonding
CN101521159A (zh) 提高圆片均匀性的方法及层间介质
KR20100014564A (ko) 질화규소막 및 비휘발성 반도체 메모리 장치
JP2016032117A (ja) タングステン含有層をエッチングする方法
CN108231667A (zh) 半导体装置结构的形成方法
CN104103512B (zh) 绝缘层形成方法
TW200402095A (en) Plasma apparatus and method capable of adaptive impedance matching
Kim et al. Chemical mechanical polishing of BTO thin film for vertical sidewall patterning of high-density memory capacitor
US20070077772A1 (en) Apparatus and method for manufacturing semiconductor device using plasma
JPH08130199A (ja) 段差基体の平坦化方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant