CN108511330A - Forming method, semiconductor devices and the integrated circuit of mask pattern - Google Patents
Forming method, semiconductor devices and the integrated circuit of mask pattern Download PDFInfo
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- CN108511330A CN108511330A CN201810273406.5A CN201810273406A CN108511330A CN 108511330 A CN108511330 A CN 108511330A CN 201810273406 A CN201810273406 A CN 201810273406A CN 108511330 A CN108511330 A CN 108511330A
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- clearance wall
- substrate
- material layer
- fusion
- mask pattern
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
Abstract
The present invention provides the forming method of mask pattern, semiconductor devices and integrated circuits.The forming method of the mask pattern includes that multiple first mandrel structures are formed in substrate, it include groove between first mandrel structure, the surface of the bottom surface exposure substrate of groove, then the first clearance wall and fusion clearance wall are formed in the side of the first mandrel structure, wherein the width of the first clearance wall is less than the width of fusion clearance wall, merge the bottom surface of clearance wall covering groove, then multiple first mandrel structures in substrate are removed, using the first clearance wall and clearance wall is merged as the second mandrel structure, the second clearance wall is formed in the side of the first clearance wall and the side for merging clearance wall, and removal second mandrel structure.The fine structure of continuous Unequal distance can be obtained in substrate as mask pattern using remaining multiple second clearance walls in substrate, be conducive to the degree of freedom and the flexibility that improve the circuit design for being formed by semiconductor devices and integrated circuit.
Description
Technical field
The present invention relates to integrated circuit fields and mask technique, more particularly to a kind of forming method of mask pattern, one kind
Semiconductor devices and a kind of integrated circuit.
Background technology
In recent years, due to the demand to increasing portability, computing capability, memory capacity and efficiency etc., constantly will
IC manufacturing obtains more crypto set, and the characteristic size for forming the device of integrated circuit is also constantly reducing.As integrated circuit
A kind of middle basic device, field-effect transistor (field effect transistors, FET) device size is also lasting
It reduces, the development of existing plane formula (planar) field effect transistor has faced the limit in manufacture craft.
In order to overcome manufacture craft to limit, with the FET device of on-plane surface (non-planar), such as fin
Field-effect transistor (fin field effect transistor, Fin FET) device replaces planar transistor devices to have become
For current mainstream development trend.Since the stereochemical structure of fin formula field effect transistor device can increase grid and fin structure
Therefore contact area can further increase control of the grid for channel region, to reduce the drain electrode that small size device faces
Causing energy band reduces (drain induced barrier lowering, DIBL) effect, and can inhibit short-channel effect
(short channel effect, SCE).In addition, due to fin formula field effect transistor device meeting under same grid length
With broader channel width, thus it can get the drain drives electric current doubled.Further, the critical voltage of transistor device
(threshold voltage) can also be regulated and controled by adjusting the work function of grid.
The manufacture craft of existing fin formula field effect transistor is fin structure first to be formed in substrate, then grid is formed in
On fin structure.Fin structure generally etches substrate and is formed by strip fin (fin), but under the requirement of size micro,
The width of each fin is tapered, and the spacing (pitch) between fin also reduces gradually, or even has exceeded the feature ruler of lithographic process
The very little limit.
Fin field-effect transistor and other be more than the lithographic process characteristic size limit fine pattern processing technology
In, sidewall pattern transfer (sidewall image transfer, SIT) is a kind of conventional process, which includes mainly following
Step：Multiple mandrel structures are formed with photoetching and etch process first in substrate, it is described more to form mask layer covering later
A mandrel structure and substrate surface, the method for then carrying out such as etch-back make the mask of only remaining covering mandrel structure side
Layer is used as the first clearance wall, the multiple mandrel structure is removed later, using the first clearance wall as mask pattern.Utilize side wall figure
Case shifting process can form the structure with more careful arrangement compared with the pattern of the multiple mandrel structure in substrate.
In order to continue to break through the characteristic size limit of lithographic process, reach smaller circuit area, in sub- 10nm nodes
It (sub-10nm node) or even needs to carry out sidewall pattern shifting process twice in succession, i.e., secondary side wall pattern transfering process
(Dual-SIT), i.e., the second clearance wall is formed again in above-mentioned first clearance wall side with similar method, then remove first
Clearance wall is etched lower layer's such as substrate using the second clearance wall as mask pattern, and careful arrangement is formed in substrate
Structure.A spacing X of the second clearance wall of the covering substrate surface formed in the first clearance wall side be can be seen that by first
The width of clearance wall determines.Since the width of usual first clearance wall is roughly equal and continuous arrangement, thus spacing X is caused to repeat
Occur, the regularity of spacing X causes to have to make as some concessions when designing the circuit around fine structure, thus limits electricity
The flexibility of road design.
Invention content
The technical problem to be solved by the present invention is between the fine structure formed in secondary side wall pattern transfering process
Occur leading to the restricted problem to circuit design away from the intervals X.
To solve the above problems, the present invention provides a kind of forming methods of mask pattern, which is characterized in that including：It carries
For substrate；Multiple first mandrel structures are formed on the substrate, include groove, the groove between first mandrel structure
Bottom surface expose the surface of the substrate；The first clearance wall and fusion clearance wall are formed in the side of first mandrel structure,
Wherein, the width of first clearance wall is less than the width of the fusion clearance wall, and the fusion clearance wall covers the groove
Bottom surface；Remove the multiple first mandrel structure in the substrate；With first clearance wall and the fusion clearance wall
As the second mandrel structure, the second gap is formed in the side of the side of first clearance wall and the fusion clearance wall
Wall；And removal second mandrel structure.
Optionally, after removing second mandrel structure, using second clearance wall as mask, the substrate is etched
To form pattern on the substrate.
Optionally, include the step of the side of first mandrel structure forms the first clearance wall and fusion clearance wall：
Spacer material layer is deposited, the spacer material layer covering includes the substrate of first mandrel structure and the groove
Surface；And etch-back is carried out to remove the institute for the upper surface for being located at first mandrel structure to the spacer material layer
Spacer material layer is stated, and first clearance wall and the fusion clearance wall are formed in the side of first mandrel structure.
Optionally, include to the step of spacer material layer progress etch-back：It will be in the groove using protective layer
The spacer material layer block, spacer material layer described in etch-back is partly to remove the spacer material layer；And
The protective layer is removed, continues etch-back to form first clearance wall and the fusion clearance wall.
Optionally, include to the step of spacer material layer progress etch-back：It will be in the groove using protective layer
The spacer material layer block, spacer material layer described in etch-back with remove be located at first mandrel structure upper table
The spacer material layer in face, and form first clearance wall in the side of the multiple first mandrel structure；And it moves
Except the protective layer, made using CMP process the upper surface of the spacer material layer in the groove with it is described
The upper surface flush of first mandrel structure, the remaining spacer material layer is as the fusion gap using in the groove
Wall.
Optionally, the multiple first mandrel structure is of same size.
Optionally, the minimum range between the multiple second clearance wall is less than or equal to 32nm.
The present invention also provides a kind of semiconductor devices, forming method includes the forming method of aforementioned mask pattern, described
Semiconductor devices includes substrate and the multiple continuous non-equally structures formed in substrate, it is the multiple it is continuous non-equally
Structure at least has one group of continuous three unequal spacing on the direction for being parallel to the substrate surface.
Optionally, the semiconductor devices is fin formula field effect transistor.
The present invention also provides a kind of integrated circuits, including above-mentioned semiconductor device.
According to the forming method of mask pattern provided by the invention, between the side of first mandrel structure forms first
Gap wall and fusion clearance wall, wherein the width of first clearance wall is less than the width of the fusion clearance wall, between the fusion
Gap wall covers the bottom surface of the groove, and the fusion clearance wall formed on the substrate in this way makes the first clearance wall no longer only have
One same or analogous width, to form the as the second mandrel structure using first clearance wall and fusion clearance wall
After two clearance walls, being formed by the spacing between the second clearance wall can be determined by the width of fusion clearance wall, to be formed by
When second clearance wall is etched substrate as mask pattern, it is formed by between semiconductor structure not including one every one
It is at least not equidistant with one group continuous three to be formed by semiconductor structure for the identical spacing that spacing repeats.Utilize packet
Semiconductor devices and integrated circuit that the forming method of the mask pattern obtains are included, in the circuit design of fine structure, tool
There are larger degree of freedom and flexibility.
Description of the drawings
Fig. 1 a to Fig. 1 e are a kind of schematic diagrames of each processing step of secondary side wall pattern transfering process.
Fig. 2 is the flow chart of the forming method of the mask pattern of the embodiment of the present invention.
Fig. 3 a to Fig. 3 e are the schematic diagrames of each processing step of the forming method of the mask pattern of the embodiment of the present invention.
Fig. 3 f are the diagrammatic cross-sections using the semiconductor devices of the embodiment of the present invention.
Reference sign：
10,30- substrates；11- first structures；110- is open；The first side walls of 12-；The second side walls of 13-；31- the first mandrel knots
Structure；310- grooves；The first clearance walls of 32-；320- merges clearance wall；The second clearance walls of 33-；300- semiconductor devices；34- is continuous
Non-equally structure.
Specific implementation mode
It to the forming method of the mask pattern of the present invention, semiconductor devices and is integrated below in conjunction with the drawings and specific embodiments
Circuit is described in further detail.According to following explanation, advantages and features of the invention will become apparent from.It should be noted that attached
Figure is all made of very simplified form and uses non-accurate ratio, only to convenient, lucidly the aid illustration present invention is real
Apply the purpose of example.
Term " first " " second " etc. is used between similar element distinguish, and is not necessarily for describing certain order
Or time sequencing.It is appreciated that in the appropriate case, these terms so used are replaceable, such as may make as described herein
The embodiment of the present invention can be different from it is as described herein or shown in other sequentially operate.Similar, if as described herein
Method includes series of steps, and the sequence of these steps presented herein is not necessarily can perform these steps unique
Sequentially, other steps that the step and described in some can be omitted and/or some are not described here can be added to this method.Figure
If the component of middle the embodiment of the present invention is identical as the component in other icons, although can all recognize this easily in all figures
A little components, but in order to keep the explanation of icon apparent, the label of all identical components will not be marked in each figure by this specification
In.
Fig. 1 a to Fig. 1 e are a kind of schematic diagrames of each processing step of secondary side wall pattern transfering process.Referring to Fig. 1 a
This secondary side wall pattern transfering process (Dual-SIT) is illustrated to Fig. 1 e.
As shown in Figure 1a, substrate 10 is provided first, forms multiple first structures 11, multiple first structures 11 on the substrate 10
Between multiple openings 110 (trench) are distributed with, multiple openings 110 expose the part surface of substrates 10.First structure 11 is for example
It is across the strip on 10 surface of substrate, opening 110 is located between the first structure 11 of these elongate in shape.
As shown in Figure 1 b, multiple first side walls 12 (spacer) then are formed in 11 both side surface of multiple first structures.
The formation of first structure 11 and the first side wall 12 can pass through film forming, photoetching and etch process shape disclosed in this field
At for example, the forming process of the first side wall 12 includes：Conformal deposited is certain thickness in the substrate 10 including first structure 11
Then material layer etches the material layer using self-registered technology vertically downward, until exposing the upper table of the first mandrel structure
The portion of upper surface of face and substrate.
As illustrated in figure 1 c, multiple first structures 11 in substrate 10 are then removed.Multiple first sides are left in substrate
Wall 12.
Distance of first side wall 12 on 11 side surface direction of first structure covering substrate, 10 surface can be used as the first side wall 12
Width X, X are usually same or similar value.
As shown in Figure 1 d, it using the first side wall 12 as the second mandrel structure, is formed in 12 both side surface of the first side wall multiple
Second side wall 13.Second side wall 13 is similar with the forming method of the first side wall 12.
As shown in fig. le, the first side wall 12 is removed.Followed by, using the second side wall 13 as the mask layer of etching substrate 10,
So as to form multiple fine structures corresponding to 13 position of the second side wall on the substrate 10.Between the multiple fine structure
It is corresponding with the spacing distribution of the second side wall 13 in substrate 10 away from being distributed.
As can be seen that since the second side wall 13 is formed in 12 both side surface of the first side wall, the spacing of multiple second side walls 13
It is defined by the width X of the first side wall 12, and according to above-mentioned technique, the width X identical (or close) of the first side wall 12 is simultaneously continuously arranged
Row, so that the second side wall 13 also has a constant spacing X, and spacing X has the rule that interval repeats.This rule and the
The design of one structure 11 is unrelated, and this interval repeats to increase complexity when circuit design, limits the degree of freedom of design.
Circuit design is flexible in processing technology in order to improve the fine pattern for being more than the lithographic process characteristic size limit
Property, and between overcoming between multiple fine structures that prior art obtains after sidewall image transfer technique twice in succession and existing
Lead to the restricted problem in circuit design every the distance values X repeated, present invention firstly provides a kind of formation of mask pattern
Method, the forming method of the mask pattern include that multiple first mandrel structures are formed in substrate, multiple first mandrel structures
Between be distributed with bottom expose substrate surface groove, then form multiple first gaps in the side of multiple first mandrel structures
Wall, forms fusion clearance wall in part of trench, then the substrate surface in the fusion clearance wall covering respective grooves removes
The multiple first mandrel structure, multiple first clearance walls left in substrate and fusion clearance wall.Then in substrate
Multiple first clearance walls and fusion clearance wall form multiple second gaps as the second mandrel structure in the second mandrel structure side
Wall is etched technique using the multiple second clearance wall as mask pattern, and the fine structure formed in substrate at least has
There is one group of continuous three unequal spacing.Invention additionally provides utilize the forming method institute shape for including the mask pattern
At semiconductor devices and integrated circuit.
Fig. 2 is a kind of flow diagram of the forming method of mask pattern provided in an embodiment of the present invention.Specifically include with
Lower step：
S1：Substrate is provided；
S2：Multiple first mandrel structures are formed on the substrate, include groove between first mandrel structure, it is described
The bottom surface of groove exposes the surface of the substrate；
S3：The first clearance wall and fusion clearance wall are formed in the side of first mandrel structure, wherein between described first
The width of gap wall is less than the width of the fusion clearance wall, and the fusion clearance wall covers the bottom surface of the groove；
S4：Remove the multiple first mandrel structure in the substrate；
S5：Using first clearance wall and the fusion clearance wall as the second mandrel structure, in first clearance wall
Side and it is described fusion clearance wall side formed the second clearance wall；And
S6：Remove second mandrel structure.
Fig. 3 a to Fig. 3 e are the schematic diagrames of each processing step of the forming method of the mask pattern of the embodiment of the present invention.Below
The forming method of the mask pattern of the embodiment of the present invention is illustrated in conjunction with Fig. 2 and Fig. 3 a to Fig. 3 e.
In conjunction with Fig. 2 and Fig. 3 a, step S1 and S2 are executed, substrate 30 is provided, forms multiple first mandrel knots in substrate 30
Structure 31 includes groove 310 between multiple first mandrel structures 31, and the bottom surface of groove 310 exposes the surface of substrate 30.
Substrate 30 is, for example, the semiconductor substrate for the integrated circuit that part manufacture is distributed with, and the semiconductor substrate can be
Silicon substrate contains silicon base or silicon-coated insulated (silicon-on-insulator, SOI) substrate etc., in addition, can be in substrate 30
Including the underlying material layer formed on a semiconductor substrate, the underlying material layer be one or more layers, for example, silicon oxide layer,
One silicon nitride layer and one silica layer arbitrarily combine the multilayer formed by it, can be with subsequently on the underlying material layer
Form the fine structure in substrate 30, or as forming mandrel structure and/or masking substrate 30 below when clearance wall
Hard mask layer.
The forming method of first mandrel structure 31 may include：A mandrel (mandrel) layer is deposited in substrate 30 first,
The mandrel layer is, for example, the siliceous film layer such as polysilicon layer or amorphous silicon layer, then progress photoetching and etch process, described in etching
Mandrel layer forms groove 310, groove to form multiple first mandrel structures 31 between multiple first mandrel structures 31
310 run through the mandrel layer so that the bottom-exposed of groove 310 goes out the part surface of substrate 30.In some implementations of the present invention
In example, the forming method of the first mandrel structure 31 can also be the method for other patterning mandrel layer.In the present embodiment, first heart
Axle construction 31 be formed in the strip structure (being strip i.e. on the paper direction in Fig. 3 a) on 30 surface of substrate, but this
Invent it is without being limited thereto, the first mandrel structure 31 can also have meets device design it is variously-shaped.
First mandrel structure 31 at least has there are one width, the width and multiple grooves of multiple first mandrel structures 31
310 width can be identical or different.In order to keep the explanation of the embodiment of the present invention clearer, indicate to scheme respectively with A, B and C
The width of two the first mandrel structures 31 and groove 310 shown in 3a.A, the value of B, C are greater than 90nm, but not limit
System, the spacing of the first mandrel structure 31 and width by lithographic equipment resolution ratio and device design definition.
With reference to Fig. 2 and Fig. 3 b, step S3 is executed, the first clearance wall 32 and fusion are formed in the side of the first mandrel structure 31
Clearance wall 320, wherein the width of the first clearance wall 32 is less than the width of fusion clearance wall, merges 320 covering groove of clearance wall
310 bottom surface.In order to make it easy to understand, it is considered that all form the first clearance wall 32 in the both sides of all first mandrel structures 31,
And two adjacent first clearance walls 32 in groove 310 are merged, and are formed fusion clearance wall 320, are covered groove
30 surface of substrate of exposure in 310, but this understanding does not constitute a part for the forming method of the present embodiment mask pattern.
The forming method of first clearance wall 32 may include following process：Deposit a spacer material layer, the clearance wall
Material layer covering includes 30 surface of substrate of the first mandrel structure 31 and groove 310；Then, for example, by self aligned vertical erosion
Carving technology carries out etch-back, gap wall material of the removal positioned at the upper surface of the first mandrel structure 31 to the spacer material layer
The bed of material forms the first clearance wall 32 and fusion clearance wall 320, wherein the first clearance wall 32 in the side of the first mandrel structure 31
Width be less than fusion clearance wall 320 width, merge 320 covering groove 310 of clearance wall bottom surface.
Fusion clearance wall 320 can pass through the size design (such as trench design width is smaller) and/or work to groove 310
Skill controls the adjustment of the methods of (such as increasing the thickness of the spacer material layer) so that is covered in the gap on 30 surface of substrate
Wall material layer segment is etched and exposes 30 surface of corresponding substrate, and the substrate surface in groove 310 is not exposed, then
Using in groove 310 remaining spacer material layer as fusion clearance wall 320.
The material of the spacer material layer may include silicon nitride (silicon nitride), silicon oxynitride (silicon
) or fire sand (silicon carbonitride) etc. oxynitride.
After above-mentioned etch-back process, groove 310 is not formed in the larger groove (not shown) of partial width or
The first clearance wall 32 that first mandrel structure, 31 both sides are formed, width (width for covering 30 surface of substrate) basic one
It causes, is set as X', and the width for merging clearance wall 320 is equal with the width C of groove 310.By using the shape of aforementioned mask pattern
At method, it is reachable that the width X' of the first clearance wall 32 can be not limited to (can greater than, equal to or be less than) common lithographic equipment
The minimum feature arrived.
First clearance wall 32 and fusion clearance wall 320 can also be formed by other means, in some embodiments, can be with
The spacer material layer in groove 310 is blocked using a protective layer (being, for example, photoresist layer or other etch-resistant material layers),
The spacer material layer in other regions in first etch-back substrate 30, then exposes all spacer material layers, continues again
Etch back process is to form the first clearance wall 32 and fusion clearance wall 320.In other embodiments, a guarantor may be used
Sheath blocks the spacer material layer in groove 310, and the spacer material layer in other regions is with shape in first etch-back substrate 30
At the first clearance wall 32, then flatening process (such as CMP process) is utilized to make to be covered in the groove 310 in non-etch-back region
Spacer material layer planarization, using the upper surface of the first mandrel structure 31 as stop-layer, to obtain fusion clearance wall 320.
In some other embodiment, can also use for example selective film build method 31 side of the first mandrel structure and/or other
30 surface of substrate in groove forms the first clearance wall 32, and fusion clearance wall 320 is formed in groove 310, in short, obtaining
First clearance wall 32 and fusion clearance wall 320 can be there are many methods, the invention is not limited thereto limited scheme that place lists.
In other embodiments of the invention, fusion clearance wall 320 can be formed in groove 310, merge clearance wall 320
30 surface of substrate in covering groove 310.That is fusion clearance wall can be formed in any one or multiple grooves 310, and
30 surface of substrate in the filled groove 310 of covering.
First clearance wall 32 and fusion clearance wall 320 can be formed as the subsurface material in mask etching substrate 30
The position distribution of fine structure defined with the first clearance wall 32 and fusion clearance wall 320, position relationship and the first clearance wall
32 is corresponding with the fusion position relationship of clearance wall 320.In order to form the smaller mask pattern of spacing, the mask of the embodiment of the present invention
The forming method of pattern can also include the steps of.
With reference to Fig. 2 and Fig. 3 c, step S4 is executed, removes multiple first mandrel structures 31 in substrate 30.First mandrel knot
Structure 31 can be removed using such as dry method etch technology, and dry method etch technology is the more mature technique of integrated circuit fields, this
Place is no longer described in detail.
With reference to Fig. 2 and Fig. 3 d, step S5 is executed, using the first clearance wall 32 and merges clearance wall 320 as the second mandrel knot
Structure forms the second clearance wall 33 in the side of the first clearance wall 32 and the side for merging clearance wall 320.Second clearance wall 33
Forming method is similar to the forming method of above-mentioned first clearance wall 32, similar, and the width X " of the second clearance wall 33 is not limited to (i.e.
Can greater than, equal to or be less than) the common accessible minimum feature of lithographic equipment.
With reference to Fig. 2 and Fig. 3 e, step S6 is executed, removes second mandrel structure.In the embodiment of the present invention, the second mandrel
Structure includes the first clearance wall 32 and fusion clearance wall 320.Removing the first clearance wall 32 and fusion clearance wall 320 can utilize and do
Method etch process.
Through the above steps and simple computation it is found that continuous distance values between the second clearance wall 33 be respectively equal to (or
Be similar to) X', A-2X ", C, B-2X " ..., wherein width A and width B respectively in step s 2 utilize lithographic equipment define
Two neighboring first mandrel structure 31 width, the width of width C groove 310 between the two first mandrel structures 31,
Width X' and width X " is respectively the width that the first clearance wall 32 and the second clearance wall 33 are covered in substrate 30, in integrated circuit work
In skill, X' and X " can be less than the accessible minimum feature of common lithographic equipment.For example, by secondary side wall shifting process, institute
Minimum spacing between the second obtained clearance wall 33 can reach 32nm or less (including being equal to 32nm).In some embodiments
In, can repeat the above steps S3 to S6, to obtain smaller n-th clearance wall of width (n is the integer more than 2).
The embodiment of the present invention can also be used as mask pattern including the use of the second clearance wall 33, be lost to 30 surface of substrate
The step of quarter.With reference to Fig. 2 and Fig. 3 f, it is mask pattern with the second clearance wall 33, substrate 30 is etched, so as in base
30 surface of bottom forms pattern.
Using the forming method of the mask pattern of the embodiment of the present invention, it is " X', A- that can obtain one group of continuous distance values
2X ", C, B-2X " ... " mask pattern breached solid compared with existing secondary sidewall pattern transfer (dual-SIT) technique
(necessarily continuous two spacing have existing secondary sidewall pattern transfer (dual-SIT) technique the rule that the intervals determining deviation X repeat
One repetition values X), be formed by the second clearance wall 32 have at least one set of continuous three unequal spacing (as A ≠ B, second
Clearance wall 32 has at least one set of continuous four unequal spacing).
Can be identical or different by designing the width value of multiple first mandrel structures 31 and groove 310, or between adjustment
The thickness of the gap wall material bed of material, so that at least partly forming fusion clearance wall 320, the width of the first clearance wall 32 in groove 310
Less than the width of fusion clearance wall 320；Again or by one or many photoetching and etch process at least partly groove 310
Form fusion clearance wall 32.After forming multiple second clearance walls 33, multiple second clearance walls 33 have one group continuous three
Or more the arrangement of unequal spacing.Those skilled in the art can use it in the case where not departing from intension of the present invention
His method forms the first clearance wall 32, fusion clearance wall 320 and the second clearance wall 33.
Mask pattern (such as the second clearance wall that there is at least one set of continuous three unequal spacing using obtained
33), substrate 30 is etched, then can obtain the fine structure at least one set of continuous three unequal spacing.
The embodiment of the invention also includes a kind of semiconductor devices 300, semiconductor devices can utilize aforementioned mask pattern
Forming method is formed.Fig. 3 f are the schematic diagrames of the semiconductor devices of the embodiment of the present invention.Semiconductor devices 300 includes at least：
Substrate 30；And
Multiple continuous non-equally structure 34 formed in substrate 30, the multiple continuous non-equally structure 34 is flat
Row on the direction on 30 surface of substrate at least have one group of continuous three unequal spacing.
Multiple continuous non-equally structures can be formed by mask pattern using the forming method of aforementioned mask pattern
Etch process is executed to substrate 30 to be formed.Specifically, may include steps of：Formed in substrate 30 first one group for example by
The mask pattern that multiple second clearance walls 33 form shown in Fig. 3 e, multiple second clearance walls 33 have at least one set of continuous three
Unequal spacing, such as one group of distance values " X', A-2X ", C, B-2X in Fig. 3 e " ... ", wherein A and B is respectively to utilize light
The width for two neighboring first mandrel structure 31 that engraving device defines, C is between two neighboring first mandrel structure 31 in Fig. 3 a
The width of groove 310, X' and X " are respectively the width of the first clearance wall 32 and the second clearance wall 33 covering substrate 30, in integrated electricity
In the technique of road, X' and X " are usually less than the accessible minimum feature of common lithographic equipment, and between the second clearance wall 33 most
Small spacing can reach 32nm or less (including being equal to 32nm).
As illustrated in figure 3f, one group of mask artwork that multiple second clearance walls 33 form shown in Fig. 3 e is formed in substrate 30
It is mask with the second clearance wall 33 after case, etches substrate 30, the material on the surface layer of substrate 30 can be semiconductor substrate materials
Can also be the single-layer or multi-layer material for being arranged or being formed in the first mandrel structure 31 of formation such as silicon.After the completion of etching, go
Except multiple second clearance walls 33, multiple continuous non-equally structure 34 are formd in remaining substrate 30.Multiple continuous Unequal distances
Spacing from structure 34 and 33 spacing of the second clearance wall as hard mask layer are same or similar, have at least one set of continuous three
Unequal spacing.
The semiconductor devices 300 of the embodiment of the present invention can be fin formula field effect transistor, plurality of continuous Unequal distance
From the fin (Fin) that structure 34 can be fin formula field effect transistor.According to manufacture craft demand, multiple fins can formed
Later, continue for example to form isolated part between each fin, and form gate structure and source/drain region in the fin
On.
The embodiment of the invention also includes a kind of integrated circuit, the integrated circuit includes above-mentioned semiconductor device.The collection
There can be multiple fine structures at circuit, and the fine structure has at least one set of continuous three unequal spacing.
The spacing of the fine structure can be not limited to and (be, for example, less than) the attainable minimum feature of common lithographic equipment institute.
Using the forming method of the mask pattern, existing secondary side wall pattern transfering process can be overcome to be formed finely
The constant spacing value being repeated once in the presence of one spacing of interval when structure causes the limitation in circuit design, the present embodiment description
Mask pattern forming method, being formed by mask pattern has at least one set of continuous three unequal spacing, utilizes this
Method can be made in substrate with continuous fine structure non-equally.The step of the present invention can also be carried out repeatedly, from
And the fine structure that continuous unequal spacing is more than three can be formed.In addition it includes institute that the embodiment of the present invention is described and utilized
The semiconductor devices that the forming method of mask pattern makes is stated, and includes the integrated circuit of this semiconductor devices.
It should be noted that the embodiment of this specification is described by the way of progressive, what each embodiment stressed
All it is difference from other examples, just to refer each other for identical and similar part between each embodiment.For reality
For applying semiconductor devices and integrated circuit disclosed in example, due to opposite with the forming method of mask pattern disclosed in embodiment
It answers, so description is fairly simple, referring to the explanation of the forming method to mask pattern in place of correlation.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of interest field of the present invention,
Any those skilled in the art without departing from the spirit and scope of the present invention, may be by the methods and techniques of the disclosure above
Content makes possible variation and modification to technical solution of the present invention, therefore, every content without departing from technical solution of the present invention,
According to the technical essence of the invention to any simple modifications, equivalents, and modifications made by above example, this hair is belonged to
The protection domain of bright technical solution.
Claims (10)
1. a kind of forming method of mask pattern, which is characterized in that including：
Substrate is provided；
Multiple first mandrel structures are formed on the substrate, include groove between first mandrel structure, the groove
Bottom surface exposes the surface of the substrate；
The first clearance wall and fusion clearance wall are formed in the side of first mandrel structure, wherein first clearance wall
Width is less than the width of the fusion clearance wall, and the fusion clearance wall covers the bottom surface of the groove；
Remove the multiple first mandrel structure in the substrate；
Using first clearance wall and the fusion clearance wall as the second mandrel structure, the side of first clearance wall with
And the side of the fusion clearance wall forms the second clearance wall；And
Remove second mandrel structure.
2. the forming method of mask pattern as described in claim 1, which is characterized in that remove second mandrel structure it
Afterwards, using second clearance wall as mask, the substrate is etched to form pattern on the substrate.
3. the forming method of mask pattern as described in claim 1, which is characterized in that in the side of first mandrel structure
It forms the first clearance wall and includes the step of merging clearance wall：
Deposit spacer material layer, spacer material layer covering includes the described of first mandrel structure and the groove
The surface of substrate；And
Etch-back is carried out to remove the gap for the upper surface for being located at first mandrel structure to the spacer material layer
The wall material bed of material, and form first clearance wall and the fusion clearance wall in the side of first mandrel structure.
4. the forming method of mask pattern as claimed in claim 3, which is characterized in that returned to the spacer material layer
The step of etching includes：
The spacer material layer in the groove is blocked using protective layer, spacer material layer is with part described in etch-back
Remove the spacer material layer；And
The protective layer is removed, continues etch-back to form first clearance wall and the fusion clearance wall.
5. the forming method of mask pattern as claimed in claim 3, which is characterized in that returned to the spacer material layer
The step of etching includes：
The spacer material layer in the groove is blocked using protective layer, spacer material layer is to remove described in etch-back
The spacer material layer positioned at the upper surface of first mandrel structure, and in the side of the multiple first mandrel structure
Form first clearance wall；And
The protective layer is removed, the upper surface of the spacer material layer in the groove is made using CMP process
With the upper surface flush of first mandrel structure, the remaining spacer material layer is as the fusion using in the groove
Clearance wall.
6. such as the forming method of mask pattern described in any one of claim 1 to 5, which is characterized in that the multiple first heart
Axle construction it is of same size.
7. such as the forming method of mask pattern described in any one of claim 1 to 5, which is characterized in that between the multiple second
Minimum range between gap wall is less than or equal to 32nm.
8. a kind of semiconductor devices, forming method includes the formation side of mask pattern as described in any one of claim 1 to 7
Method, which is characterized in that the multiple continuous non-equally structures formed including substrate and in substrate, it is the multiple continuously to differ
Distance structure at least has one group of continuous three unequal spacing on the direction for being parallel to the substrate surface.
9. semiconductor devices as claimed in claim 8, which is characterized in that the semiconductor devices is fin field effect crystal
Pipe.
10. a kind of integrated circuit, which is characterized in that including semiconductor devices as claimed in claim 8 or 9.
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| CN201810273406.5A CN108511330A (en) | 2018-03-29 | 2018-03-29 | Forming method, semiconductor devices and the integrated circuit of mask pattern |
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