CN108493194B - Array substrate and display panel - Google Patents
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- CN108493194B CN108493194B CN201810269512.6A CN201810269512A CN108493194B CN 108493194 B CN108493194 B CN 108493194B CN 201810269512 A CN201810269512 A CN 201810269512A CN 108493194 B CN108493194 B CN 108493194B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
Abstract
The invention discloses an array substrate and a display panel. The array substrate comprises a first metal layer, a first insulating layer, a second metal layer and a second insulating layer which are sequentially arranged, a first through hole exposing the first metal layer and a second through hole exposing the second metal layer, an auxiliary metal block arranged on the same layer as the second metal layer and an auxiliary through hole exposing the auxiliary metal block, wherein the first through hole, the second through hole and the auxiliary through hole are formed by adopting a one-time etching process. After the second insulating layer is etched, in the process of etching the first insulating layer by forming the first via hole, the sum of the etching areas of the metal exposed by the second via hole and the metal exposed by the auxiliary via hole is larger than the etching area of the metal exposed by the second via hole, so that the etching load on the second metal layer is increased, the etching rate of the second metal layer at the second via hole is reduced, the over-etching of the second via hole is reduced, the increase of the contact resistance between the integrated circuit and the data line is avoided, and the product yield of the display panel is improved.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to an array substrate and a display panel.
Background
The prior TFT-L CD generally adopts a bottom Gate type TFT structure, wherein a grid (Gate) is connected to a scanning line (Scan L ine), a Source (Source) is connected to a Data line (Data L ine), a Drain (Drain) is connected to a Pixel electrode (Pixel electrode), the electrodes at two ends of the Pixel are generally connected to a grid line and the Drain electrode to generate a voltage difference, and peripheral wiring of the display also needs to realize transmission of electric signals through via holes, so the via holes play a vital role in the signal transmission process.
However, in the prior art, when the via hole exposing the drain electrode is formed by using an etching process, an over-etching problem often occurs, so that the yield of the via hole is reduced, the display of the display panel is poor, and the product yield of the display panel is reduced.
Disclosure of Invention
An object of an embodiment of the present invention is to provide an array substrate and a display panel, so as to reduce an etching rate and reduce via over-etching.
In order to solve the technical problem, an embodiment of the present invention provides an array substrate, including a first metal layer, a first insulating layer, a second metal layer, and a second insulating layer sequentially disposed on a substrate, and further including a first via hole exposing the first metal layer and a second via hole exposing the second metal layer, the array substrate further includes an auxiliary metal block disposed on a same layer as the second metal layer and an auxiliary via hole exposing the auxiliary metal block, and the first via hole, the second via hole, and the auxiliary via hole are formed by a one-time etching process.
Optionally, the auxiliary metal block is disposed in a blank area of the non-display area of the array substrate.
Optionally, the auxiliary metal block and the second metal layer are formed by a sequential patterning process.
Optionally, the first via hole, the second via hole and the auxiliary via hole are formed by a dry etching process.
Optionally, the number of the auxiliary metal blocks is multiple, and the multiple auxiliary metal blocks are arranged in a matrix manner.
Optionally, at least one auxiliary via is disposed on each auxiliary metal block.
Optionally, the auxiliary metal block is rectangular, circular, oval or trapezoidal in shape.
Optionally, the cross section of the auxiliary via hole is circular, trapezoidal, elliptical or rectangular.
Optionally, the first metal layer includes scan lines located in the integrated circuit bonding region, the second metal layer includes data lines located in the integrated circuit bonding region, each scan line is provided with a plurality of first via holes arranged in parallel, and each data line is provided with a plurality of second via holes arranged in parallel.
In order to solve the above technical problem, an embodiment of the present invention further provides a display panel, including the array substrate described above.
According to the array substrate provided by the embodiment of the invention, the auxiliary metal block on the same layer as the second metal layer and the auxiliary via hole exposing the auxiliary metal block are arranged, and the first via hole, the second via hole and the auxiliary via hole are formed by adopting a one-time etching process, so that after the second insulating layer is etched, in the process of etching the first insulating layer by forming the first via hole, the sum of the etching areas of the metals exposed by the second via hole and the auxiliary via hole is larger than the etching area of the metal exposed by the second via hole, thus the etching load on the second metal layer is increased, the etching rate of the second metal layer at the second via hole is reduced, the over-etching of the second via hole is reduced, the increase of the contact resistance between the integrated circuit and the data line is avoided, the display panel display defect caused by the increase of the contact resistance is avoided, and the product yield of the display panel is. The array substrate provided by the embodiment of the invention is used for a display panel in an advanced super-dimensional field conversion mode.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a schematic top view illustrating a non-display area of an array substrate in the related art;
FIG. 2 is a schematic cross-sectional view A-A of FIG. 1;
FIG. 3 is a schematic top view of an array substrate according to a first embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view B-B of FIG. 3;
FIG. 5 is a schematic structural diagram illustrating a second embodiment of the present invention after forming a first metal layer and a first insulating layer;
FIG. 6 is a schematic structural diagram illustrating an active layer formed thereon according to a second embodiment of the present invention;
FIG. 7 is a schematic structural diagram illustrating a pixel electrode layer formed according to a second embodiment of the present invention;
FIG. 8 is a schematic structural diagram of a second metal layer and an auxiliary metal block formed according to a second embodiment of the present invention;
FIG. 9 is a schematic structural diagram illustrating a second insulating layer and first, second and auxiliary vias formed in accordance with a second embodiment of the present invention;
fig. 10 is a schematic structural diagram of a second embodiment of the present invention after a common motor layer is formed.
Description of reference numerals:
10-a substrate; 20-a second metal layer; 21-scanning line;
22-a gate electrode; 30-a first insulating layer; 40-an active layer;
50-a pixel electrode layer; 60-a second metal layer; 61-data lines;
62-auxiliary metal block; 63-a source electrode; 64-a drain electrode;
70-a second insulating layer; 81-a first via; 82-a second via;
83-auxiliary vias; 90-common electrode layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
Fig. 1 is a schematic top view illustrating a non-display region of an array substrate in the related art, and fig. 2 is a schematic cross-sectional view illustrating a-a in fig. 1. Referring to fig. 1, the non-display area of the array substrate includes a bonding area 100 of the integrated circuit and a blank area (an area without signal transmission is called a blank area, also called a Dummy area) 200. In order to ensure the uniformity of the array substrate manufacturing process, typically, some simple metal lines 201 and metal blocks 202 are disposed in the blank area 200, as shown in fig. 1. The integrated circuit bonding area 100 has a scan line 21 connected to the gate electrode and a data line 61 connected to the source electrode, and has a first via hole 81 exposing the scan line 21 and a second via hole 82 exposing the data line 61 in the integrated circuit bonding area 100 in order to transmit an electrical signal to the scan line 21 and the data line 61, so that the integrated circuit is electrically connected to the data line 61 and the scan line 21.
Referring to fig. 2, the non-display region includes a scan line 21, a first insulating layer 30, a data line 61, and a second insulating layer 70 sequentially disposed on a substrate 10. The first via hole 81 exposes the scan line 21, and the second via hole 82 exposes the data line 61. Typically, the first via 81 and the second via 82 are simultaneously formed using one etching process. As further seen in fig. 2, the second via 82 is formed by etching only the second insulating layer 70, while the first via 81 is formed by etching both the second insulating layer 70 and the first insulating layer 30. This results in that the second via 82 is always in an over-etched state during the etching of the first insulating layer 30 for forming the first via 81. Moreover, considering the non-uniformity of the various films on the array substrate and the uniformity of the dry etching on the substrate 10, the etching rate is faster at the periphery of the substrate, which results in more serious over-etching of the second via 82 in the bonding region of the integrated circuit, as shown in fig. 2. The over-etching of the second via 82 increases the over-etching of molybdenum (Mo) in the data line 61, which increases the contact resistance between the integrated circuit and the data line, causes poor display of the display panel, and reduces the product yield of the display panel.
In order to solve the problem of over-etching of the second via hole, an embodiment of the invention provides an array substrate. The array substrate comprises a first metal layer, a first insulating layer, a second metal layer and a second insulating layer which are sequentially arranged on a substrate, and further comprises a first through hole exposing the first metal layer and a second through hole exposing the second metal layer, the array substrate further comprises an auxiliary metal block arranged on the same layer as the second metal layer and an auxiliary through hole exposing the auxiliary metal block, and the first through hole, the second through hole and the auxiliary through hole are formed by adopting a one-time etching process.
According to the array substrate provided by the embodiment of the invention, the auxiliary metal block on the same layer as the second metal layer and the auxiliary via hole exposing the auxiliary metal block are arranged, and the first via hole, the second via hole and the auxiliary via hole are formed by adopting a one-time etching process, so that after the second insulating layer is etched, in the process of etching the first insulating layer by forming the first via hole, the sum of the etching areas of the metals exposed by the second via hole and the auxiliary via hole is larger than the etching area of the metal exposed by the second via hole, thus the etching load on the second metal layer is increased, the etching rate of the second metal layer at the second via hole is reduced, the over-etching of the second via hole is reduced, the increase of the contact resistance between the integrated circuit and the data line is avoided, the display panel display defect caused by the increase of the contact resistance is avoided, and the product yield of the display panel is.
The technical contents of the present invention will be described in detail by specific embodiments.
The first embodiment:
fig. 3 is a schematic top view of an array substrate according to a first embodiment of the invention. Fig. 4 is a schematic cross-sectional view of B-B in fig. 3. Referring to fig. 3 and 4, the array substrate includes a first metal layer 20, a first insulating layer 30, a second metal layer 60, and a second insulating layer 70 sequentially disposed on a substrate 10, and further includes a first via 81 exposing the first metal layer 20 and a second via 82 exposing the second metal layer 60. Referring to fig. 3 and 4, the array substrate further includes an auxiliary metal block 62 disposed at the same layer as the second metal layer 60 and an auxiliary via 83 exposing the auxiliary metal block 62, and the first via 81, the second via 82 and the auxiliary via 83 are formed by a single etching process.
As will be appreciated by those skilled in the art, typically, the first metal layer 20 is a gate metal layer and the second metal layer 60 is a source/drain metal layer. The gate metal layer includes a gate electrode and a scan line 21 connected to the gate electrode, the source/drain metal layer includes a source electrode and a data line 61 connected to the source electrode, the first metal layer 20 shown in fig. 4 is the scan line 21 in the gate metal layer, and the second metal layer 60 shown in fig. 4 is the data line 61 in the source/drain metal layer.
In the array substrate provided by the embodiment of the invention, the auxiliary metal block 62 and the auxiliary via hole 83 exposing the auxiliary metal block 62 are arranged on the same layer as the second metal layer 60, and the first via hole 81, the second via hole 82 and the auxiliary via hole 83 are formed by adopting a one-time etching process, so that after the second insulating layer 70 is etched, in the process of etching the first insulating layer 30 by forming the first via hole 81, the sum of the etching areas of the metals exposed by the second via hole 82 and the auxiliary via hole 83 is larger than the etching area of the metal exposed by the second via hole 82, thereby increasing the etching load on the second metal layer, reducing the etching rate of the second metal layer at the second via hole 82, reducing the over-etching of the second via hole, reducing the over-etching of Mo in the second metal layer, namely the source/drain metal layer, avoiding the increase of the contact resistance between the integrated circuit and the data line, and avoiding the poor display of the display panel caused by the increase of the over-etching, the product yield of the display panel is improved.
It will be readily appreciated that the second metal layer typically comprises three metal films, molybdenum-aluminum-molybdenum (Mo-Al-Mo) in sequence, so reducing the over-etching of the second metal layer reduces the over-etching of Mo.
In this embodiment, a dry etching process is used to form the first via hole, the second via hole, and the auxiliary via hole.
Fig. 3 is a schematic top view of a non-display area of an array substrate, which generally includes a bonding area 100 and a blank area 200. In order to avoid the influence of the auxiliary metal blocks on the display effect of the display panel, in the present embodiment, as shown in fig. 3, the auxiliary metal blocks 62 are disposed in the blank area 200 of the non-display area of the array substrate.
In order not to affect the manufacturing process of the array substrate, it is preferable that the auxiliary metal block 62 and the second metal layer 60 are formed by a single patterning process. Therefore, the over-etching of the second via hole is reduced, and the patterning times of the array substrate are not influenced.
As can be seen from fig. 3, the number of the auxiliary metal blocks 62 is plural, and the plural auxiliary metal blocks 62 are arranged in a matrix form in the blank area.
In the present embodiment, the shape of the auxiliary metal block 62 is rectangular, but it is needless to say that the shape of the auxiliary metal block may be a shape which is easy to manufacture, such as a circle, an ellipse, or a trapezoid.
At least one auxiliary via 83 is disposed on each auxiliary metal block 62, so that each auxiliary metal block can be used to increase the metal etching area, further reduce the etching rate of the source/drain metal layer at the second via 82, and further reduce the over-etching of the second via 82.
As can be seen from fig. 3, the auxiliary metal blocks are square at the upper part of the blank area 200, and each auxiliary metal block is provided with one auxiliary via hole, and the auxiliary metal blocks are rectangular at the lower part of the blank area 200, and each auxiliary metal block is provided with 5 auxiliary via holes. It is easy to understand that the shape and arrangement of the auxiliary metal blocks are not limited to those shown in fig. 3, in practical implementation, auxiliary metal blocks with various shapes can be disposed in the blank area 200 according to needs, and the number of auxiliary vias on each auxiliary metal block can also be disposed according to needs as long as the purpose of reducing the over-etching of the second vias can be achieved.
In the present embodiment, the cross section of the auxiliary via 83 is circular, and it is easily understood that in other embodiments, the cross section of the auxiliary via 83 may be any one of trapezoidal, elliptical, rectangular, and the like, which is easy to manufacture.
As can be seen from a comparison between fig. 3 and fig. 1, in the array substrate provided in this embodiment, the first metal layer 20 includes the scan line 21 located in the integrated circuit bonding region, the second metal layer 60 includes the data line 61 located in the integrated circuit bonding region, the first via 81 exposes the scan line 21, and the second via 82 exposes the data line 61. Each scanning line 21 is provided with a plurality of first via holes 81 arranged in parallel, and each data line 61 is provided with a plurality of second via holes 82 arranged in parallel. The first via holes 81 on two adjacent scan lines 21 are arranged in parallel, and the second via holes 82 on two adjacent data lines 61 are arranged in parallel. Due to the arrangement structure, the wiring structure of the integrated circuit binding area is simpler, and the binding connection of the integrated circuit is facilitated.
Second embodiment:
the second embodiment of the invention provides a preparation method of an array substrate. The preparation method comprises the following steps:
s1: sequentially forming a first metal layer and a first insulating layer on a substrate;
s2: forming a second metal layer and an auxiliary metal block on the same layer on the first insulating layer;
s3: forming a second insulating layer on the second metal layer and the auxiliary metal block;
s4: and forming a first via hole exposing the first metal layer, a second via hole exposing the second metal layer and an auxiliary via hole exposing the auxiliary metal block by adopting a one-time etching process.
Wherein the second metal layer and the auxiliary metal block are formed by a one-time patterning process.
And forming a first via hole, a second via hole and an auxiliary via hole by adopting a dry etching process.
Wherein, the auxiliary metal block is positioned in the blank area of the non-display area.
Before forming the second metal layer and the auxiliary metal block on the same layer, the preparation method further comprises the following steps:
forming an active layer on the first insulating layer;
a pixel electrode layer is formed on the active layer.
It is easily understood that the pixel electrode layer may be formed after the second metal layer and the auxiliary metal block are formed on the active layer.
The preparation method also comprises the following steps: and forming a common electrode layer over the pixel electrode layer on the second insulating layer.
The technical solution of the embodiment of the present invention will be described in detail through the preparation process of the array substrate. The "patterning process" in the embodiments includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist, and is a well-established manufacturing process. The deposition may be performed by a known process such as sputtering, evaporation, chemical vapor deposition, etc., the coating may be performed by a known coating process, and the etching may be performed by a known method, which is not particularly limited herein.
And a first metal layer and a first insulating layer are sequentially formed on the substrate by a first patterning process. The method specifically comprises the following steps: depositing a gate metal film on the substrate 10, and coating a layer of photoresist on the gate metal film; exposing and developing the photoresist by adopting a single-tone eye mask, forming an unexposed area at the positions of a gate electrode and a scanning line, reserving the photoresist, and forming a completely exposed area at other positions without the photoresist; and etching the gate metal film in the complete exposure area and stripping the residual photoresist to form a pattern of the first metal layer. A first insulating film is deposited on the substrate on which the above-described pattern is formed, and a first insulating layer 30 is formed, as shown in fig. 5. The first metal layer includes a gate electrode 22 and a scan line 21, the scan line 21 is connected to the gate electrode 22 (not shown), and the scan line 21 extends to the integrated circuit bonding area 100 of the array substrate. The gate metal film may be one or more of platinum Pt, ruthenium Ru, gold Au, silver Ag, molybdenum Mo, chromium Cr, aluminum Al, tantalum Ta, titanium Ti, tungsten W, and the like, and the first insulating film may be a composite layer of silicon nitride SiNx, silicon oxide SiOx, or SiNx/SiOx.
And forming an active layer on the first insulating layer by a second patterning process. The method specifically comprises the following steps: depositing an insulating film on the first insulating layer 30, and coating a layer of photoresist on the active film; exposing and developing the photoresist by adopting a single-tone mask, forming an unexposed area at the pattern position of the active layer, retaining the photoresist, forming a completely exposed area at other positions, and exposing the active film without the photoresist; the active film in the completely exposed region is etched and the remaining photoresist is stripped, forming a pattern of the active layer 40, as shown in fig. 6. The active thin film may be amorphous silicon, polycrystalline silicon, or microcrystalline silicon, or may be a metal Oxide material, and the metal Oxide material may be Indium Gallium Zinc Oxide (IGZO) or Indium Tin Zinc Oxide (ITZO).
And forming a pixel electrode layer on the active layer by a third patterning process. The method specifically comprises the following steps: depositing a pixel electrode film on the substrate on which the active layer 40 pattern is formed, coating a layer of photoresist on the pixel electrode film, exposing and developing the photoresist by adopting a single-tone mask, forming an unexposed area at the position of the pixel electrode layer pattern, reserving the photoresist, forming a completely exposed area at other positions, having no photoresist, and exposing the pixel electrode film; the pixel electrode film in the completely exposed region is etched and the remaining photoresist is stripped, forming a pattern of the pixel electrode layer 40, as shown in fig. 7. The pixel electrode film is made of a transparent conductive material, such as Indium Tin Oxide (ITO).
And a fourth patterning process to form a second metal layer and an auxiliary metal block. The method specifically comprises the following steps: depositing a source/drain metal film on the substrate on which the pixel electrode layer 50 is formed, coating a layer of photoresist on the source/drain metal film, exposing and developing the photoresist by adopting a single-tone mask, forming unexposed areas at the positions of the source electrode, the drain electrode, the data line and the auxiliary metal block pattern, retaining the photoresist, forming completely exposed areas at other positions, and exposing the source/drain metal film without the photoresist; the source/drain metal film of the completely exposed region is etched and the remaining photoresist is glassed to form a source electrode 63, a drain electrode 64, a data line 61 and an auxiliary metal block 62, as shown in fig. 8. The data line 61 is connected to the source electrode 63 (not shown), the data line 61 extends to the integrated circuit bonding area 100 of the array substrate, and the auxiliary metal block 62 is located in the blank area 200 of the non-display area. The source/drain metal film may be one or more of platinum Pt, ruthenium Ru, gold Au, silver Ag, molybdenum Mo, chromium Cr, aluminum Al, tantalum Ta, titanium Ti, tungsten W, etc.
And a fifth composition process is carried out to form a second insulating layer, the first via hole, the second via hole and the auxiliary via hole. The method specifically comprises the following steps: depositing a second insulating film on the substrate on which the second metal layer and the auxiliary metal block pattern are formed, to form a second insulating layer 70; coating a layer of photoresist on the second insulating layer 70, exposing and developing the photoresist by adopting a single-tone mask, forming a complete exposure area at the pattern positions of the first via hole, the second via hole and the auxiliary via hole, exposing the second insulating layer 70 without the photoresist, forming an unexposed area at other positions, and keeping the photoresist; the insulating layer in the completely exposed region is etched by a dry etching process and the remaining photoresist is stripped, thereby forming a first via hole 81 exposing the scan line 21, a second via hole 82 exposing the data line 61, and an auxiliary via hole 83 exposing the auxiliary metal block 62, as shown in fig. 9.
In the process of etching the insulating layer by using the dry etching process, only the second insulating layer 70 is disposed on the data line 61 and the auxiliary metal block 62, and the first insulating layer 30 and the second insulating layer 70 are disposed on the scan line 21, so that the second via 82 exposing the data line 61 and the auxiliary via 83 exposing the auxiliary metal block 62 are formed after the second insulating layer 70 is etched. In the process of etching the first insulating layer 30 by forming the first via hole 81, the sum of the etching areas of the metal exposed by the second via hole 82 and the auxiliary via hole 83 is greater than the etching area of the metal exposed by the second via hole 82, thereby increasing the etching load on the second metal layer, reducing the etching rate of the data line 61 at the second via hole 82, reducing the over-etching of the second via hole 82, and reducing the over-etching of Mo in the second metal layer, i.e., the source/drain metal layer.
And a sixth patterning process, wherein a common electrode layer is formed on the second insulating layer and above the pixel electrode layer. The method specifically comprises the following steps: depositing a common electrode film on the substrate on which the patterns are formed, coating a layer of photoresist on the common electrode film, exposing and developing the photoresist by adopting a single-tone mask, forming an unexposed area at the pattern position of the common electrode layer, reserving the photoresist, forming a completely exposed area at other positions, having no photoresist and exposing the common electrode film; the common electrode film in the completely exposed region is etched and the remaining photoresist is stripped, forming a pattern of the common electrode layer 90, as shown in fig. 10. The common electrode film is made of a transparent conductive material, such as Indium Tin Oxide (ITO).
In this embodiment, the pixel electrodes in the pixel electrode layer 50 are block electrodes, and the common electrodes in the common electrode layer 90 are strip electrodes, but in other embodiments, the pixel electrodes may be strip electrodes, and the common electrodes may be block electrodes, so that the same technical effect may be achieved.
The method for manufacturing an array substrate provided in this embodiment may be used to manufacture an array substrate in an advanced super Dimension switching (ADSDS, ADS) mode.
The third embodiment:
based on the inventive concept of the foregoing embodiments, embodiments of the present invention also provide a display panel including the array substrate employing the foregoing embodiments, or including the pixel circuit employing the foregoing embodiments. The display panel may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
In the description of the embodiments of the present invention, it should be understood that the terms "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
In the description of the embodiments of the present invention, it should be noted that, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. An array substrate comprises a first metal layer, a first insulating layer, a second metal layer and a second insulating layer which are sequentially arranged on a substrate, and further comprises a first through hole exposing the first metal layer and a second through hole exposing the second metal layer, and is characterized by further comprising an auxiliary metal block arranged at the same layer as the second metal layer and an auxiliary through hole exposing the auxiliary metal block, wherein the first through hole, the second through hole and the auxiliary through hole are formed by adopting a one-time etching process; the auxiliary metal block is used for increasing the metal etching area so as to reduce the etching rate of the second metal layer at the second through hole.
2. The array substrate of claim 1, wherein the auxiliary metal block is disposed in a blank area of the non-display area of the array substrate.
3. The array substrate of claim 1, wherein the auxiliary metal block and the second metal layer are formed by a single patterning process.
4. The array substrate of claim 1, wherein the first via, the second via, and the auxiliary via are formed using a dry etching process.
5. The array substrate of claim 1, wherein the number of the auxiliary metal blocks is plural, and the plural auxiliary metal blocks are arranged in a matrix.
6. The array substrate of claim 1, wherein at least one auxiliary via is disposed on each auxiliary metal block.
7. The array substrate of claim 1, wherein the auxiliary metal block is rectangular, circular, oval or trapezoidal in shape.
8. The array substrate of claim 1, wherein the auxiliary via has a cross section of a circular shape, a trapezoid shape, an oval shape or a rectangular shape.
9. The array substrate of claim 1, wherein the first metal layer comprises scan lines in the integrated circuit bonding area, the second metal layer comprises data lines in the integrated circuit bonding area, each scan line has a plurality of first vias arranged in parallel, and each data line has a plurality of second vias arranged in parallel.
10. A display panel comprising the array substrate according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810269512.6A CN108493194B (en) | 2018-03-28 | 2018-03-28 | Array substrate and display panel |
Applications Claiming Priority (1)
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| CN113327939B (en) * | 2021-05-28 | 2023-12-26 | 合肥维信诺科技有限公司 | Array substrate and display panel |
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| CN103064223A (en) * | 2013-01-07 | 2013-04-24 | 京东方科技集团股份有限公司 | Array substrate and display panel |
| CN103811463A (en) * | 2012-11-01 | 2014-05-21 | 辉达公司 | Buried TSVs used for DECAP |
| CN104536174A (en) * | 2015-01-27 | 2015-04-22 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN107329297A (en) * | 2017-08-30 | 2017-11-07 | 上海中航光电子有限公司 | The binding structure and display panel of display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811463A (en) * | 2012-11-01 | 2014-05-21 | 辉达公司 | Buried TSVs used for DECAP |
| CN103064223A (en) * | 2013-01-07 | 2013-04-24 | 京东方科技集团股份有限公司 | Array substrate and display panel |
| CN104536174A (en) * | 2015-01-27 | 2015-04-22 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN107329297A (en) * | 2017-08-30 | 2017-11-07 | 上海中航光电子有限公司 | The binding structure and display panel of display panel |
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