CN108461483B - Embedded capacitor adapter plate packaging structure and manufacturing method - Google Patents
Embedded capacitor adapter plate packaging structure and manufacturing method Download PDFInfo
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- CN108461483B CN108461483B CN201810283286.7A CN201810283286A CN108461483B CN 108461483 B CN108461483 B CN 108461483B CN 201810283286 A CN201810283286 A CN 201810283286A CN 108461483 B CN108461483 B CN 108461483B
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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Abstract
The invention discloses an embedded capacitor adapter plate packaging structure, which comprises: a silicon interposer; the first capacitor electrode is arranged on the first surface of the silicon adapter plate; a package substrate; a second capacitive electrode disposed on the first side of the package substrate, the first capacitive electrode being aligned parallel to the second capacitive electrode; and the capacitor dielectric layer is positioned between the first capacitor electrode and the second capacitor electrode, and the capacitor dielectric layer, the first capacitor electrode and the second capacitor electrode form a complete capacitor structure together.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to an embedded capacitor adapter plate packaging structure and a manufacturing method and other technical fields.
Background
At present, components in portable/mobile consumer electronic devices represented by mobile phones continuously require designers to provide miniaturized and low-cost product solutions. In fact, miniaturization and cost reduction are not contradictory, but complement each other.
For example, discrete passive devices currently account for 90% of the total number of components, 80% of the substrate area, and 70% of the overall cost of the rf module. If Integrated Passive Device (IPD) technology is used, discrete passive devices can be replaced or attached by chips, which has the following main advantages: 1) the electrical property is improved, so that the interconnection between the active device and the passive device, the external interface of the device is shortened, the impedance is lowered, and the parasitic effect is reduced; 2) further miniaturization, the reduction of discrete passive devices significantly reduces the required substrate area, thereby enabling the size of the RF system-in-package module to be greatly reduced; 3) the cost is remarkably low, all processes can be realized at a wafer level, the mass production effect is achieved, and the size of an Integrated Passive Device (IPD) is not limited by the size of a package.
However, the design of the Integrated Passive Device (IPD) on the conventional chip is limited by the chip structure and material, and the electrical performance of the corresponding passive device cannot meet the requirements of high performance and high Q value. For example, the capacitor design in the conventional system-in-package mostly adopts the SMT surface mount type capacitor design, and is limited by the capacitor size and the assembly process requirements, and the SMT capacitor occupies a large space and cannot meet the increasingly miniaturized packaging requirements.
In some advanced packaging processes, an Integrated Passive Device (IPD) design scheme is adopted to manufacture an inductor and a capacitor on a silicon substrate, and the scheme can greatly reduce the occupied area of the passive device, but is limited by the limitations of structures and process materials, and cannot manufacture a capacitor with a high capacitance value.
Accordingly, the present invention is directed to an embedded capacitor interposer package and method of manufacture that at least partially solve or ameliorate the above-mentioned problems.
Disclosure of Invention
To solve the problems in the prior art, according to an embodiment of the present invention, an embedded capacitor interposer package structure is provided, including:
a silicon interposer;
the first capacitor electrode is arranged on the first surface of the silicon adapter plate;
a package substrate;
a second capacitive electrode disposed on the first side of the package substrate, the first capacitive electrode being aligned parallel to the second capacitive electrode; and
and the capacitor dielectric layer, the first capacitor electrode and the second capacitor electrode form a complete capacitor structure together.
In an embodiment of the present invention, the embedded capacitor interposer package structure further includes:
a through silicon via disposed in the silicon interposer; and
and the silicon through hole is electrically interconnected to the first capacitor electrode and/or the silicon adapter plate interconnection circuit.
In an embodiment of the present invention, the embedded capacitor interposer package structure further includes:
a package substrate interconnect circuit disposed on the first side of the package substrate;
a package substrate through-hole disposed in the package substrate; and
an external bonding pad disposed on a second side of the package substrate opposite the first side of the package substrate, the package substrate via electrically interconnected to the second capacitive electrode and/or the package substrate interconnect circuit.
In an embodiment of the present invention, the embedded capacitor interposer package structure further includes:
a chip disposed on the second side of the silicon interposer;
leads electrically interconnecting the chip and/or the silicon interposer and/or the package substrate; and
and the plastic packaging layer is positioned on the first surface of the packaging substrate and wraps the silicon adapter plate, the chip and the lead.
In an embodiment of the present invention, the embedded capacitor interposer package structure further includes an external solder ball disposed on the external pad.
In one embodiment of the invention, the silicon interposer interconnect circuitry comprises interconnect lines and or chip pads and or wire pads.
In one embodiment of the invention, the package substrate interconnect circuitry comprises interconnect lines and or wire bond pads.
According to another embodiment of the present invention, a method for manufacturing an embedded capacitor interposer package structure is provided, which includes:
forming a first capacitance electrode on a first surface of the silicon interposer;
forming a second capacitor electrode on the first surface of the package substrate; and
the first surface of the silicon adapter plate is attached to the first surface of the packaging substrate through a dielectric material, the first capacitor electrode and the second capacitor electrode are aligned in parallel, the middle of the first capacitor electrode and the middle of the second capacitor electrode are filled with the dielectric material, and the dielectric material, the first capacitor electrode and the second capacitor electrode form a complete capacitor structure together.
In another embodiment of the present invention, the method further comprises:
forming a silicon through hole in the silicon adapter plate;
forming an interconnection circuit and a bonding pad on a second surface of the silicon interposer opposite to the first surface of the silicon interposer;
forming a package substrate interconnection circuit on the package substrate first side;
forming a packaging substrate through hole in the packaging substrate; and
and externally connecting a bonding pad on a second surface of the packaging substrate opposite to the first surface of the packaging substrate.
In another embodiment of the present invention, the method further comprises:
mounting a chip on the second surface of the silicon adapter plate;
completing electrical interconnection among the chip, the silicon interposer and the package substrate by wire bonding;
forming a plastic packaging layer covering the chip, the adapter plate and the lead; and
and forming external solder balls on the external bonding pads of the packaging substrate.
The invention provides an embedded capacitor adapter plate packaging structure and a manufacturing method thereof, based on a traditional packaging structure, a silicon adapter plate and a PCB structure are combined, two electrode structures of a capacitor are formed between the silicon adapter plate and the PCB structure, then a capacitor medium between two electrodes is combined to form an integrated capacitor, and then the electrical and signal interconnection between the integrated capacitor and a chip, the adapter plate and a PCB substrate is realized through a subsequent lead process, so that the system-level interconnection relation is realized. The embedded capacitor adapter plate packaging structure has the advantages that the capacitor does not need extra occupied space, and the smaller packaging size can be ensured; a large-area capacitor structure is adopted, so that a high capacitance value is realized; the capacitance dielectric material between the two electrodes of the capacitor has wide selection range, and can realize the adjustment of larger capacitance value range.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 illustrates a cross-sectional view of an embedded capacitive interposer package 100 according to one embodiment of the present invention.
Fig. 2A-2G illustrate cross-sectional projection views of a process for forming an embedded capacitive interposer package 100 according to one embodiment of the present invention.
Fig. 3 illustrates a flow diagram for forming an embedded capacitive interposer package 100 according to one embodiment of the present invention.
Fig. 4 illustrates a cross-sectional view of an embedded capacitive interposer package 400 according to another embodiment of the present invention.
Detailed Description
In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that, in the embodiments of the present invention, the process steps are described in a specific order, however, this is only for convenience of distinguishing the steps, and the order of the steps is not limited, and in different embodiments of the present invention, the order of the steps may be adjusted according to the adjustment of the process.
The invention provides an embedded capacitor adapter plate packaging structure and a manufacturing method thereof, based on a traditional packaging structure, a silicon adapter plate and a PCB structure are combined, two electrode structures of a capacitor are formed between the silicon adapter plate and the PCB structure, then a capacitor medium between two electrodes is combined to form an integrated capacitor, and then the electrical and signal interconnection between the integrated capacitor and a chip, the adapter plate and a PCB substrate is realized through a subsequent lead process, so that the system-level interconnection relation is realized. The embedded capacitor adapter plate packaging structure has the advantages that the capacitor does not need extra occupied space, and the smaller packaging size can be ensured; a large-area capacitor structure is adopted, so that a high capacitance value is realized; the capacitance dielectric material between the two electrodes of the capacitor has wide selection range, and can realize the adjustment of larger capacitance value range.
An embedded capacitor interposer package structure according to an embodiment of the present invention is described in detail below with reference to fig. 1. Fig. 1 is a schematic cross-sectional view illustrating an embedded capacitor interposer package structure 100 according to an embodiment of the invention, as shown in fig. 1, the embedded capacitor interposer package structure 100 further includes a silicon interposer 101, a first capacitor electrode 102, a through silicon via 103, a silicon interposer interconnect circuit 104, a package substrate 105, a second capacitor electrode 106, a package substrate interconnect circuit 107, a package substrate through hole 108, an external connection pad 109, a capacitor dielectric layer 110, a first chip 111, a second chip 112, a first lead 113, a second lead 114, a molding compound layer 115, and an external connection solder ball 116.
In one embodiment of the invention, the first capacitive electrode 102, the through silicon via 103, and the silicon interposer interconnect circuit 104 are all attached to the silicon interposer 101. The specific structural relationship is as follows:
in another embodiment of the present invention, a conductive trace (not shown) is further disposed on the first surface of the silicon interposer 101, and the conductive trace has an electrical and/or signal interconnection function.
One or more sets of through-silicon vias 103 are formed inside the silicon interposer 101, wherein at least one set of through-silicon vias 103 forms an electrical interconnection with the first capacitive electrode 102. In yet another embodiment of the present invention, still other conductive vias form electrical and/or signal interconnections with the conductive traces on the first side of the silicon interposer 101.
On a second face of the silicon interposer 101 opposite to the first face on which the first capacitance electrode 102 is located, a silicon interposer interconnect circuit 104 is formed. In one embodiment of the present invention, the silicon interposer interconnect circuitry 104 includes interconnect circuitry, chip pads, wire bond pads, etc., to form an electrical and/or signal interconnect interface between the silicon interposer and the chip and subsequent package substrates.
In one embodiment of the invention, the second capacitive electrode 106, the package substrate interconnect circuitry 107, the package substrate via 108 and the external pad 109 are all attached to the package substrate 105, the material of the package substrate 105 being a PCB. The specific structural relationship is as follows:
a second capacitance electrode 106 is formed on the first surface of the packaging substrate 105, and a packaging substrate interconnection line 107 is arranged on the first surface of the packaging substrate 105, so that electric and/or signal interconnection with the silicon adapter plate 101 and the chip is realized; wherein the position of the second capacitive electrode 106 is horizontally aligned with the position of the first capacitive electrode 102 as shown in fig. 1.
A plurality of groups of package substrate through holes 108 are formed in the package substrate 105, wherein at least one group of package substrate through holes 108 is electrically interconnected with the second capacitor electrode 106; at least one other set of package substrate vias 108 forms an electrical interconnection with the package substrate interconnect lines 107.
The capacitor dielectric layer 110 is disposed between the first surface of the package substrate 105 and the first surface of the silicon interposer 101, and is made of an insulating dielectric material, which functions as a capacitor dielectric between electrodes and also functions as a mechanical bond.
The first chip 111 and the second chip 112 are attached at corresponding positions on the second side of the silicon interposer 101. The first chip 111 and the second chip 112 form electrical and/or signal interconnections with the silicon interposer 101 through the first leads.
In another embodiment of the present invention shown in fig. 4, fig. 4 is a schematic cross-sectional view of an embedded capacitor interposer package 400 according to another embodiment of the present invention. As shown in fig. 4, the first chip 402 and the second chip 403 are flip-chip bonded to the silicon interposer 401 by bumps, solder balls, or copper pillars 404.
In addition, the silicon interposer interconnect circuitry 104 on the silicon interposer 101 is electrically connected to the package substrate interconnect lines 107 on the package substrate 105 by second leads 114 to form electrical and/or signal interconnections between the chip, the silicon interposer, and the package substrate. In yet another embodiment of the present invention, there may also be leads electrically connected directly from the chip to the package substrate (not shown in the figures).
The plastic encapsulation layer 115 covers the first surface of the package substrate 105, and encapsulates the silicon interposer 101, the chip 111/112, the first lead 113, the second lead 114, and the capacitor dielectric layer together to form a complete electrical insulation and mechanical protection function.
The process of forming an embedded capacitor interposer package 100 is described in detail below with reference to fig. 2A-2G and fig. 3. Fig. 2A-2G illustrate cross-sectional projection views of a process for forming an embedded capacitive interposer package 100 according to one embodiment of the present invention; fig. 3 illustrates a flow diagram for forming an embedded capacitive interposer package 100 according to one embodiment of the present invention.
First, in step 301, as shown in fig. 2A, a first capacitor electrode 102, a through silicon via 103, an interconnection circuit, and a pad 104 are formed on a silicon interposer 101. In an embodiment of the present invention, the first capacitor electrode 102 is formed on the first surface of the silicon interposer 101 by a patterned electroplating process, and optionally an interconnect circuit (not shown) may also be formed; and then through-hole and electroplating processes are performed to form a conductive through-silicon-via 103 and an interconnection circuit and a pad 104 on a second surface of the silicon interposer 101 opposite to the first surface. To meet the requirements of finer and more systematic packaging, a multi-layer interconnect circuit (not shown) can be formed on the second side of the silicon interposer 101 to meet the design requirements.
Next, in step 302, as shown in fig. 2B, the second capacitance electrode 106, the package substrate interconnection circuit 107, the package substrate via 108, and the external connection pad 109 are formed on the package substrate 105. In an embodiment of the present invention, the package substrate 105 is made of a PCB, the second capacitor electrode 106 and the package substrate interconnection circuit 107 are formed on the first surface of the package substrate 105 by a patterned electroplating process, and the package substrate interconnection circuit 107 may further include a pad required for wire bonding; and forming a package substrate through hole 108 and an external bonding pad 109 through processes of laser through hole, electroplating and the like. To meet finer and more systematic packaging requirements, a multilayer interconnection circuit (not shown) may also be formed on the first and/or second side of the package substrate 105 to meet design requirements.
Then, in step 303, as shown in fig. 2C, the silicon interposer 101 is mounted onto the package substrate 105 through a dielectric material. After mounting, a capacitor dielectric layer 110 is formed between the first capacitor electrode 102 of the silicon interposer 101 and the second capacitor electrode 106 of the package substrate 105, and the material thereof is an insulating dielectric material, which on one hand functions as a capacitor dielectric between electrodes and on the other hand functions as a mechanical adhesive. In addition, a dielectric material with a corresponding dielectric constant can be selected according to the requirement of the Q value of the capacitor, so that the requirement is met.
Next, at step 304, a chip is mounted on the second side of the silicon interposer 101, as shown in fig. 2D. In one embodiment of the present invention, one or more chips 111/112 are mounted as needed, where the chips are mounted by SMT. In yet another embodiment of the present invention, the chip may also be flip-chip bonded to the silicon interposer, as shown in fig. 4, and the chip 402 and the chip 403 are flip-chip bonded to the silicon interposer 401 through solder balls.
Then, in step 305, as shown in fig. 2E, the electrical interconnection between the chip 111/112, the silicon interposer 101, and the package substrate 105 is completed by wire bonding. In one embodiment of the present invention, die 111/112 and silicon interposer 101 are electrically interconnected first by leads 113, and silicon interposer 101 and package substrate 105 are electrically interconnected by leads 114. In other embodiments of the present invention, the objects of its wire bonding may be flexible, such as wire bonding electrically interconnecting the chip and the package substrate.
Next, at step 306, a molding layer for protecting the chip, the interposer and the leads is formed as shown in fig. 2F. The plastic encapsulation layer 115 covers the package substrate 105, and encapsulates the silicon interposer 101, the chip 111/112, the first lead 113, the second lead 114, and the capacitor dielectric layer together to form a comprehensive electrical insulation and mechanical protection function.
Finally, in step 307, as shown in fig. 2G, external solder balls 116 are formed on the external pads 109 of the package substrate 105. In one embodiment of the present invention, the external solder balls 116 are formed by a ball-mounting and reflow process.
The invention provides an embedded capacitor adapter plate packaging structure and a manufacturing method thereof, based on a traditional packaging structure, a silicon adapter plate and a PCB structure are combined, two electrode structures of a capacitor are formed between the silicon adapter plate and the PCB structure, then a capacitor medium between two electrodes is combined to form an integrated capacitor, and then the electrical and signal interconnection between the integrated capacitor and a chip, the adapter plate and a PCB substrate is realized through a subsequent lead process, so that the system-level interconnection relation is realized. The embedded capacitor adapter plate packaging structure has the advantages that the capacitor does not need extra occupied space, and the smaller packaging size can be ensured; a large-area capacitor structure is adopted, so that a high capacitance value is realized; the capacitance dielectric material between the two electrodes of the capacitor has wide selection range, and can realize the adjustment of larger capacitance value range.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (10)
1. An embedded capacitor interposer package structure, comprising:
a silicon interposer;
the first capacitor electrode is arranged on the first surface of the silicon adapter plate;
a package substrate;
a second capacitive electrode disposed on the first side of the package substrate, the first capacitive electrode being aligned parallel to the second capacitive electrode; and
the first surface of the silicon adapter plate is attached to the first surface of the packaging substrate through the dielectric material, the first capacitor electrode and the second capacitor electrode are aligned in parallel, the middle of the first capacitor electrode and the middle of the second capacitor electrode are filled with the dielectric material, and the dielectric material, the first capacitor electrode and the second capacitor electrode form a complete capacitor structure together.
2. The embedded capacitor interposer package of claim 1, further comprising:
a through silicon via disposed in the silicon interposer; and
and the silicon through hole is electrically interconnected to the first capacitor electrode and/or the silicon adapter plate interconnection circuit.
3. The embedded capacitor interposer package of claim 1, further comprising:
a package substrate interconnect circuit disposed on the first side of the package substrate;
a package substrate through-hole disposed in the package substrate; and
an external bonding pad disposed on a second side of the package substrate opposite the first side of the package substrate, the package substrate via electrically interconnected to the second capacitive electrode and/or the package substrate interconnect circuit.
4. The embedded capacitor interposer package of claim 1, further comprising:
a chip disposed on the second side of the silicon interposer;
leads electrically interconnecting the chip and/or the silicon interposer and/or the package substrate; and
and the plastic packaging layer is positioned on the first surface of the packaging substrate and wraps the silicon adapter plate, the chip and the lead.
5. The embedded capacitor interposer package of claim 3 further comprising external solder balls disposed on the external pads.
6. The embedded capacitance interposer package of claim 2 wherein the silicon interposer interconnect circuitry comprises interconnect lines and or chip pads and or lead pads.
7. The embedded capacitance interposer package of claim 3 wherein the package substrate interconnect circuitry comprises interconnect lines and or wire bond pads.
8. A manufacturing method of an embedded capacitor interposer package structure comprises the following steps:
forming a first capacitance electrode on a first surface of the silicon interposer;
forming a second capacitor electrode on the first surface of the package substrate; and
the first surface of the silicon adapter plate is attached to the first surface of the packaging substrate through a dielectric material, the first capacitor electrode and the second capacitor electrode are aligned in parallel, the middle of the first capacitor electrode and the middle of the second capacitor electrode are filled with the dielectric material, and the dielectric material, the first capacitor electrode and the second capacitor electrode form a complete capacitor structure together.
9. The method of claim 8, further comprising:
forming a silicon through hole in the silicon adapter plate;
forming an interconnection circuit and a bonding pad on a second surface of the silicon interposer opposite to the first surface of the silicon interposer;
forming a package substrate interconnection circuit on the package substrate first side;
forming a packaging substrate through hole in the packaging substrate; and
and externally connecting a bonding pad on a second surface of the packaging substrate opposite to the first surface of the packaging substrate.
10. The method of claim 8, further comprising:
mounting a chip on the second surface of the silicon adapter plate;
completing electrical interconnection among the chip, the silicon interposer and the package substrate by wire bonding;
forming a plastic packaging layer covering the chip, the adapter plate and the lead; and
and forming external solder balls on the external bonding pads of the packaging substrate.
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| CN201810283286.7A CN108461483B (en) | 2018-04-02 | 2018-04-02 | Embedded capacitor adapter plate packaging structure and manufacturing method |
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| CN201810283286.7A CN108461483B (en) | 2018-04-02 | 2018-04-02 | Embedded capacitor adapter plate packaging structure and manufacturing method |
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| CN112234027A (en) * | 2020-10-14 | 2021-01-15 | 天津津航计算技术研究所 | 2.5D electronic packaging structure |
| CN114720733B (en) * | 2022-06-08 | 2022-09-09 | 南通江海电容器股份有限公司 | Solid-liquid mixed aluminum electrolytic capacitor life test switching PCB |
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| US5672911A (en) * | 1996-05-30 | 1997-09-30 | Lsi Logic Corporation | Apparatus to decouple core circuits power supply from input-output circuits power supply in a semiconductor device package |
| US6985349B2 (en) * | 2001-12-13 | 2006-01-10 | Harris Corporation | Electronic module including a low temperature co-fired ceramic (LTCC) substrate with a capacitive structure embedded therein and related methods |
| KR100716824B1 (en) * | 2005-04-28 | 2007-05-09 | 삼성전기주식회사 | Printed circuit board with embedded capacitors using hybrid materials, and manufacturing process thereof |
| JP4838068B2 (en) * | 2005-09-01 | 2011-12-14 | 日本特殊陶業株式会社 | Wiring board |
| US20160055976A1 (en) * | 2014-08-25 | 2016-02-25 | Qualcomm Incorporated | Package substrates including embedded capacitors |
| CN104505386A (en) * | 2014-12-30 | 2015-04-08 | 中国科学院微电子研究所 | Lateral-interconnection package on package structure |
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