CN108449086A - A kind of multi-channel high-speed universal serial bus transmitting terminal parallel port synchronous method, circuit and chip - Google Patents
A kind of multi-channel high-speed universal serial bus transmitting terminal parallel port synchronous method, circuit and chip Download PDFInfo
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/181—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
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Abstract
The present invention relates to transmitting terminal parallel port synchronous method, circuit and chips in a kind of multi-channel high-speed universal serial bus.In the prior art, it usually realizes that parallel port synchronizes using caching, and caches and often occupy more chip area, increase cost.Circuit/chip of the present invention has only used several logic gates, coordinates automatic phase-detection, and parallel clock phase is dynamically adjusted in practical work process and realizes that port synchronizes.Using method of the present invention, circuit and chip, solve the problems, such as parallel port synchronization and cross clock domain simultaneously, it avoids and uses buffer, reduce resource overhead and link delay, the phase relation between clock is automatically adjusted in practical work process, guarantee system is not influenced by voltage, temperature and process deviation.
Description
Technical field
The invention belongs to IC design fields, and in particular to physical layer design in high-speed serial bus, especially its
The method of the synchronization of transmitting terminal parallel data port, circuit and chip in physical layer.
Background technology
In the communications field, serial communication refers to the communication mode of primary only transmission a data when sending data.Now,
More and more parallel bus structures are substituted by universal serial bus, such as PCIe, SATA and USB etc..Universal serial bus usually with
For SerDes as physical layer, communication media is usually the cabling on printed circuit board, backboard or cable etc..Communication uses
Point-to-point topological structure, difference cabling, and in the absence of clock deviate the problem of.Not needing to clock signal follows data simultaneously
It sends simultaneously, receiving terminal can receive data from extracting data and recovered clock.
The design of high-speed serial bus often uses multi-channel structure to improve bandwidth, and if PCIe often uses 2 channels, 4 is logical
The structure in road or even 32 channels.Multi-channel structure often also faces the problem of time domain deviates between channel, main offset source
In communication media, often a caching for going offset is realized in receiving terminal to cope with this problem.But caching is often
More chip area is occupied, design cost is improved, all kinds of agreements would generally strictly limit the maximum clock offset of transmitting terminal, core
Piece design has to comply with protocol requirement.It requires the time domain of transmitting terminal to deviate in PCIe forth generation agreements and was less than for 1.25 nanoseconds.Respectively
The class agreement of requirement in to(for) multichannel transmitting terminal clock skew in high-speed serial bus is often below the period of parallel clock, example
Such as when parallel bit wide is 16 or 32, the parallel clock cycle number of PCIe physical layer and upper layer connection is all received in 2 nanoseconds to 4
In second range, if to accomplish that the time domain less than 1.25ns deviates, it is desirable to cannot between parallel data port plurality of passages
There are time sequence differences.
The prior art would generally allow when physical layer initializes all channels while generating parallel clock, makes simultaneously
These parallel clocks phases are approximate, time sequence difference is not present when ensureing parallel data port mutual transmission data.
But since the area that multichannel occupies on chip is larger, often there is process deviation between channel and channel, actually answering
With the drift situation that can also face voltage and temperature in the process, cause the failure of clock synchronous initiation or initialize successfully it
Afterwards, in practical work process, with the variation of temperature and voltage, there are synchronization failure, cross clock domain in some or certain channels
Situations such as problem, occurs, and eventually leads to entire communication link connection failure.
Invention content
In view of the deficiencies in the prior art, the object of the present invention is to provide a kind of transmissions of multi-channel high-speed universal serial bus
Hold parallel port synchronous method, circuit and chip.The circuit/chip has only used several logic gates, coordinates automatic phase-detection,
Parallel clock phase is dynamically adjusted in practical work process realizes that port synchronizes.Using method of the present invention, circuit and
Chip, at the same solve the problems, such as parallel port synchronize and cross clock domain, avoid using buffer, reduce resource overhead with
Link delay automatically adjusts the phase relation between clock in practical work process, ensures system not by voltage, temperature and work
The influence of skill deviation.
To achieve the above objectives, the technical solution adopted by the present invention is：A kind of multi-channel high-speed universal serial bus transmitting terminal is simultaneously
Row port synchronous method, includes the following steps：
S1, phase lock loop locks generate local high-frequency clock；
S2, it selects an output clock as system master clock from the output clock of each transmitting terminal transmission channel, passes
It send to each transmitting terminal transmission channel；
S3, each transmitting terminal transmission channel to be transmitted into row information is chosen, each transmitting terminal transmission channel in being elected to
After detecting phase lock loop locks, initialized into row clock, tranmitting data register ready signal；
S4, by each transmitting terminal transmission channel send each clock prime carry out with operation obtain all reset when
The clock prime of clock ready signal, all reset is sampled using system master clock, is obtained in system master clock domain
Synchronous enabled signal is sent to each transmitting terminal transmission channel chosen；
S5, each transmitting terminal transmission channel chosen generate the adjustment of clock using synchronous enabled signal as frequency divider
Signal starts frequency divider, generates frequency-dividing clock, the output clock as each transmitting terminal transmission channel；
The phase difference value of S6, comparison system master clock and the output clock in transmitting terminal channel；
S7, when phase difference value be more than or less than threshold value when, adjust output clock phase, with keep system master clock with output
The phase difference that clock is kept fixed reaches clock synchronization.
Further, the specific method of the comparison system master clock and the phase difference value of the output clock in transmitting terminal channel
To carry out phase demodulation by phase discriminator, comparing phase difference, the specific phase difference value of counter records.
Further, the phase discriminator is JK flip-flop or Hogge phase discriminators.
Further, the specific method of the adjustment output clock phase is that phase difference value is maintained at 3~4 local high
Between the fast clock cycle, when phase difference value is more than 2, keep the output clock phase in channel motionless；When phase difference value be less than etc.
When 2, moved after the output clock phase in channel.
A kind of multi-channel high-speed universal serial bus transmitting terminal parallel port synchronous circuit, the circuit include：Phaselocked loop, clock letter
Number selecting unit, multiple transmitting terminal transmission channels, synchronous enabled generation unit；And transmitting terminal transmission channel further include frequency divider,
Phase comparator, phase controller and string data converter；
The phaselocked loop connects multiple transmitting terminal transmission channels for generating local high-speed clock signal, phaselocked loop；
The clock signal selection unit, for selecting an output from the output clock of multiple transmitting terminal transmission channels
Clock signal sends each transmitting terminal transmission channel to as system master clock；
The transmitting terminal transmission channel, which is used to work as, detects phase lock loop locks, and transmitting terminal transmission channel is initial into row clock
Change, and to synchronous enabled generation unit tranmitting data register ready signal；
The synchronous enabled generation unit, the clock prime for sending each channel chosen carries out and fortune
It calculates, obtains the clock prime of all reset, the clock prime of all reset is subjected to system master clock sampling again, is obtained
Synchronous enabled signal in system master clock domain；
The transmitting terminal transmission channel and string data converter, for the data of system in parallel port to be converted to serially
Data are in channel transfer；
The frequency divider of the transmitting terminal transmission channel is carried out based on local high-frequency clock according to synchronous enabled signal enabling
Frequency dividing generates output clock of the frequency-dividing clock as the transmitting terminal transmission channel；
The phase comparator of the transmitting terminal transmission channel receives output clock, the system master clock that frequency divider generates, and
Phase controller is connected, the phase difference value for comparison system master clock and the output clock of transmitting terminal transmission channel；
Phase controller connection frequency divider, phase comparator and the phaselocked loop of the transmitting terminal transmission channel, for working as phase
When potential difference value is more than or less than threshold value, the local high-frequency clock phase of phaselocked loop is adjusted, so as to adjust output clock phase.
Further, phase comparator includes phase discriminator and two phase counters, carries out phase demodulation by phase discriminator, compares phase
Potential difference records specific phase difference value by two phase counters.
Further, the phase discriminator is JK flip-flop or Hogge phase discriminators.
Further, the phase controller adjustment output clock phase specific method is that phase difference value is maintained at 3~4
Between a local high-frequency clock period, when phase difference value is more than 2, keep the output clock phase in channel motionless；Work as phase difference
When value is less than or equal to 2, moved after the output clock phase in channel.
A kind of multi-channel high-speed universal serial bus transmitting terminal parallel port synchronizing chip, arrangement include as described above mostly logical
Road high-speed serial bus transmitting terminal parallel port synchronous circuit.
Effect of the invention is that using method of the present invention and circuit, solves in high-speed serial bus and send
The stationary problem of parallel port is held, following advantage is shared：
1) while parallel port synchronization and cross clock domain being solved the problems, such as, avoids using buffer, reduces resource
Expense and link delay；
2) system layer implementation is easy, and expense is small, only several and gate logic and latch；
3) in practical work process automatically adjust clock between phase relation, ensure system not by voltage, temperature and
The influence of process deviation.
Description of the drawings
Fig. 1 is the flow chart of multi-channel high-speed universal serial bus transmitting terminal parallel port synchronous method of the present invention；
Fig. 2 is the structure principle chart of multi-channel high-speed universal serial bus transmitting terminal parallel port synchronous circuit of the present invention；
Fig. 3 is the sequence diagram that multi-channel high-speed universal serial bus transmitting terminal parallel port of the present invention synchronizes.
Specific implementation mode
The invention will be further described with reference to the accompanying drawings and detailed description.
As shown in Figure 1, a kind of multi-channel high-speed universal serial bus transmitting terminal parallel port synchronous method, includes the following steps：
S1, phase lock loop locks generate local high-frequency clock, connect each transmitting terminal transmission channel；
S2, when selecting the output clock in a channel main as system from the output clock of each transmitting terminal transmission channel
Clock is sent to each transmitting terminal transmission channel, carries out parallel data transmission；
S3, each transmitting terminal transmission channel to be transmitted into row information is chosen, each transmitting terminal transmission channel in being elected to
It after detecting phase lock loop locks, is initialized into row clock, resets frequency divider, tranmitting data register ready signal；
S4, by each transmitting terminal transmission channel send each clock prime carry out with operation obtain all reset when
The clock prime of clock ready signal, all reset is sampled using system master clock, is obtained in system master clock domain
Synchronous enabled signal is sent to each transmitting terminal transmission channel chosen；
S5, each transmitting terminal transmission channel chosen generate the adjustment of clock using synchronous enabled signal as frequency divider
Signal starts frequency divider, generates frequency-dividing clock, and as the output clock of each transmitting terminal transmission channel, i.e., each channel generates
Simultaneously and concurrently clock；
The phase difference value of S6, comparison system master clock and the output in channel clock；
S7, when phase difference value be more than or less than threshold value when, adjust output clock phase, with keep system master clock with output
The phase difference that clock is kept fixed reaches clock synchronization.
In the present embodiment, the specific method of the phase difference value of the output clock in comparison system master clock and channel is to pass through
Phase discriminator carries out phase demodulation, compares phase difference, records specific phase difference value.
In the present embodiment, transmitting terminal transmission channel can be 1~n, n>=2；
In the present embodiment, system master clock is sent to the frequency divider of each transmitting terminal transmission channel by d type flip flop, described
System master clock is used for the transmission of parallel data in system parallel-serial conversion, clock prime sampling, phase difference value sampling, will believe
Number timing control is in system master clock domain.
In the present embodiment, phaselocked loop connects the frequency divider of each transmitting terminal transmission channel, works as phase lock loop locks, generates local
High-speed clock signal, each transmitting terminal transmission channel detects phase lock loop locks, and the modules in channel are initial into row clock
Change, resets frequency divider.
In the present embodiment, each transmitting terminal transmission channel to be carried out data transmission is selected, phase lock loop locks are worked as, it is selected
The parallel serial conversion unit of each transmitting terminal transmission channel sends out clock prime respectively, and each clock prime is sent
To with door, carry out and operation, since the clock initialization time of each transmission channel is different, each clock prime of generation
Also there is certain delay, by generating the clock prime of all reset with operation, can be ensured by the signal selected
Each transmission channel completed by divider reset, that is, clock initialization, when the clock prime of all reset is main using system
Clock samples, and generates the synchronous enabled signal in system master clock domain, sends each transmission channel to.Synchronous enabled signal transmission
To the parallel-to-serial converter in transmission channel, parallel-to-serial converter is started to work.
In the present embodiment, frequency divider generates the adjustment signal of clock using synchronous enabled signal as frequency divider, according to synchronization
Enable signal starts frequency divider, and frequency divider is based on local high-frequency clock and is divided, generates frequency-dividing clock and transmitted as transmitting terminal
The output clock of the output clock in channel, the transmitting terminal transmission channel is divided for receiving the serial data after parallel-serial conversion
Device connects phase comparator and phase controller；
In the present embodiment, as shown in figure 3, since synchronous enabled signal is to sample to obtain by system master clock, and frequency divider
The output clock signal of generation is generated by synchronous enabled signal, is divided based on local high-frequency clock, first in local high-frequency clock
3 times 2 frequency dividings are carried out on the basis of frequency dividing, that is, when output of 8 fractional frequency signals of local high-frequency clock as transmitting terminal channel
Clock signal, then exporting clock signal and system master clock signal has fixed phase intervals, simultaneously as metastable deposit
Synchronous enabled signal has prolonged 2~3 high-frequency clock periods in master clock domain so that export the rising edge of clock signal with
There are the fixed intervals in 1~3 high-frequency clock period for the failing edge of master clock signal, and the fixed intervals are usually at hundreds of picoseconds
To between one or two of nanosecond, such interval can ensure that the data of system in parallel can directly use channel when being sent into channel
It exports clock and receives data, remain optimal settling time and retention time, solve the problems, such as cross clock domain, the present invention can be with
Set fixed intervals to 3~4 high-frequency clock periods.
In the present embodiment, the specific method of the phase difference value of the output clock in the comparison system master clock and channel is,
Phase demodulation is carried out by phase discriminator, compares phase difference, specific phase difference value is recorded by phase counter.
In the present embodiment, the circuit of the phase comparator of the output clock and system master clock phase that compare channel is provided
It is, including a phase discriminator and a phase counter.Method can be：Phase demodulation is carried out by a JK flip-flop, is compared
The output rising edge clock and the actual phase difference value of system master clock failing edge in channel.Other linear phase discriminators, such as Hogge
Phase discriminator etc. may serve to realize this function.Phase difference value is counted by phase counter, records specific phase difference
Value measures the practical duration of two clock skews.For the low power dissipation design of circuit, set phase counter to
Two bit architectures are saturated after counting down to 3, and to prevent from causing mistake after overflowing, count value is between 0~3.It is relatively low in power consumption requirements
System in counter can be given to more bit wides, improve the precision of adjusting.Count results are obtained by system master clock sampling
Phase difference value.When phase difference value is less than or equal to 2, we can think that the rising edge of the output clock in channel is non-
Very close to the rising edge of system master clock, the nargin at this time leaving the retention time for is just very small.The phase difference value of generation, meeting
It is sent to phase controller, to control the phase of phaselocked loop high-frequency clock, and then adjusts the phase for exporting clock in channel after frequency dividing.
The control rule of phase controller is：
When phase difference value is more than 2, keep the output clock phase in channel motionless.
It when phase difference value is less than or equal to 2, moves after the output clock phase in channel, allows the output in system master clock and channel
Clock is maintained at 3~4 clock cycle.
In the present embodiment, if the output clock in channel is very high, that is, frequency divider frequency division system it is smaller when
It waits, 2 fractional frequency signals based on local high-frequency clock as shown in Figure 3, it may appear that the rising edge of the output clock in channel is ahead of
The case where failing edge of system master clock, it may appear that cross clock domain problem causes data not to be ready in time just according to output
Clock is received, and data also will be disorderly at this time.In this case, it needs in addition to increase a phase bits comparison module, in turn
The phase difference value for comparing output rising edge clock and system master clock failing edge is when phase difference value is positive value, i.e., logical when finding
In the case that the output clock in road is advanced, the Phase delay that phase control module will export clock can be controlled.
As shown in Fig. 2, a kind of multi-channel high-speed universal serial bus transmitting terminal parallel port synchronous circuit, the circuit include：
Phaselocked loop, clock signal selection unit, multiple transmitting terminal transmission channels, synchronous enabled generation unit；And transmitting terminal
Transmission channel further includes frequency divider, phase comparator, phase controller and string data converter,
In the present embodiment, the multiple transmitting terminal transmission channel can be 1~n, n>=2, it gives in the present embodiment
Channel 0, channel 1, channel 2, channel 3, specific embodiment is as shown in channel 1.Frequency divider produces in each transmitting terminal transmission channel
Raw output clock is connected to clock signal selection unit；
The clock signal selection unit selects an output clock from the output clock of multiple transmitting terminal transmission channels
Signal sends each transmitting terminal transmission channel to as system master clock,
In the present embodiment, the system master clock that clock signal selection unit generates is sent to the frequency dividing of each transmission channel
Device, simultaneity factor master clock are additionally operable to the transmission of parallel data, the clock prime sampling of all reset, phase comparator phase
Difference samples, by signal sequence control in system master clock domain.
Phaselocked loop connects multiple transmitting terminal transmission channels for generating local high-speed clock signal, phaselocked loop, and transmitting terminal passes
Defeated channel is used to, when detecting phase lock loop locks, the modules of transmitting terminal transmission channel be initialized into row clock, reset and divide
Frequency device, and to synchronous enabled generation unit tranmitting data register ready signal, specifically, that phaselocked loop connects each transmission channel and go here and there
Data converter, frequency divider, it is when each transmission channel detects phase lock loop locks, the modules in channel are initial into row clock
Change, resets frequency divider；
Transmission channel and string data converter, for by the data of system in parallel port be converted to serial data high speed
It is transmitted in serial transmission line, i.e., multi-bit parallel data is converted into multiple 1 serial data and carries out list bit and transmitted, in transmitting terminal,
Transformed serial data is received with the output clock that transmission channel generates；
In the present embodiment, and string data converter is additionally operable to, and works as phase lock loop locks, selected each transmission channel and go here and there
Data converter sends out clock prime respectively.
In the present embodiment, synchronous enabled generation unit receives the clock prime in each channel, progress and operation, due to
The clock initialization time of each transmission channel is different, and each clock prime of generation also has certain delay, passes through
The clock prime that all reset is generated with operation can ensure selected each transmission by the clock prime of all reset
Divider reset, that is, clock initialization has been completed in channel, and the clock prime of all reset is sampled using system master clock,
The synchronous enabled signal in system master clock domain is generated, sends each transmission channel to.Synchronous enabled signal sends transmission to
Parallel-to-serial converter in channel, parallel-to-serial converter are started to work.
The frequency divider of transmitting terminal transmission channel is the synchronous enabled signal enabling point generated according to synchronous enabled generation unit
Frequency device, frequency divider are based on local high-frequency clock and are divided, and generate output of the frequency-dividing clock as the transmitting terminal transmission channel
Clock；
In the present embodiment, the frequency divider generates the adjustment signal of clock using synchronous enabled signal as frequency divider, according to
Synchronous enabled signal enabling frequency divider, frequency divider are based on local high-frequency clock and are divided, and generate frequency-dividing clock as the hair
The output clock of sending end transmission channel, frequency divider connect phase comparator and phase controller；
In the present embodiment, as shown in figure 3, since synchronous enabled signal is to sample to obtain by system master clock, and frequency divider
The output clock signal of generation is generated by synchronous enabled signal, is divided based on local high-frequency clock, first in local high-frequency clock
3 times 2 frequency dividings are carried out on the basis of frequency dividing, that is, when output of 8 fractional frequency signals of local high-frequency clock as transmitting terminal channel
Clock signal, then exporting clock signal and system master clock signal has fixed phase intervals, simultaneously as metastable deposit
Synchronous enabled signal has prolonged 2~3 high-frequency clock periods in master clock domain so that export the rising edge of clock signal with
There are the fixed intervals in 1~3 high-frequency clock period for the failing edge of master clock signal, and the fixed intervals are usually at hundreds of picoseconds
To between one or two of nanosecond, such interval can ensure that the data of system in parallel can directly use channel when being sent into channel
It exports clock and receives data, remain optimal settling time and retention time, solve the problems, such as cross clock domain, the present invention can be with
Set fixed intervals to 3 high-frequency clock periods.
The phase comparator of transmitting terminal transmission channel receives output clock information, the system master clock letter that frequency divider generates
Number, and phase controller is connected, the phase difference value for comparison system master clock and the output clock in channel；
Phase controller connection frequency divider, phase comparator and the phaselocked loop of transmitting terminal transmission channel, work as phase for described
When potential difference value is more than or less than threshold value, the local high-frequency clock phase of phaselocked loop is adjusted, after being divided so as to adjust frequency divider
Output clock phase；
In the present embodiment, due to the influence of voltage, temperature and process deviation, in system practical work process, when output
The fixed phase intervals of clock and system master clock can change, and interval is shorter or longer can all have asking for cross clock domain
Topic, data can not be normally received by the output clock in channel, influence the stationary problem of cross clock domain port.It is asked to solve this
It inscribes, a phase bits comparison module can be realized in each channel, relatively export the phase difference of clock and system master clock in real time, sentence
The changing value of disconnected phase difference can adjust automatically output clock in channel when phase difference changing value is more than or less than a certain threshold value
Phase, so that the variation of the phase intervals of the failing edge of output rising edge clock and system master clock is maintained at 1 high-frequency clock
Within period, then if setting fixed intervals to 3 high-frequency clock periods, in real work, output rising edge clock and
The phase intervals of the failing edge of system master clock were maintained within 4 high-frequency clock periods.Phase bits comparison module can be in system work
As when continue to monitor the phase relations of two clocks, after the phase difference variation when between the two is more than 1 high-frequency clock period,
Channel can automatically adjust the phase of output clock, to maintain system stable operation.
In the present embodiment, a kind of phase ratio for the output clock and system master clock phase comparing channel in the channel is provided
Circuit compared with device is, including a phase discriminator and a phase counter.Method can be：It is reflected by a JK flip-flop
Phase compares the output rising edge clock and the actual phase difference value of system master clock failing edge in channel.Other linear phase demodulations
Device, such as Hogge phase discriminators may serve to realize this function.Phase difference value is counted by phase counter, record tool
The phase difference value of body measures the practical duration of two clock skews.For the low power dissipation design of circuit, by phasometer
Number device is set as two bit architectures, is saturated after counting down to 3, and to prevent from causing mistake after overflowing, count value is between 0~3.In work(
Consumption requires that counter can be given to more bit wides in lower system, improves the precision of adjusting.When count results are main by system
Clock sampling obtains phase difference value.When phase difference value is less than or equal to 2, we can think the upper of the output clock in channel
The rising edge along very close system master clock is risen, the nargin at this time leaving the retention time for is just very small.It generates
Phase difference value can be sent to phase controller, to control the phase of phaselocked loop high-frequency clock, and then adjust the output in channel after frequency dividing
The phase of clock.Phase controller is the clock that a kind of analog circuit can generate various phases by four phase clocks, including
270 ° of 0 ° of PLLCLK, 90 ° of PLLCLK, 180 ° of PLLCLK, PLLCLK phases.The control rule of phase controller is：
When phase difference value is more than 2, keep the output clock phase in channel motionless.
It when phase difference value is less than or equal to 2, moves after the output clock phase in channel, allows the output in system master clock and channel
Clock is maintained at 3~4 clock cycle.
In the present embodiment, if the output clock in channel is very high, that is, frequency divider frequency division system it is smaller when
It waits, 2 fractional frequency signals based on local high-frequency clock as shown in Figure 3, it may appear that the rising edge of the output clock in channel is ahead of
The case where failing edge of system master clock, it may appear that cross clock domain problem causes data not to be ready in time just according to output
Clock is received, and data also will be disorderly at this time.In this case, it needs in addition to increase a phase bits comparison module, in turn
The phase difference value for comparing output rising edge clock and system master clock failing edge is when phase difference value is positive value, i.e., logical when finding
In the case that the output clock in road is advanced, the Phase delay that phase control module will export clock can be controlled.
It will be understood by those skilled in the art that method and system of the present invention is not limited to institute in specific implementation mode
The embodiment stated, specific descriptions above are intended merely to explain the purpose of the present invention, are not intended to limit the present invention.This field skill
Art personnel can derive other implementation manners according to the technical scheme of the present invention, and also belong to the scope of the technical innovation of the present invention, this
The protection domain of invention is limited by claim and its equivalent.
Claims (9)
1. a kind of multi-channel high-speed universal serial bus transmitting terminal parallel port synchronous method, which is characterized in that include the following steps：
S1, phase lock loop locks generate local high-frequency clock；
S2, it selects an output clock as system master clock from the output clock of each transmitting terminal transmission channel, is sent to
Each transmitting terminal transmission channel；
S3, each transmitting terminal transmission channel to be transmitted into row information is chosen, each transmitting terminal transmission channel detection in being elected to
To after phase lock loop locks, initialized into row clock, tranmitting data register ready signal；
S4, the clock that each clock prime that each transmitting terminal transmission channel is sent obtain with operation all reset are accurate
Standby signal, the clock prime of all reset are sampled using system master clock, obtain the synchronization in system master clock domain
Enable signal is sent to each transmitting terminal transmission channel chosen；
The adjustment that S5, each transmitting terminal transmission channel chosen generate clock using synchronous enabled signal as frequency divider is believed
Number, start frequency divider, generates frequency-dividing clock, the output clock as each transmitting terminal transmission channel；
The phase difference value of S6, comparison system master clock and the output clock in transmitting terminal channel；
S7, when phase difference value be more than or less than threshold value when, adjust output clock phase, with keep system master clock with output clock
The phase difference being kept fixed reaches clock synchronization.
2. a kind of multi-channel high-speed universal serial bus transmitting terminal parallel port synchronous method as described in claim 1, feature exist
In：The specific method of the comparison system master clock and the phase difference value of the output clock in transmitting terminal channel is to pass through phase discriminator
Phase demodulation is carried out, phase difference, the specific phase difference value of counter records are compared.
3. a kind of multi-channel high-speed universal serial bus transmitting terminal parallel port synchronous method as claimed in claim 2, feature exist
In：The phase discriminator is JK flip-flop or Hogge phase discriminators.
4. a kind of multi-channel high-speed universal serial bus transmitting terminal parallel port synchronous method as described in claim 1, feature exist
In：The specific method of the adjustment output clock phase is, by phase difference value be maintained at 3~4 local high-frequency clock periods it
Between, when phase difference value is more than 2, keep the output clock phase in channel motionless；When phase difference value is less than or equal to 2, channel
It is moved after output clock phase.
5. a kind of multi-channel high-speed universal serial bus transmitting terminal parallel port synchronous circuit, which is characterized in that including：Phaselocked loop, when
Clock signal behavior unit, multiple transmitting terminal transmission channels, synchronous enabled generation unit；The transmitting terminal transmission channel further includes point
Frequency device, phase comparator, phase controller and string data converter；
The phaselocked loop connects multiple transmitting terminal transmission channels for generating local high-speed clock signal, phaselocked loop；
The clock signal selection unit, for selecting an output clock from the output clock of multiple transmitting terminal transmission channels
Signal sends each transmitting terminal transmission channel to as system master clock；
The transmitting terminal transmission channel is used to, when detecting phase lock loop locks, transmitting terminal transmission channel be initialized into row clock,
And to synchronous enabled generation unit tranmitting data register ready signal；
The synchronous enabled generation unit, the clock prime for sending each channel chosen carries out and operation, obtains
To the clock prime of all reset, the clock prime of all reset is subjected to system master clock sampling again, is obtained in system
Synchronous enabled signal in master clock domain；
The transmitting terminal transmission channel and string data converter, for the data of system in parallel port to be converted to serial data
In channel transfer；
The frequency divider of the transmitting terminal transmission channel is divided based on local high-frequency clock according to synchronous enabled signal enabling
Frequently, output clock of the frequency-dividing clock as the transmitting terminal transmission channel is generated；
The phase comparator of the transmitting terminal transmission channel receives output clock, the system master clock that frequency divider generates, and connects
Phase controller, the phase difference value for comparison system master clock and the output clock of transmitting terminal transmission channel；
Phase controller connection frequency divider, phase comparator and the phaselocked loop of the transmitting terminal transmission channel, for working as phase difference
When value is more than or less than threshold value, the local high-frequency clock phase of phaselocked loop is adjusted, so as to adjust output clock phase.
6. a kind of multi-channel high-speed universal serial bus transmitting terminal parallel port synchronous circuit as claimed in claim 5, feature exist
In：Phase comparator includes phase discriminator and two phase counters, carries out phase demodulation by phase discriminator, compares phase difference, pass through two
Position phase counter records specific phase difference value.
7. a kind of multi-channel high-speed universal serial bus transmitting terminal parallel port synchronous circuit as claimed in claim 6, feature exist
In：The phase discriminator is JK flip-flop or Hogge phase discriminators.
8. a kind of multi-channel high-speed universal serial bus transmitting terminal parallel port synchronous circuit as claimed in claim 5, feature exist
In：The phase controller adjustment output clock phase specific method is, when phase difference value is maintained at 3~4 local high speeds
Between the clock period, when phase difference value is more than 2, keep the output clock phase in channel motionless；When phase difference value is less than or equal to 2
When, it moves after the output clock phase in channel.
9. a kind of multi-channel high-speed universal serial bus transmitting terminal parallel port synchronizing chip, which is characterized in that it arranges to include as weighed
Profit requires a kind of any multi-channel high-speed universal serial bus transmitting terminal parallel port synchronous circuits of 5-8.
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