CN108445818B

CN108445818B - Data interaction intelligent terminal system and communication method

Info

Publication number: CN108445818B
Application number: CN201810505809.8A
Authority: CN
Inventors: 赵明; 陈敬茹
Original assignee: Individual
Current assignee: Individual
Priority date: 2018-05-19
Filing date: 2018-05-19
Publication date: 2023-12-12
Anticipated expiration: 2038-05-19
Also published as: CN108445818A

Abstract

The invention relates to a data interaction intelligent terminal system and a communication method, wherein a host terminal comprises a core control unit, a DIDO isolation card circuit, an AI isolation card circuit, an AO isolation card circuit, a co-processing unit interface circuit, a serial port isolation card circuit, a comprehensive communication card circuit, a man-machine interaction circuit, a PWM counter isolation board circuit, an IO expansion card circuit and a power management unit; the terminal system comprises a data interaction intelligent host terminal, a data bus and 1 st slave terminals to N th slave terminals; the communication method is to use the main module of the beacon relay to communicate with the slave module of the beacon relay; the invention has flexible splicing property; the invention has the characteristics of high-efficiency and strong secondary development and the characteristics of high-efficiency and convenient secondary machine expansion; the host computer is separated from the mode of selecting the slave computer through the communication bus, the original bidirectional response type communication is changed into a relay response mode, and the communication instantaneity is improved; the invention has stronger anti-interference capability and stability, and can realize cascade infinite expansion by plug and play of the slave.

Description

Data interaction intelligent terminal system and communication method

Technical Field

The invention relates to a data interaction intelligent terminal system and a communication method, and belongs to the technical field of automatic control.

Background

The industry often collects signals from devices or automatically controls devices, and various controllers and signal types are used by the industry, which requires a controller or medium capable of connecting with various devices, where the types of signals connected to the controller or medium need to cover DI (digital input), DO (digital output), AI (analog input), AO (analog output), and various serial communication data signals (such as 485 communication, CAN communication, ethernet, etc.). The existing processing mode is generally as follows: 1. a PLC was used. The PLC has simple use and high reliability, but has high cost, the system structure is closed, each PLC manufacturer also has a hundred-family dispute, the hardware systems are mutually incompatible, the programming languages and instruction systems are different, when a user selects one PLC product, the control rules corresponding to the PLC product are required to be selected, and the specific programming language is required to be learned. This clearly extends the development cycle, which is particularly evident in places where personnel flow is frequent; 2. and purchasing some general modules for secondary research and development. Although the control sites have various signals, the emphasis of different control sites is different, which makes it difficult to apply a control medium to various communication occasions, and developers of the control medium often need to purchase different modules for different industrial sites for developing different control devices; both the above two modes can cause waste of human resources and material resources to a certain extent. Moreover, although the electronic product is convenient to use, the electronic product has large potential harm to the environment and low recovery rate, and is unfavorable for ecological civilization development today with increasingly serious environmental problems.

Disclosure of Invention

Aiming at the problems, the invention provides the data interaction intelligent terminal system and the communication method by taking the thought of the type printing operation into consideration, so that the functional decomposition is realized while the requirements of an industrial site are not influenced, each functional module is independently formed, and the functional modules are assembled according to the requirements when in use, so that the utilization rate of electronic products is greatly improved.

The technical scheme adopted by the invention is as follows:

the intelligent host terminal comprises a core control unit, a DIDO isolation card circuit, an AI isolation card circuit, an AO isolation card circuit, a co-processing unit interface circuit, a serial port isolation card circuit, a comprehensive communication card circuit, a man-machine interaction circuit, a PWM counter isolation board circuit, an IO expansion card circuit and a power management unit; the core control unit is in bidirectional connection with a corresponding port of the serial port isolation card circuit, and the serial port isolation card circuit is in bidirectional connection with a serial port signal port to be tested; the core control unit is in bidirectional connection with a corresponding port of the integrated communication card circuit, and the integrated communication card circuit is in bidirectional connection with a serial digital signal port; the core control unit is in bidirectional connection with a corresponding port of the IO expansion card circuit, and the IO expansion card circuit is in bidirectional connection with a port of the multifunctional data interaction intelligent slave terminal; the core control unit is in bidirectional connection with a corresponding port of the co-processing unit interface circuit, a first input end of the co-processing unit interface circuit is connected with an intrusion detection and interrupt input signal port, a first output end of the co-processing unit interface circuit is connected with a corresponding input end of the man-machine interaction circuit, and a second output end of the co-processing unit interface circuit is connected with a corresponding input end of the PWM counter isolation board circuit; the man-machine interaction circuit is connected with the corresponding port of the core control unit in a bidirectional manner; the core control unit is in bidirectional connection with the corresponding port of the PWM counter isolation board circuit, and the pulse signal port to be tested is in bidirectional connection with the corresponding port of the PWM counter isolation board circuit; the output end of the core control unit is connected with the input end of a corresponding port of the AO isolation card circuit, and the output end of the AO isolation card circuit is connected with an analog control signal port; the input end of the AI isolation card circuit is connected with an analog signal port to be measured, and the output end of the AI isolation card circuit is connected with the corresponding input end of the core control unit; the DIDO isolation card circuit is in bidirectional connection with a corresponding port of the core control unit, and the DIDO isolation card circuit is in bidirectional connection with a corresponding port of the switch signal port; the output end of the power management unit is respectively connected with corresponding power ports of the core control unit, the DIDO isolation card circuit, the AI isolation card circuit, the AO isolation card circuit, the co-processing unit interface circuit, the serial port isolation card circuit, the comprehensive communication card circuit, the man-machine interaction circuit, the PWM counter isolation board circuit and the IO expansion card circuit, and the input end of the power management unit is connected with an external power supply.

The data interaction intelligent host terminal also comprises a main board and first to tenth circuit boards; the co-processing unit interface circuit is arranged on the main board; the core control unit is arranged on the first circuit board; the DIDO isolation card circuit is arranged on the second circuit board; the AI isolation card circuit is arranged on the third circuit board; the AO isolation card circuit is arranged on the fourth circuit board; the serial port isolation card circuit is arranged on the fifth circuit board; the integrated communication card circuit is arranged on the sixth circuit board; the man-machine interaction circuit is arranged on the seventh circuit board; the PWM counter isolation board circuit is arranged on the eighth circuit board; the IO expansion card circuit is arranged on the ninth circuit board; the power management unit is arranged on the tenth circuit board; the first to tenth circuit boards are connected with the main board in a plugging mode.

An assembled data interaction intelligent terminal system comprises a data interaction intelligent host terminal, a data bus, a 1 st slave terminal and an N th slave terminal, wherein N is an integer greater than 1; the structures of the 1 st slave terminal to the N th slave terminal are the same, and the expansion forms from the 1 st slave terminal to the N th slave terminal are cascade connection; the data interaction intelligent host terminal is connected with the Nth slave terminal through the 1 st slave terminal, the 2 nd slave terminal, … and the N-1 th slave terminal in sequence; and the data interaction intelligent host terminal, the 1 st slave terminal and the N th slave terminal are respectively connected to the data bus.

The communication method by utilizing the assembled data interaction intelligent terminal system utilizes the communication between the beacon relay main module and the beacon relay slave module, and comprises the following specific steps:

(1) The core processing unit is initialized, so that the pin of the selection signal input end FH of the beacon relay main module is low level, and the pin of the clock signal input end CLK of the beacon relay main module is high level;

(2) The embedded chip 1U1 sends a selection signal to a pin of a selection signal input end FH of the honeycomb relay main module, namely, sends a high level;

(3) The embedded chip 1U1 sends a clock signal of one period, namely high level-low level-high level, to a pin of a clock signal input end CLK of the honeycomb relay main module;

(4) The embedded chip 1U1 sends a clearing signal, namely a low level, to a pin of a selection signal input end FH of the honeycomb relay main module, and clears a slave address i;

(5) The embedded chip 1U1 sends a clock signal of one period to a pin of a clock signal input end CLK of the beacon relay master module, and increases the slave address i by 1;

(6) The embedded chip 1U1 detects whether the slave addresses i are larger than the limit number m of the slaves, if so, the step (7) is executed, otherwise, the step (8) is executed;

(7) When the beacon relay slave module is abnormal, outputting an abnormal notification;

(8) The embedded chip 1U1 judges whether a termination signal is received or not, the pin of the feedback signal output end FHFK of the beacon relay main module sends a selection signal to be low level, if not, the step (9) is executed, otherwise, the step (10) is executed;

(9) The embedded chip 1U1 outputs a read-write data notification, and then jumps to step (5);

(10) The embedded chip 1U1 judges whether the slave address i exceeds the number n of the data interaction intelligent slave terminals detected by the beacon relay master module, if so, the step (2) is skipped, otherwise, the step (11) is executed;

(11) The embedded chip 1U1 outputs an on-line and off-line notification of the slave terminal;

(12) Resetting the number n of the data interaction intelligent slave terminals as i-1, and jumping to the step (2);

in the above steps, i is the slave address; n is the number of slave terminals; m is the limit number of slave terminals; wherein, the value range of i is 1-100, the value range of n is 1-100, and the value range of m is 1-100.

The beneficial effects of the invention are as follows: the invention has flexible assembly characteristic, can replace PLC to work, and has highly flexible secondary development performance, AI, AO, DI, DO, serial communication interface to the core control unit, provide flexible user expansion module interface, users can design the isolation circuit or other functional circuits by themselves according to the actual demand, this makes the whole architecture like the open system, can be improved conveniently; also, like lettering, there is no need to carry out a new production of the whole set of circuit boards due to local improvement; the invention has high-efficiency and strong secondary development characteristic, and the NET Micro Framework embedded system is carried, so that the object-oriented design idea is applied to hardware development, software developers can quickly enter from a PC development end of C#, net/VB.NET, and the hardware system is developed by using high productivity of Visual Studio without professional hardware development engineers, thereby reducing labor cost for enterprises of secondary development; the invention has the characteristic of efficient and convenient slave expansion, the data interaction host terminal and the data interaction expansion slave terminal integrate a special beacon relay module, and a special signal transmission mode (named as a beacon power method) is used, so that the host is separated from a mode of selecting the slave through a communication bus, and the slave can automatically connect the communication bus to send data after detecting a relay signal, thus the original bidirectional response communication is changed into a relay response mode, the host is not used for shouting, the slave automatically responds, and the communication instantaneity is improved; the slave terminal served by the system does not need to have a programmable MCU, and compared with MCU series, the system has stronger anti-interference capability and stability; the slave can be plugged and used only by using 4 wires including a power wire and a ground wire, so that the theoretical cascading infinite extension book is realized; the invention is suitable for various industries such as steel, petroleum, chemical industry, electric power, building materials, machinery manufacturing, automobiles, light spinning, transportation, environmental protection and the like, and can be used for all automatic control fields requiring switching value logic control, process control, data processing and communication networking.

Drawings

FIG. 1 is a schematic block diagram of a data interaction intelligent host terminal of the present invention;

FIG. 2 is a schematic circuit diagram of a power management unit according to the present invention;

FIG. 3 is a schematic circuit diagram of a core control unit of the present invention;

FIG. 4 is a schematic circuit diagram of an IO expansion bus communication circuit of the present invention;

fig. 5 is a schematic circuit diagram of the inventive tower relay master module circuit;

FIG. 6 is a schematic circuit diagram of a first serial port isolation card circuit of the present invention;

FIG. 7 is a schematic circuit diagram of a first AI isolation circuit of the invention;

FIG. 8 is a circuit schematic of the AO isolation card circuit of the present invention;

FIG. 9 is a schematic circuit diagram of a parallel-to-serial conversion input circuit according to the present invention;

FIG. 10 is a schematic circuit diagram of a serial-to-parallel output circuit of the present invention;

FIG. 11 is a schematic circuit diagram of a first DO driving circuit of the present invention;

FIG. 12 is a schematic circuit diagram of a first DO isolation circuit of the invention;

FIG. 13 is a schematic circuit diagram of a first DI isolation circuit according to the present invention;

FIG. 14 is a schematic circuit diagram of a DIDO isolation circuit of the invention;

FIG. 15 is a schematic circuit diagram of a PWM counter spacer circuit of the present invention;

FIG. 16 is a schematic circuit diagram of a first human-computer interaction circuit of the present invention;

FIG. 17 is a schematic circuit diagram of a second man-machine interaction circuit according to the present invention

FIG. 18 is a schematic circuit diagram of a serial circuit of the present invention;

FIG. 19 is a circuit schematic of the CAN bus circuit of the invention; the method comprises the steps of carrying out a first treatment on the surface of the

FIG. 20 is a schematic block diagram of an assembled data interaction intelligent terminal system of the present invention;

FIG. 21 is a schematic block diagram of a 1 st slave terminal of the present invention;

FIG. 22 is a schematic circuit diagram of the present invention of a tower relay slave circuit;

fig. 23 is a circuit diagram of a bus controller of the present invention.

Detailed Description

1-23, it can be seen that it relates to a data interaction intelligent host terminal, including a core control unit, a DIDO isolation card circuit, an AI isolation card circuit, an AO isolation card circuit, a co-processing unit interface circuit, a serial port isolation card circuit, a comprehensive communication card circuit, a man-machine interaction circuit, a PWM counter isolation board circuit, an IO expansion card circuit and a power management unit; the core control unit is in bidirectional connection with a corresponding port of the serial port isolation card circuit, and the serial port isolation card circuit is in bidirectional connection with a serial port signal port to be tested; the core control unit is in bidirectional connection with a corresponding port of the integrated communication card circuit, and the integrated communication card circuit is in bidirectional connection with a serial digital signal port; the core control unit is in bidirectional connection with a corresponding port of the IO expansion card circuit, and the IO expansion card circuit is in bidirectional connection with a port of the multifunctional data interaction intelligent slave terminal; the core control unit is in bidirectional connection with a corresponding port of the co-processing unit interface circuit, a first input end of the co-processing unit interface circuit is connected with an intrusion detection and interrupt input signal port, a first output end of the co-processing unit interface circuit is connected with a corresponding input end of the man-machine interaction circuit, and a second output end of the co-processing unit interface circuit is connected with a corresponding input end of the PWM counter isolation board circuit; the man-machine interaction circuit is connected with the corresponding port of the core control unit in a bidirectional manner; the core control unit is in bidirectional connection with the corresponding port of the PWM counter isolation board circuit, and the pulse signal port to be tested is in bidirectional connection with the corresponding port of the PWM counter isolation board circuit; the output end of the core control unit is connected with the input end of a corresponding port of the AO isolation card circuit, and the output end of the AO isolation card circuit is connected with an analog control signal port; the input end of the AI isolation card circuit is connected with an analog signal port to be measured, and the output end of the AI isolation card circuit is connected with the corresponding input end of the core control unit; the DIDO isolation card circuit is in bidirectional connection with a corresponding port of the core control unit, and the DIDO isolation card circuit is in bidirectional connection with a corresponding port of the switch signal port; the output end of the power management unit is respectively connected with corresponding power ports of the core control unit, the DIDO isolation card circuit, the AI isolation card circuit, the AO isolation card circuit, the co-processing unit interface circuit, the serial port isolation card circuit, the comprehensive communication card circuit, the man-machine interaction circuit, the PWM counter isolation board circuit and the IO expansion card circuit, and the input end of the power management unit is connected with an external power supply.

The power management unit consists of a chip U1, a chip U5, a chip U8, a voltage stabilizing tube D101, an inductor L101, a capacitor C101-capacitor C105 and a resistor R101-resistor R104; the model of the chip U1 is MP2403, the model of the chip U5 is APL117-3.3, the model of the chip U8 is DC1212, and the model of the voltage stabilizing tube D101 is SS14;

the input pin 2 of the chip U1 is connected with an external power supply WB; the output pin 3 of the chip U1 is used as an output end +5V through an inductor L101; the capacitor C101 is connected between the input pin 2 of the chip U1 and the ground, the voltage regulator tube D101 is connected between the output pin 3 of the chip U1 and the ground, the capacitor C102 is connected between the pin 1 and the pin 3 of the chip U1, the pin 4 of the chip U1 is grounded, the pin 5 of the chip U1 is connected with the output end +5V through the resistor R102, the resistor R101 is connected between the pin 5 of the chip U1 and the ground, the capacitor C104 is connected between the pin 6 of the chip U1 and the ground after being connected with the resistor R103 in series, the capacitor C105 is connected between the output end +5V and the ground, the resistor R104 is connected between the pin 7 and the pin 2 of the chip U1, and the capacitor C103 is connected between the pin 8 of the chip U1 and the ground;

The input end Vin of the chip U5 is connected with the output end +5V, the output end Vout of the chip U5 is the output end +3.3V, and the grounding end of the chip U5 is grounded;

the input pin 2 of the chip U8 is connected with an external power supply WB, the pins 1 and 3 of the chip U8 are grounded, and the pin 4 of the chip U8 is an output end +12V;

the core control unit comprises an embedded chip 1U1, a peripheral component switch 1S2, a crystal oscillator 1Y101-1Y102, a resistor 1R101-1R103, a capacitor 1C101-1C107, a data latch 1U2-1U3 and an inverter chip 1U8; the embedded chip 1U1 is an embedded chip with the model STM32F103ZET6 implanted with a Net Micro Framwork micro-frame, a reset circuit composed of a switch 1S2, a resistor 1R103 and a capacitor 1C105 is connected between 25 pins of the embedded chip 1U1 and the ground, a first crystal oscillator circuit composed of a crystal oscillator 1Y102, a resistor 1R102 and a capacitor 1C103-1C104 is connected between 23 pins and 24 pins of the embedded chip 1U1, and a second crystal oscillator circuit composed of a crystal oscillator 1Y101, a resistor 1R101 and a capacitor 1C101-1C102 is connected between 8 pins and 9 pins of the embedded chip 1U 1; the model of the data latch 1U2-1U3 is 74HC573, the input pin 2 pin-9 pin of the data latch 1U2 is respectively connected with the pin 86, the pin 85, the pin 114, the pin 115, the pin 58, the pin 59, the pin 60 and the pin 63 of the embedded chip 1U1, the pin 10 of the data latch 1U2 is grounded, and the pin 20 of the data latch 1U2 is connected with the output end +3.3V; the input pins 2-9 of the data latch 1U3 are respectively connected with the pins 64-68 and 77-79 of the embedded chip 1U1, the pin 10 of the data latch 1U3 is grounded, and the pin 20 of the data latch 1U3 is connected with the output end +3.3V; the model of the inverter chip 1U8 is 74LVC2G04, the 1 pin of the inverter chip 1U8 is connected with the 137 pin of the embedded chip 1U1, the 3 pin of the inverter chip 1U8 is connected with the 110 pin of the embedded chip 1U1, the 6 pin of the inverter chip 1U8 is connected with the 11 pin of the data latch 1U2 and the 11 pin of the data latch 1U3, the 2 pin of the inverter chip 1U8 is grounded, and the 5 pin of the inverter chip 1U8 is connected with the output end +3.3V;

The core control unit further comprises a chip 1U4, a chip 1U5 and a chip 1U7;

the model of the chip 1U4 IS an external expansion SRAM chip SRAM-IS62WV51216BLL, and the 7 pin-10 pin, the 13 pin-16 pin, the 29 pin-32 pin and the 35 pin-38 pin of the chip 1U4 are respectively connected with the 86 pin, the 85 pin, the 114 pin, the 115 pin, the 58 pin-60 pin, the 63 pin-68 pin and the 77 pin-79 pin of the embedded chip 1U 1; the pins 19-22, 24-27, 42-44 and 1-5 of the chip 1U4 are respectively connected with the pins 12-19 and 12-19 of the data latch 1U3 and 1U 2; the 18 pins, the 23 pins and the 28 pins of the chip 1U4 are respectively connected with the 80 pins to 82 pins of the embedded chip 1U 1; the 6 feet, 17 feet and 39 feet-41 feet of the chip 1U4 are respectively connected with the 123 feet, 119 feet, 41 feet-42 feet and 118 feet of the embedded chip 1U 1; the power supply terminal 11 pin and 33 pin of the chip 1U4 are connected with the output terminal +3.3V, the capacitor 1C401 is connected between the 11 pin of the chip 1U4 and the ground, the capacitor 1C402 is connected between the 33 pin of the chip 1U4 and the ground, and the resistor 1R401 is connected between the 6 pin of the chip 1U4 and the output terminal +3.3V;

the model of the chip 1U5 is an external FLASH chip MX29LV320, and the 29, 31, 33, 35, 38, 40, 42, 44, 30, 32, 34, 36, 39, 41, 43 and 45 pins of the chip 1U5 are respectively connected with the 86, 85, 114, 115, 58-60, 63-68 and 77-79 pins of the embedded chip 1U 1; the 1 pin-8 pin and the 18 pin-25 pin of the chip 1U5 are respectively connected with the 12 pin-19 pin of the output pin of the data latch 1U3, and the 12 pin-19 pin of the output pin of the data latch 1U 2; the 48 feet, 17 feet, 16 feet and 9 feet-10 feet of the chip 1U5 are respectively connected with the 80 feet-82 feet and 2 feet-3 feet of the embedded chip 1U 1; the 11 pin, the 12 pin, the 15 pin, the 28 pin and the 26 pin of the chip 1U5 are respectively connected with the 119 pin, the 25 pin, the 122 pin, the 118 pin and the 125 pin of the embedded chip 1U 1; the 14 pins of the chip 1U5 are connected with the output end +3.3V through a resistor 1R502, the 15 pins of the chip 1U5 are connected with the output end +3.3V through a resistor 1R501, the 37 pins of the chip 1U5 are connected with the output end +3.3V, and a filter capacitor 1C501 is connected between the 37 pins of the chip 1U5 and the ground;

The chip 1U7 is an external memory MT29F1G08, and pins 29-32, 41-44, 26-28, 33, 40 and 45-47 of the chip 1U7 are respectively connected with pins 86, 85, 114, 115, 58-60, 63-68 and 77-79 of the embedded chip 1U 1; the 7 pin, the 8 pin, the 9 pin and the 18 pin of the chip 1U7 are respectively connected with the 122 pin, the 118 pin, the 124 pin and the 119 pin of the embedded chip 1U 1; the 16 pins and the 17 pins of the chip 1U7 are respectively connected with the 81 pin and the 80 pin of the embedded chip 1U 1; the 19 pins of the chip 1U7 are connected with the 14 pins of the chip 1U 5; the 12 pins, 34 pins, 37 pins and 39 pins of the chip 1U7 are all connected with the output end +3.3V, and the capacitor 1C701 is connected between the 12 pins of the chip 1U7 and the ground.

The IO expansion card circuit comprises an IO expansion bus communication circuit and a beacon relay main module circuit; the IO expansion bus communication circuit consists of an optical coupler 2U5, a NAND gate 2U6, optical couplers 2U1 to 2U4, chips 2U7 to 2U8, resistors 2RP101 to 2RP104 and resistors 2R501 to 2R 506; the model of the optical coupler 2U5 is TLP281-2, the model of the NAND gate 2U6 is 74HC00, the models of the optical couplers 2U1 to 2U4 are TLP281-4, and the models of the chips 2U7 to 2U8 are 74HC245;

the beacon relay main module circuit consists of a chip 12U4, an amplifier 12U3, an optocoupler 12U1, a chip 12U2, a chip 12U5, a constant current source 12U6, a triode 12Q 01-triode 12Q03, a potentiometer 12RJ01, a resistor 12R 11-resistor 12R15, a resistor 12R 31-resistor 12R35, a resistor 12R 22-resistor 12R27 and a capacitor 12C 31-capacitor 12C 33; the model of the chip 12U4 is 74HC74, the model of the amplifier 12U3 is LM358, the model of the optical coupler 12U1 is TLP281-4, the model of the chip 12U2 is LM393, the model of the chip 12U5 is CN5710, and the model of the constant current source 12U6 is E-102T;

The serial port isolation card circuit comprises first to fourth serial port isolation card circuits; the first to fourth serial port isolation card circuits have the same structure; the first serial port isolation card circuit consists of a chip 10U1 to a chip 10U7, a digital triode 10Q3 to a digital triode 10Q5, a diode 10D1, a resistor 10R51 to a resistor 10R59 and a capacitor 10C11 to a capacitor 10C 21; the chip 10U1 is of a model MAX232, the chip 10U2 is of a model MAX485, the chip 10U3 is of a model SN75179B, the chip 10U4 is of an XC6401, the chip 10U5 is of a model TLP281-2, the chip 10U6 is of an ADUM1201ARZ, and the chip 10U7 is of a model DC-DC05; the triodes 10Q3 and 10Q4 are PNP type digital triodes, and the triodes 10Q5 are NPN type digital triodes; the diode 10D1 is a common cathode diode; the second serial port isolation card circuit consists of a chip 2-10U1 to a chip 2-10U7, a digital triode 2-10Q3 to a digital triode 2-10Q5, a diode 2-10D1, a resistor 2-10R51 to a resistor 2-10R59 and a capacitor 2-10C11 to a capacitor 2-10C 21; the third serial port isolation card circuit consists of a chip 3-10U1 to a chip 3-10U7, a digital triode 3-10Q3 to a digital triode 3-10Q5, a diode 3-10D1, a resistor 3-10R51 to a resistor 3-10R59 and a capacitor 3-10C11 to a capacitor 3-10C 21; the fourth serial port isolation card circuit consists of a chip 4-10U1 to a chip 4-10U7, a digital triode 4-10Q3 to a digital triode 4-10Q5, a diode 4-10D1, a resistor 4-10R51 to a resistor 4-10R59, a capacitor 4-10C11 and a capacitor 4-10C 21;

The AI isolation card circuit comprises a first AI isolation circuit and a second AI isolation circuit; the first AI isolation circuit consists of an amplifier 4U1, an amplifier 4U2, resistors 4R11-4R18, resistors 4R 21-4R 28, resistors 4R 31-4R 38, capacitors 4C11-4C12 and resistors 4RP511-4RP 512; the model numbers of the amplifier 4U1 and the amplifier 4U2 are LM324;

the AO isolation card circuit consists of an amplifier 5U1, triodes 5Q1-5Q2, resistors 5R1-5R12 and capacitors 5C1-5C 2; the model of the amplifier 5U1 is LM324;

the co-processing unit interface circuit consists of a parallel-serial conversion input circuit and a serial-parallel conversion output circuit; the parallel-serial conversion input circuit consists of a chip 6U1, a chip 6U5 to a chip 6U7, a chip 6UA to a chip 6UB, a triode 6Q701-6Q702, a triode 6Q602, a resistor 6R701-6R708, a resistor 6R601-6R603, a capacitor 6C701-6C702 and a capacitor 6C601-6C 605; the model of the chip 6U1 is TLP281-2, the models of the chips 6U5 and 6U6 are 74HC165, the model of the chip 6U7 is BL1551, the model of the chip 6UA is 74HC165, and the model of the chip 6UB is 74HC86;

the serial-parallel conversion output circuit consists of chips 7U1 to 7U5, chips 7U8 to 7U9, capacitors 7C701 to 7C705 and capacitors 7C708 to 7C 709; the models of the chips 7U1 to 7U5 and 7U9 are 74HC594, and the model of the chip 7U8 is 74HC139;

The pins 2 and 4 of the optocoupler 2U5 of the IO expansion bus communication circuit are grounded, the pins 6 and 8 of the optocoupler 2U5 are connected with the output end +5V, and the pins 5 and 7 of the optocoupler 2U5 are grounded through a resistor 2R504 and a resistor 2R503 respectively; the 1 foot, the 5 foot, the 10 foot and the 13 foot-14 foot of the NAND gate 2U6 are connected with the output end +5V, the 3 foot and the 12 foot of the NAND gate 2U6 are connected, the 6 foot and the 9 foot of the NAND gate 2U6 are connected, the 2 foot of the NAND gate 2U6 is connected with the 7 foot of the optical coupler 2U5, and the 4 foot of the NAND gate 2U6 is connected with the 5 foot of the optical coupler 2U 5;

the optocouplers 2U1 to 2U2, the chip 2U7 and the resistors 2RP101 to 2RP102 form a signal output circuit; one end of each of the resistors 2RP101 to 2RP102 is connected with pins 93, 10-15 and 132 of the embedded chip 1U1, and the other end of each of the resistors 2RP101 to 2RP102 is sequentially connected with pins 1, 3, 5 and 7 of the optocoupler 2U1, and pins 1, 3, 5 and 7 of the optocoupler 2U 2; the 2 feet, the 4 feet, the 6 feet and the 8 feet of the optical coupler 2U1 are grounded; the 16 feet, 14 feet, 12 feet and 10 feet of the optocoupler 2U1, and the 16 feet, 14 feet, 12 feet and 10 feet of the optocoupler 2U2 are all connected with the output end +3.3V; the 15 pin, the 13 pin, the 11 pin and the 9 pin of the optical coupler 2U1, and the 15 pin, the 13 pin, the 11 pin and the 9 pin of the optical coupler 2U2 are sequentially connected with the 2 pin-9 pin of the chip 2U 7; the 1 pin and the 20 pin of the chip 2U7 are both connected with the output end +3.3V, and the 19 pin of the chip 2U7 is connected with the 6 pin of the NAND gate 2U 6;

The optocouplers 2U3 to 2U4, the chip 2U8 and the resistors 2RP103 to 2RP06 form a signal input circuit; one end of each of the resistors 2RP104 and 2RP103 is sequentially connected with the 11 pin-18 pin of the chip 2U7, and the other end of each of the resistors 2RP104 and 2RP103 is sequentially connected with the 7 pin, the 5 pin, the 3 pin and the 1 pin of the optocoupler 2U4, and the 7 pin, the 5 pin, the 3 pin and the 1 pin of the optocoupler 2U 3; the 2 feet, the 4 feet, the 6 feet and the 8 feet of the optical coupler 2U3, and the 2 feet, the 4 feet, the 6 feet and the 8 feet of the optical coupler 2U4 are all grounded; the 16 feet, 14 feet, 12 feet and 10 feet of the optocoupler 2U3, and the 16 feet, 14 feet, 12 feet and 10 feet of the optocoupler 2U4 are all connected with the output end +3.3V; the 15 pin, the 13 pin, the 11 pin and the 9 pin of the optical coupler 2U3, and the 15 pin, the 13 pin, the 11 pin and the 9 pin of the optical coupler 2U4 are sequentially connected with the 2 pin-9 pin of the chip 2U 8; the 1 pin and the 20 pin of the chip 2U8 are both connected with the output end +3.3V, and the 19 pin of the chip 2U8 is connected with the 4 pin of the chip 7U9 of the serial-parallel conversion output circuit of the co-processing unit interface circuit; the pins 11-18 of the chip 2U8 are sequentially connected with the pins 132, 15, 14, 13, 12, 11, 10 and 93 of the embedded chip 1U1, and the pins 2-9 of the chip 2U8 are grounded through the resistors 2RP105 and 2RP 106;

the 12 pins of the chip 12U4 are connected with the 49 pins of the embedded chip 1U1, the 11 pin of the chip 12U4 is connected with the 50 pins of the embedded chip 1U1, the 5 pins of the chip 12U4 are the feedback signals FHFK of the honeycomb relay main module circuit, the 1 pins, the 4 pins, the 10 pins, the 13 pins and the 14 pins of the chip 12U4 are connected with the output end +3.3V, the 2 pins of the chip 12U4 are grounded through the resistor 12R14, and the 3 pins of the chip 12U4 are connected with the collector electrode of the triode 12Q 03; the collector of the triode 12Q03 is connected with the output end +3.3V through a resistor 12R34, the base of the triode is connected with the 7 pin of the amplifier 12U3 through a resistor 12R33, the emitter of the triode 12Q03 is grounded, and a capacitor 12C32 is connected between the base of the triode 12Q03 and the ground; the 1 pin of the amplifier 12U3 is connected with the 6 pin of the optocoupler 12U1, the resistor 12R31 and the resistor 12R32 are connected in series and then connected between the output end +3.3V and the ground, the 2 pin and the 6 pin of the amplifier 12U3 are both connected with the nodes of the resistor 12R31 and the resistor 12R32, and the 7 pin of the amplifier 12U3 is connected with the 7 pin of the optocoupler 12U 1; the 3 pin of the amplifier 12U3 is connected with the 12 pin of the chip 12U4, and the 5 pin of the amplifier 12U3 is connected with the 11 pin of the chip 12U 4; the 3 pin of the optocoupler 12U1 is connected with the 9 pin of the chip 12U4, the 1 pin of the optocoupler 12U1 is connected with the collector of the triode 12Q02 through the potentiometer 12RJ01, the resistor 12R25 and the resistor 12R24 are connected in series and then connected between the 7 pin of the 12U2 and the ground, the base of the triode 12Q02 is connected with the node of the resistor 12R25, the emitter of the triode 12Q02 is grounded, the 2 pin of the optocoupler 12U1 is grounded through the constant current source 12U6, the 4 pin of the optocoupler 12U1 is connected with the 5 pin of the optocoupler 12U1, the 8 pin of the optocoupler 12U1 is grounded through the resistor 12R15, the 9 pin of the optocoupler 12U1 is grounded through the resistor 12R13, the 11 pin of the optocoupler 12U1 is grounded through the resistor 12R12, the 10 pin and the 16 pin of the optocoupler 12U1 are connected with +5V, and the 15 pin of the optocoupler 12U1 is connected with the 2 pin of the chip 12U 4; the 5 pin of the chip 12U2 is connected with the 11 pin of the optical coupler 12U1, the 7 pin of the chip 12U2 is connected with the output end +5V through a resistor 12R26, the 1 pin of the chip 12U2 is connected with the output end +5V through a resistor 12R23, the 6 pin of the chip 12U2 is connected with the 2 pin, and the 3 pin of the chip 12U2 is connected with the 9 pin of the optical coupler 12U 1; the 1 pin of the chip 12U5 is connected with the 1 pin of the chip 12U2, the 3 pin of the chip 12U5 is grounded through a resistor 12R27, the 5 pin of the chip 12U5 is connected with the collector of the triode 12Q02, and the 5 pin of the chip 12U5 is a clock output port FHCLK of the tower relay main module circuit; the base electrode of the triode 12Q01 is connected with the 12 pin of the optocoupler 12U1, the resistor 12R21 and the resistor 12R22 are connected in series and then connected between the output end +5V and the ground, the 2 pin of the chip 12U2 is connected with the node of the resistor 12R21 and the resistor 12R22, and the collector electrode of the triode 12Q01 is a signal transmitting port FHn of the beacon relay main module circuit;

The 2 pins of the chip 10U7 of the first serial port isolation card circuit are connected with the output end +5V, the 1 pin of the chip 10U7 of the first serial port isolation card circuit is grounded, the 3 pins of the chip 10U7 of the first serial port isolation card circuit are output isolated, the 4 pins of the chip 10U7 of the first serial port isolation card circuit are output isolated power supplies, the 2 pins of the chip 10U4 are connected with the 4 pins of the chip 10U7, the 1 pin of the chip 10U4 is connected with the 4 pins of the chip 10U7 through a resistor 10R59, the collector of the digital triode 10Q5 is connected with the 1 pin of the chip 10U4, the base of the triode 10Q5 is connected with the 3 pins of the chip 10U4, the emitter of the triode 10Q5 is connected with the 3 pins of the chip 10U7, and a capacitor 10C21 is connected between the collector of the triode 10Q5 and the 3 pins of the chip 10U 7; the 6 pins of the chip 10U4 are the first path of output end VCC1, the 4 pins of the chip 10U4 are the second path of output end VCC2, the 5 pins of the chip 10U4 are connected with the 3 pins of the chip 10U7, the 6 pins of the chip 10U4 are connected with the first anode of the diode 10D1, the 4 pins of the chip 10U4 are connected with the second anode of the diode 10D1, the cathode of the diode 10D1 is the output end VCC0, the capacitor 10C19 is connected between the 6 pins of the chip 10U4 and the 3 pins of the chip 10U7, and the capacitor 10C20 is connected between the 4 pins of the chip 10U4 and the 3 pins of the chip 10U 7;

the 2 pin of the chip 10U6 is connected with the 101 pin of the embedded chip 1U1, the 3 pin of the chip 10U6 is connected with the 102 pin of the embedded chip 1U1, the 1 pin of the chip 10U6 is connected with the output end +5V, the resistor 10R57 is connected between the 2 pin and the 7 pin of the chip 10U6, the resistor 10R58 is connected between the 3 pin and the 6 pin of the chip 10U6, the 8 pin of the chip 10U6 is connected with the output end VCC0, the capacitor 10C18 is connected between the 1 pin of the chip 10U6 and the 3 pin of the chip 10U7, and the capacitor 10C17 is connected between the 8 pin of the chip 10U6 and the 3 pin of the chip 10U 7; the emitter of the triode 10Q3 is connected with the output end VCC0, the base of the triode 10Q3 is connected with the 8 pin of the chip 10U5, the collector of the triode 10Q3 is connected with the 3 pin of the chip 10U7 through a resistor 10R53, the emitter of the triode 10Q4 is connected with the output end VCC0, the base of the triode 10Q4 is connected with the 6 pin of the chip 10U5, the collector of the triode 10Q4 is connected with the 3 pin of the chip 10U7 through a resistor 10R54, and the collector of the triode 10Q4 is connected with the 3 pin of the chip 10U 4; the 1 pin of the chip 10U5 is connected with the 1 pin of the 7U9 through a resistor 10R55, the 3 pin of the chip 10U5 is connected with the 15 pin of the 7U1 through a resistor 10R56, the collector of the triode 10Q3 is connected with the 15 pin of the 7U9 through a resistor 10R51, the collector of the triode 10Q4 is connected with the 15 pin of the 7U1 through a resistor 10R52, and the 2 pin, the 4 pin, the 5 pin and the 7 pin of the chip 10U5 are all connected with the 3 pin of the chip 10U 7; the 1 pin of the chip 10U2 is connected with the 7 pin of the chip 10U6, the 2 pin of the chip 10U2 is connected with the 3 pin and then connected with the collector of the triode 10Q3, the 4 pin of the chip 10U2 is connected with the 6 pin of the chip 10U6, the 8 pin of the chip 10U2 is connected with the output end VCC2, and the capacitor 10C16 is connected between the 8 pin of the chip 10U2 and the 3 pin of the chip 10U 7; the 1 pin of the chip 10U3 is connected with the output end VCC2, the 2 pin of the chip 10U3 is connected with the 1 pin of the chip 10U2, the 3 pin of the chip 10U3 is connected with the 4 pin of the chip 10U2, the 7 pin of the chip 10U3 is connected with the 7 pin of the chip 10U2, and the 8 pin of the chip 10U3 is connected with the 6 pin of the chip 10U 2; the 11 pin of the chip 10U1 is connected with the 3 pin of the chip 10U3, the 12 pin of the chip 10U1 is connected with the 2 pin of the chip 10U3, the 13 pin of the chip 10U1 is connected with the 7 pin of the chip 10U3, the 14 pin of the chip 10U1 is connected with the 8 pin of the chip 10U3, the capacitor 10C13 is connected between the 1 pin and the 3 pin of the chip 10U1, the capacitor 10C15 is connected between the 4 pin and the 5 pin of the chip 10U1, the 16 pin of the chip 10U1 is connected with the output end VCC1, the capacitor 10C11 is connected between the 16 pin of the chip 10U1 and the 3 pin of the chip 10U7, the capacitor 10C12 is connected between the 2 pin of the chip 10U1 and the 3 pin of the chip 10U7, and the capacitor 10C14 is connected between the 6 pin of the chip 10U1 and the 3 pin of the chip 10U 7;

The 2 pins of the chip 2-10U6 of the second serial port isolation card circuit are connected with the 37 pins of the embedded chip 1U1, the 3 pins of the chip 2-10U6 are connected with the 36 pins of the embedded chip 1U1, the 3 pins of the chip 2-10U5 are connected with the 2 pins of the 7U1, and the 1 pins of the chip 2-10U5 are connected with the 1 pins of the 7U 9; the 2 pins of the chip 3-10U6 of the third serial port isolation card circuit are connected with the 70 pins of the embedded chip 1U1, the 3 pins of the chip 3-10U6 are connected with the 69 pins of the embedded chip 1U1, the 3 pins of the chip 3-10U5 are connected with the 4 pins of the 7U1, and the 1 pins of the chip 3-10U5 are connected with the 2 pins of the 7U 9; the 2 pins of the chip 4-10U6 of the fourth serial port isolation card circuit are connected with the 112 pin of the embedded chip 1U1, the 3 pins of the chip 4-10U6 are connected with the 111 pin of the embedded chip 1U1, the 3 pins of the chip 4-10U5 are connected with the 6 pin of the 7U1, and the 1 pin of the chip 4-10U5 is connected with the 3 pin of the 7U 9;

the DIDO isolation card circuit comprises a DIDO isolation circuit, a DI isolation circuit, a DO isolation circuit and a DO driving circuit; the DO driving circuit comprises eight driving circuits with the same structure, namely a first DO driving circuit to an eighth DO driving circuit; the first DO driving circuit consists of triodes Q1-Q2, a light emitting diode DS1, a voltage stabilizing tube D2 and resistors R2-R3; the collector of the triode Q1 is connected with an external driving power supply WV through a resistor R3 and a resistor R2 in sequence, the collector of the triode Q1 is an output pin O+ and is connected with a switching signal port, the emitter of the triode Q1 is an output pin O-of a first DO driving circuit, and the base of the triode Q1 is connected with the collector of the triode Q2; the emitter of the triode Q2 is connected with an external driving power supply WV through a resistor R2, and the base electrode of the triode Q2 is an input pin OC+ of the first DO driving circuit; the voltage stabilizing tube D2 is connected between an external driving power supply WV and the output pin O+, and the light emitting diode DS1 is connected between the emitter of the triode Q2 and the input pin OC+;

The second DO driving circuit consists of triodes 2-Q1 to 2-Q2, a light emitting diode 2-DS1, a voltage stabilizing tube 2-D2 and resistors 2-R2 to 2-R3; the collector electrode of the triode 2-Q1 is an output pin O+ and is connected with a switch signal port, the emitter electrode of the triode 2-Q1 is an output pin O-of the second DO driving circuit, and the base electrode of the triode 2-Q2 is an input pin OC+ of the second DO driving circuit; the third DO driving circuit consists of triodes 3-Q1 to 3-Q2, a light emitting diode 3-DS1, a voltage stabilizing tube 3-D2 and resistors 3-R2 to 3-R3; the collector electrode of the triode 3-Q1 is an output pin O+ and is connected with a switch signal port, the emitter electrode of the triode 3-Q1 is an output pin O-of the third DO driving circuit, and the base electrode of the triode 3-Q2 is an input pin OC+ of the third DO driving circuit; the fourth DO driving circuit consists of triodes 4-Q1 to 4-Q2, a light emitting diode 4-DS1, a voltage stabilizing tube 4-D2 and resistors 4-R2 to 4-R3; the collector electrode of the triode 4-Q1 is an output pin O+ and is connected with a switch signal port, the emitter electrode of the triode 4-Q1 is an output pin O-of a fourth DO driving circuit, and the base electrode of the triode 4-Q2 is an input pin OC+ of the fourth DO driving circuit; the fifth DO driving circuit consists of triodes 5-Q1 to 5-Q2, a light emitting diode 5-DS1, a voltage stabilizing tube 5-D2 and resistors 5-R2 to 5-R3; the collector electrode of the triode 5-Q1 is an output pin O+ and is connected with a switch signal port, the emitter electrode of the triode 5-Q1 is an output pin O-of a fifth DO driving circuit, and the base electrode of the triode 5-Q2 is an input pin OC+ of the fifth DO driving circuit; the sixth DO driving circuit consists of triodes 6-Q1 to 6-Q2, a light emitting diode 6-DS1, a voltage stabilizing tube 6-D2 and resistors 6-R2 to 6-R3; the collector electrode of the triode 6-Q1 is an output pin O+ and is connected with a switch signal port, the emitter electrode of the triode 6-Q1 is an output pin O-of a sixth DO driving circuit, and the base electrode of the triode 6-Q2 is an input pin OC+ of the sixth DO driving circuit; the seventh DO driving circuit consists of triodes 7-Q1 to 7-Q2, a light emitting diode 7-DS1, a voltage stabilizing tube 7-D2 and resistors 7-R2 to 7-R3; the collector electrode of the triode 7-Q1 is an output pin O+ and is connected with a switch signal port, the emitter electrode of the triode 7-Q1 is an output pin O-of a seventh DO driving circuit, and the base electrode of the triode 7-Q2 is an input pin OC+ of the seventh DO driving circuit; the eighth DO driving circuit consists of triodes 8-Q1 to 8-Q2, a light emitting diode 8-DS1, a voltage stabilizing tube 8-D2 and resistors 8-R2 to 8-R3; the collector electrode of the triode 8-Q1 is an output pin O+ and is connected with a switch signal port, the emitter electrode of the triode 8-Q1 is an output pin O-of the eighth DO driving circuit, and the base electrode of the triode 8-Q2 is an input pin OC+ of the eighth DO driving circuit;

The DO isolation circuit comprises a first DO isolation circuit and a second DO isolation circuit; the second DO isolation circuit has the same structure as the first DO isolation circuit; the first DO isolation circuit consists of an optical coupler 3U1, an exclusion 3RP1 and light emitting diodes 3DO1-3DO 4; the 2, 4, 6 and 8 pins of the optical coupler 3U1 are connected and then grounded, the 1, 3, 5 and 7 pins of the optical coupler 3U1 are respectively connected with one end of the discharge resistor 3RP1 through the light emitting diodes 3DO1-3DO4, the other end of the discharge resistor 3RP1 is an input end 3MDKI 0-3 MDKI3 of the first DO isolation circuit, the 16, 14, 12 and 10 pins of the optical coupler 3U1 are respectively connected with the input pins OC+ of the first DO drive circuit to the fourth DO drive circuit, and the 15, 13, 11 and 9 pins of the optical coupler 3U1 are respectively connected with the output pins O-of the first DO drive circuit to the fourth DO drive circuit;

the second DO isolation circuit consists of an optical coupler 2-3U1, an exclusion 2-3RP1 and light emitting diodes 2-3DO1 to 2-3DO 4; 1, 3, 5 and 7 pins of the optical coupler 2-3U1 are respectively connected with one end of an arranging block 2-3RP1 through light emitting diodes 2-3DO1 to 2-3DO4, the other end of the arranging block 2-3RP1 is an input end 3MDKI 0-3 MDKI3 of a second DO isolation circuit, 16, 14, 12 and 10 pins of the optical coupler 2-3U1 are respectively connected with input pins OC+ of fifth DO driving circuits to eighth DO driving circuits, and 15, 13, 11 and 9 pins of the optical coupler 2-3U1 are respectively connected with output pins O-of the fifth DO driving circuits to eighth DO driving circuits;

The DI isolation circuit comprises a first DI isolation circuit and a second DI isolation circuit; the second DI isolation circuit has the same structure as the first DI isolation circuit; the first DI isolation circuit consists of an optocoupler 3U5, an exclusion 3RP3-3RP4 and a light emitting diode 3DI1-3DI 4; the 2, 4, 6 and 8 pins of the optical coupler 3U5 are connected with the public end of the switch signal, the 1, 3, 5 and 7 pins of the optical coupler 3U5 are respectively connected with four paths of switch signal ports through the resistor 3RP4 and the light emitting diodes 3D11-3D14, the 10, 12, 14 and 16 pins of the optical coupler 3U5 are connected with the output end +3.3V, the 15, 13, 11 and 9 pins of the optical coupler 3U5 are grounded through the resistor 3RP3, and the 15, 13, 11 and 9 pins of the optical coupler 3U5 are respectively the signal output ends 3MDKO 0-3 MDKO3 of the first DI isolation circuit; the second DI isolation circuit consists of an optocoupler 2-3U5, resistors 2-3RP3 to 2-3RP4 and light emitting diodes 2-3DI1 to 2-3DI 4; the 15 pins, the 13 pins, the 11 pins and the 9 pins of the optical coupler 2-3U5 are respectively the signal output ends 3MDKO 0-3 MDKO3 of the second DI isolation circuit;

the DIDO isolation circuit consists of a chip 3U2-3U3, a digital triode 3Q1, a resistor 3R1 and a capacitor 3C1-3C2, wherein the 20 pins of the chip 3U2-3U3 are all connected with the output end +3.3V, the 10 pins of the chip 3U2-3U3 are all grounded, the 19 pin of the chip 3U2 is connected with the 11 pin of the chip 7U8, the 18 pin, 17 pin, 16 pin, 15 pin, 14 pin, 13 pin, 12 pin and 11 pin of the chip 3U3 are connected with the 2 pin-9 pin of the chip 3U3, the 18 pin, 17 pin, 16 pin, 15 pin, 14 pin, 13 pin, 12 pin and 11 pin of the chip 3U2 are respectively connected with the 56-57 pin and 87-92 pin of the embedded chip 1U1, the 5 pin of the chip 3U2 is connected with the 5 pin of the chip 3U2, the signal output end 3 MDO 0-3 MDO 3 of the first isolation circuit, and the second signal output end 3 MDO 3 of the chip 3U 3-3 is connected with the second end 3D 3; the 1 foot of the chip 3U3 is connected with the 3 foot of the chip 7U5, the 11 foot is connected with the collector of the digital triode 3Q1, the 19 foot, the 18 foot, the 17 foot and the 16 foot of the chip 3U3 are connected with the input end 3MDKI 0-3 MDKI3 of the first DO isolation circuit, the 15 foot, the 14 foot, the 13 foot and the 12 foot of the chip 3U3 are connected with the input end 3MDKI 0-3 MDKI3 of the second DO isolation circuit, the base of the digital triode 3Q1 is connected with the 1 foot of the chip 3U2, the emitter of the digital triode 3Q1 is connected with the 19 foot of the chip 3U2, the resistor 3R1 is connected between the 11 foot of the chip 3U3 and the ground, the capacitor 3C1 is connected between the 20 foot of the chip 3U2 and the ground, and the capacitor 3C2 is connected between the 20 foot of the chip 3U 3;

The model of the amplifier 4U1 and the model of the amplifier 4U2 of the first AI isolating circuit are LM324, the analog signal port to be measured of the same-direction input end 3 pin of the amplifier 4U1, the same-direction input end 3 pin of the amplifier 4U1 is grounded through a resistor 4R31, the reverse input end 2 pin of the amplifier 4U1 is grounded through a resistor 4R12, and the output end 1 pin of the amplifier 4U1 is connected with the reverse input end 2 pin of the amplifier 4U1 through a feedback resistor 4R 11; the unidirectional input end 5 pin of the amplifier 4U1 is connected with an analog signal port to be measured, the unidirectional input end 5 pin of the amplifier 4U1 is grounded through a resistor 4R32, the reverse input end 6 pin of the amplifier 4U1 is grounded through a resistor 4R14, and the output end 7 pin of the amplifier 4U1 is connected with the reverse input end 6 pin of the amplifier U1 through a feedback resistor 4R 13; the same-direction input end 10 pin of the amplifier 4U1 is connected with an analog signal port to be measured, the same-direction input end 10 pin of the amplifier 4U1 is grounded through a resistor 4R33, the reverse input end 9 pin of the amplifier 4U1 is grounded through a resistor 4R16, and the output end 8 pin of the amplifier 4U1 is connected with the reverse input end 9 pin of the amplifier 4U1 through a feedback resistor 4R 15; the pin 12 of the same-direction input end of the amplifier 4U1 is connected with an analog signal port to be measured, the pin 12 of the same-direction input end of the amplifier 4U1 is grounded through a resistor 4R34, the pin 13 of the reverse input end of the amplifier 4U1 is grounded through a resistor 4R18, and the pin 14 of the output end of the amplifier 4U1 is connected with the pin 13 of the reverse input end of the amplifier 4U1 through a resistor 4R 17; the 4 pin of the amplifier 4U1 is connected with the output end +5V, and the capacitor 4C11 is connected between the 4 pin of the amplifier 4U1 and the ground;

The pin 3 of the homodromous input end of the amplifier 4U2 is connected with an analog signal port to be measured, the pin 3 of the homodromous input end of the amplifier 4U2 is grounded through a resistor 4R35, the pin 2 of the reverse input end of the amplifier 4U2 is grounded through a resistor 4R22, and the pin 1 of the output end of the amplifier 4U2 is connected with the pin 2 of the reverse input end of the amplifier 4U2 through a feedback resistor 4R 21; the same-direction input end 5 pin of the amplifier 4U2 is connected with an analog signal port to be measured, the same-direction input end 5 pin of the amplifier 4U2 is grounded through a resistor 4R36, the reverse input end 6 pin of the amplifier 4U2 is grounded through a resistor 4R24, and the output end 7 pin of the amplifier 4U2 is connected with the reverse input end 6 pin of the amplifier 4U2 through a feedback resistor 4R 23; the same-direction input end 10 pin of the amplifier 4U2 is connected with an analog signal port to be measured, the same-direction input end 10 pin of the amplifier 4U2 is grounded through a resistor 4R37, the reverse input end 9 pin of the amplifier 4U2 is grounded through a resistor 4R26, and the output end 8 pin of the amplifier 4U2 is connected with the reverse input end 9 pin of the amplifier 4U2 through a feedback resistor 4R 25; the pin 12 of the same-direction input end of the amplifier 4U2 is connected with an analog signal port to be measured, the pin 12 of the same-direction input end of the amplifier 4U2 is grounded through a resistor 4R38, the pin 13 of the reverse input end of the amplifier 4U2 is grounded through a resistor 4R28, and the pin 14 of the output end of the amplifier 4U2 is connected with the pin 13 of the reverse input end of the amplifier 4U2 through a feedback resistor 4R 27; the 4 pin of the amplifier 4U2 is connected with the output end +5V, and the capacitor 4C12 is connected between the 4 pin of the amplifier 4U2 and the ground;

The output ends 1, 7, 8 and 14 of the amplifier 4U1 are respectively connected with the 34, 35, 42 and 43 pins of the embedded chip 1U1 through the resistor 4RP 511; the output ends 1, 7, 8 and 14 of the amplifier 4U2 are respectively connected with the 46, 47, 26 and 27 pins of the embedded chip 1U1 through the resistor 4RP 512;

the second AI isolation circuit has the same structure as the first AI isolation circuit, and consists of an amplifier 2-4U1, an amplifier 2-4U2, resistors 2-4R11 to 2-4R18, resistors 2-4R21 to 2-4R28, resistors 2-4R31 to 2-4R38, capacitors 2-4C11 to 2-4C12 and resistors 2-4RP511 to 2-4RP 512; the pins 1, 7, 8 and 14 of the output end of the amplifier 2-4U1 are respectively connected with the pins 28, 29, 44 and 45 of the embedded chip 1U1 through the resistors 2-4RP 511; the pins 1, 7, 8 and 14 of the output end of the amplifier 2-4U2 are respectively connected with the pins 18, 19, 20 and 21 of the embedded chip 1U1 through the resistors 2-4RP 512; the 3 feet, the 5 feet, the 10 feet and the 12 feet of the same-direction input end of the amplifier 2-4U1 and 2-4U2 respectively receive analog signal ports to be measured;

the resistor 5R4 and the resistor 5R11 of the AO isolation card circuit are connected in series and then connected between the pin 5 of the input end of the amplifier 5U1 and the ground, the resistor 5R1 and the resistor 5R12 are connected in series and then connected between the pin 10 of the input end of the amplifier 5U1 and the ground, the node of the resistor 5R4 and the resistor 5R11 is connected with the pin 41 of the embedded chip 1U1, and the node of the resistor 5R1 and the resistor 5R12 is connected with the pin 40 of the embedded chip 1U 1; the 1 pin and the 2 pin of the amplifier 5U1 are connected and then connected with the 5 pin of the amplifier 5U1 through a resistor 5R2, the 7 pin of the amplifier 5U1 is connected with the base electrode of the triode 5Q2, the 6 pin of the amplifier 5U1 is connected with the emitter electrode of the triode 5Q2 through a resistor 5R5, the resistor 5R7 is connected between the 6 pin of the amplifier 5U1 and the ground, and the capacitor 5C1 is connected between the 7 pin of the amplifier 5U1 and the ground; the collector of the triode 5Q2 is connected with the output end +12V, and the emitter of the triode is connected with the 3 pin of the amplifier 5U1 through a resistor 5R 10; the 13 pin and the 14 pin of the amplifier 5U1 are connected and then are connected with the 10 pin of the amplifier 5U1 through a resistor 5R3, the 8 pin of the amplifier 5U1 is connected with the base electrode of the triode 5Q1, the 9 pin of the amplifier 5U1 is connected with the emitter electrode of the triode 5Q1 through a resistor 5R6, the resistor 5R8 is connected between the 9 pin of the amplifier 5U1 and the ground, and the capacitor 5C2 is connected between the 8 pin of the amplifier 5U1 and the ground; the collector of the triode 5Q1 is connected with the output end +12V, and the emitter of the triode is connected with the 12 pin of the amplifier 5U1 through a resistor 5R 9;

The 1 pin and the 4 pin of the chip 6U1 of the parallel-serial conversion input circuit are respectively connected with intrusion detection and interruption input signals through a resistor 6R702 and a resistor 6R701, the 6 pin and the 8 pin of the chip 6U1 are respectively connected with the output end +3.3V through a resistor 6R703 and a resistor 6R704, the 5 pin of the chip 6U1 is grounded through a resistor 6R708, the capacitor 6C701 is connected with the resistor 6R708 in parallel, the 7 pin of the chip 6U1 is grounded through a resistor 6R707, the capacitor 6C702 is connected with the resistor 6R702 in parallel, the base of the triode 6Q701 is connected with the 5 pin of the chip 6U1, the emitter of the triode 6Q701 is grounded, the collector of the triode 6Q701 is connected with the output end +3.3V through a resistor 6R706, the base of the triode 6Q702 is connected with the 7 pin of the chip 6U1, the collector of the triode 6Q702 is connected with the output end +3.3V through a resistor 6R705, and the collector of the triode 6Q702 is connected with the embedded triode 1 of the triode 1; the chip 6U5 to the chip 6U6 and the 2 pins of the chip 6UA are connected with the 133 pin of the embedded chip 1U1, the collector of the triode 6Q602 is connected with the output end +3.3V through a resistor 6R601, the base of the triode 6Q602 is connected with the 6 pin of the chip 6U7 through a resistor 6R602, the emitter of the triode 6Q602 is grounded, and a resistor 6R603 is connected between the base of the triode 6Q602 and the ground after being connected with a capacitor 6C601 in parallel; the pins 1 of the chips 6U5 to 6U6 and 6UA are connected with the collector of the triode 6Q602, the pin 3 of the chip 6U6 is connected with the collector of the triode 6Q701, and the pin 14 of the chip 6U6 is connected with the pin 5 of the chip 12U 4; the 4 pins of the chip 6U7 are connected with the 134 pins of the embedded chip 1U1, the 1 pin of the chip 6UB is connected with the 3 pin of the chip 6U6, the 2 pin of the chip 6UB is connected with the 4 pins of the chip 6U6, the 4 pins and the 5 pins of the chip 6UB are respectively connected with the 13 pins and the 12 pins of the chip 6U5, the 11 pin of the chip 6UB is connected with the 54 pin of the embedded chip 1U1, the 3 pin of the chip 6UB is connected with the 13 pin of the chip 6UB, and the 6 pin of the chip 6UB is connected with the 12 pin of the chip 6 UB;

Pins 11 of the chips 7U1 to 7U5 of the serial-parallel conversion output circuit are connected with pins 133 of the embedded chip 1U 1; the 14 pins of the chip 7U1 are connected with the 135 pins of the embedded chip 1U1, and the 15 pins, the 2 pins, the 4 pins and the 6 pins of the chip 7U1 are respectively connected with the 3 pins of the chip 10U6 of the first serial port isolation card circuit, the 3 pins of the chip 2-10U6 of the second serial port isolation card circuit, the 3 pins of the chip 3-10U6 of the third serial port isolation card circuit and the 3 pins of the chip 4-10U6 of the fourth serial port isolation card circuit;

the 14 pins of the chip 7U5 are connected with the 9 pins of the chip 7U2, and the 14 pins of the chip 7U3 are connected with the 9 pins of the chip 7U 5; the 14 pins of the chip 7U4 are connected with the 9 pins of the chip 7U 3;

the 15 pins of the chip 7U8 are connected with the 15 pins of the chip 7U5, the 1 pins-3 pins of the chip 7U8 are respectively connected with the 110 pins, the 55 pins and the 126 pins of the embedded chip 1U1, and the 4 pins of the chip 7U8 are connected with the 12 pins of the chip 7U1 to the chip 7U5 and the 6 pins of the chip 6U 7;

the 6 pin-7 pin of the chip 7U9 is connected with the 14 pin and the 13 pin of the chip 7U8, the 11 pin-12 pin and the 14 pin of the chip 7U9 are connected with the 75 pin, the 76 pin and the 74 pin of the embedded chip 1U1, and the 15 pin and the 1 pin-3 pin of the chip 7U9 are respectively connected with the 1 pin of the chip 10U5 of the first serial port isolation card circuit, the 1 pin of the chip 2-10U5 of the second serial port isolation card circuit, the 1 pin of the chip 3-10U5 of the third serial port isolation card circuit and the 1 pin of the chip 4-10U5 of the fourth serial port isolation card circuit; the 3 pins of the chip 7U5 are connected with the 1 pin of the optical coupler 2U5 through the resistor 2R501, and the 4 pins of the chip 7U9 are connected with the 3 pins of the optical coupler 2U5 through the resistor 2R 502.

The PWM counter isolation board circuit consists of chips 8U4-8U7, optocouplers 8U2-8U3, transistors 8Q201-8Q204, transistors 8Q301-8Q308, an exclusion 8RP101, an exclusion 8RP201, an exclusion 8RP202, light emitting diodes 8D301-8D304, light emitting diodes 8D201-8D204 and resistors 8R301-8R 304; the model of the chip 8U4-8U7 is an analog electronic switch BL1551, the model of the optical coupler 8U3 is TLP521-4, and the model of the optical coupler 8U4 is TLP281-4; the input pins 4 of the chips 8U4-8U7 are respectively connected with the 96 pins, 97 pins, 100 pins and 136 pins of the embedded chip 1U 1; the input pin 6 of the chip 8U4-8U7 is respectively connected with the 2 pin-5 pin of the 7U2 in the serial-parallel conversion output circuit, the output pin 3 of the chip 8U4-8U7 is respectively connected with the 1 pin, the 3 pin, the 5 pin and the 7 pin of the optical coupler 8U3 through the row resistor 8RP101 and the LED 8D301-8D304, and the 2 pin, the 4 pin, the 6 pin and the 8 pin of the optical coupler 8U3 are grounded;

the 9 feet to 16 feet of the optical coupler 8U3 are connected with four paths of pulse output circuits with the same structure; the first path pulse output circuit consists of a transistor 8Q301, a transistor 8Q305 and a resistor 8R 301; the 16 pins of the optocoupler 8U3 are connected with the corresponding ports of the pulse signal ports, the 16 pins of the optocoupler 8U3 are connected with the collector of the transistor 8Q301, the emitter of the transistor 8Q301 is connected with one end of the resistor 8R301, the emitter of the transistor 8Q305 is connected with the 15 pins of the optocoupler 8U3, the collector of the transistor 8Q305 is connected with the base of the transistor 8Q301, and the base of the transistor 8Q305 is connected with the other end of the resistor 8R 301; the second pulse output circuit consists of a transistor 8Q302, a transistor 8Q306 and a resistor 8R 302; the collector of the transistor 8Q302 is connected with the 14 pin of the optocoupler 8U3, the 14 pin of the optocoupler 8U3 is connected with the corresponding port of the pulse signal port, and the emitter of the transistor 8Q306 is connected with the 13 pin of the optocoupler 8U 3; the third pulse output circuit consists of a transistor 8Q303, a transistor 8Q307 and a resistor 8R 303; the collector of the transistor 8Q303 is connected to the 12 pin of the optocoupler 8U3, the 12 pin of the optocoupler 8U3 is connected to the corresponding port of the pulse signal port, and the emitter of the transistor 8Q307 is connected to the 11 pin of the optocoupler 8U 3; the fourth pulse output circuit consists of a transistor 8Q304, a transistor 8Q308 and a resistor 8R 304; the collector of the transistor 8Q304 is connected with the 10 pin of the optocoupler 8U3, the 10 pin of the optocoupler 8U3 is connected with the corresponding port of the pulse signal port, and the emitter of the transistor 8Q308 is connected with the 9 pin of the optocoupler 8U 3;

The pulse input circuit of the PWM counter isolation board circuit consists of an optocoupler 8U2, digital transistors 8Q201-8Q204, a resistor-discharging 8RP201, a resistor-discharging 8RP202 and light-emitting diodes 8D201-8D 204; the anodes of the LEDs 8D201-8D204 are respectively connected with the emitters of the transistors 8Q301-8Q304, the cathodes of the LEDs 8D201-8D204 are respectively connected with the 1 pin, the 3 pin, the 5 pin and the 7 pin of the optocoupler 8U2, the 2 pin, the 4 pin, the 6 pin and the 8 pin of the optocoupler 8U2 are respectively connected with the 16 pin, the 14 pin, the 12 pin and the 10 pin of the optocoupler 8U3 through the row-resistance 8RP201, the 16 pin, the 14 pin, the 12 pin and the 10 pin of the optocoupler 8U2 are respectively connected with the bases of the transistors 8Q201-8Q204, and the 15 pin, the 13 pin, the 11 pin and the 9 pin of the optocoupler 8U2 are grounded; the collectors of the transistors 8Q201-8Q204 are respectively grounded through the resistor-discharging 8RP202, the collectors of the transistors 8Q201-8Q204 are respectively connected with the 1 pin of the chip 8U4, the 1 pin of the chip 8U5, the 1 pin of the chip 8U6 and the 1 pin of the chip 8U7, and the emitters of the transistors 8Q201-8Q204 are connected with the output end +3.3V;

the man-machine interaction circuit comprises a first man-machine interaction circuit and a second man-machine interaction circuit;

the first man-machine interaction circuit consists of resistors 9R1-9R8 and light emitting diodes 9D1-9D 8; the resistor 9R1 is connected in series with the light emitting diode 9D1 and then is connected between the 3 pins of the chip 7U4 in the serial-parallel conversion output circuit and the ground; the resistor 9R2 is connected in series with the light emitting diode 9D2 and then connected between the 2 pin of the chip 7U4 in the serial-parallel conversion output circuit and the ground; the resistor 9R3 is connected in series with the light-emitting diode 9D3 and then connected between the pin 1 of the chip 7U4 in the serial-parallel conversion output circuit and the ground; the resistor 9R4 is connected in series with the light-emitting diode 9D4 and then connected between the 15 pins of the chip 7U4 in the serial-parallel conversion output circuit and the ground; the resistor 9R5 is connected in series with the light-emitting diode 9D5 and then connected between the pin 5 of the chip 7U4 in the serial-parallel conversion output circuit and the ground; the resistor 9R6 is connected in series with the light-emitting diode 9D6 and then connected between the pin 4 of the chip 7U4 in the serial-parallel conversion output circuit and the ground; the resistor 9R7 is connected in series with the light emitting diode 9D7 and then connected between the pin 7 of the chip 7U4 in the serial-parallel conversion output circuit and the ground; the resistor 9R8 is connected in series with the light-emitting diode 9D8 and then connected between the pin 6 of the chip 7U4 in the serial-parallel conversion output circuit and the ground;

The second man-machine interaction circuit consists of resistors 9R11-9R18, switches 9S1-9S8 and capacitors 9C1-9C 8; the resistor 9R11 is connected in series with the switch 9S1 and then connected between the output end +3.3V and the ground, and the node between the resistor 9R11 and the switch 9S1 is connected with the 11 pin of the chip 6UA in the parallel-serial conversion input circuit; the resistor 9R12 is connected in series with the switch 9S2 and then connected between the output end +3.3V and the ground, and the node between the resistor 9R12 and the switch 9S2 is connected with the 12 pin of the chip 6UA in the parallel-serial conversion input circuit; the resistor 9R13 is connected in series with the switch 9S3 and then connected between the output end +3.3V and the ground, and the node between the resistor 9R13 and the switch 9S3 is connected with the 13 pin of the chip 6UA in the parallel-serial conversion input circuit; the resistor 9R14 is connected in series with the switch 9S4 and then connected between the output end +3.3V and the ground, and the node between the resistor 9R14 and the switch 9S4 is connected with the 14 pin of the chip 6UA in the parallel-serial conversion input circuit; the resistor 9R15 is connected in series with the switch 9S5 and then connected between the output end +3.3V and the ground, and the node of the resistor 9R15 and the switch 9S5 is connected with the 3 pin of the chip 6UA in the parallel-serial conversion input circuit; the resistor 9R16 is connected in series with the switch 9S6 and then connected between the output end +3.3V and the ground, and the node between the resistor 9R16 and the switch 9S6 is connected with the 4 pin of the chip 6UA in the parallel-serial conversion input circuit; the resistor 9R17 is connected in series with the switch 9S7 and then connected between the output end +3.3V and the ground, and the node between the resistor 9R17 and the switch 9S7 is connected with the 5 pin of the chip 6UA in the parallel-serial conversion input circuit; the resistor 9R18 is connected in series with the switch 9S8 and then connected between the output end +3.3V and the ground, and the node between the resistor 9R18 and the switch 9S8 is connected with the 6 pin of the chip 6UA in the parallel-serial conversion input circuit; the capacitors 9C1-9C8 are respectively connected with the switches 9S1-9S8 in parallel;

The integrated communication card circuit comprises a serial port circuit and a CAN bus circuit; the serial circuit consists of a serial chip 11U11, resistors 11R1-11R2 and capacitors 11C1-11C 5; the serial port chip 11U11 is MAX232 in type, the serial port chip 11U11 pins 11 and 12 are respectively connected with the embedded chip 1U1 pins 113 and 116, the serial port chip 11U11 pins 11 and 12 are respectively connected with serial port signals corresponding to the outside, the resistor 11R1 is connected between the serial port chip 11U11 pins 10 and 12, the resistor 11R2 is connected between the serial port chip 11U11 pins 9 and 11, the capacitor 11C3 is connected between the serial port chip 11U11 pins 4 and 5, the capacitor 11C5 is connected between the serial port chip 11U11 pins 1 and 3, the capacitor 11C1 is connected between the serial port chip 11U11 pin 16 and the ground, the serial port chip 11U11 pin 16 is connected with the output end +5V, the capacitor 11C2 is connected between the serial port chip 11U11 pin 2 and the ground, and the capacitor 11C4 is connected between the serial port chip 11U11 pin 6 and the ground;

the CAN bus circuit consists of an isolation chip 11U21 and a capacitor 11C6-11C 7; the model of the isolation chip 11U21 is ISO1050; the 1 foot of the isolation chip 11U21 is connected with the output end +5V, the 2 foot of the isolation chip 11U21 is connected with the 140 foot of the embedded chip 1U1, the 3 foot of the isolation chip 11U21 is connected with the 139 foot of the embedded chip 1U1, the 4 foot and the 5 foot of the isolation chip 11U21 are both grounded, the 6 foot and the 7 foot of the isolation chip 11U21 are CAN control bus output ends, the 8 foot of the isolation chip 11U21 is connected with the output end +5V, the capacitor 11C6 is connected between the 1 foot of the isolation chip 11U21 and the ground, and the capacitor 11C7 is connected between the 8 foot of the isolation chip 11U21 and the ground.

The invention also relates to an assembled data interaction intelligent terminal system based on the data interaction intelligent host terminal of claim 1, which comprises the data interaction intelligent host terminal, a data bus and a 1 st slave terminal to an N-th slave terminal, wherein N is an integer larger than 1; the structures of the 1 st slave terminal to the N th slave terminal are the same, and the expansion forms from the 1 st slave terminal to the N th slave terminal are cascade connection; the data interaction intelligent host terminal is connected with the Nth slave terminal through the 1 st slave terminal, the 2 nd slave terminal, … and the N-1 th slave terminal in sequence; and the data interaction intelligent host terminal, the 1 st slave terminal and the N th slave terminal are respectively connected to the data bus.

The data buses comprise first to eighth data buses DWKZ0 to DWKZ7, a ninth data bus WKWRZ, a tenth data bus WKOEZ, a data bus power line and a data bus ground line; the data bus power line is connected with a +5V power supply, and the data bus ground line is grounded;

the 1 st slave terminal comprises a slave core control unit, a slave isolation card, a slave power management unit, a 1 st bus controller and a 1 st flame relay slave module circuit;

the slave core control unit has the same structure as the core control unit of the data interaction intelligent host terminal; the slave power management unit has the same structure as the power management unit of the data interaction intelligent host terminal;

The slave isolating card, the 1 st bus controller and the 1 st flame relay slave module circuit are respectively connected with corresponding ports of the slave core control unit;

the external power supply supplies power to the slave core control unit, the slave isolating card, the 1 st bus controller and the 1 st tower relay slave module circuit through the slave power supply management unit;

the 1 st bus controller consists of a chip 13U7 and a resistor 13R 1; the model of the chip 13U7 is 74HC245, and the 1 pin of the chip 13U7 is connected to a ninth data bus WKWRZ of the data bus; the pins 2-9 of the chip 13U7 are respectively connected with the pins 93, 10-15 and 132 of the embedded chip 1U 1; the 10 pin of the chip 13U7 is grounded; pins 18 to 11 of the chip 13U7 are respectively connected to first data buses DWKZ0 to eighth data lines DWKZ7 of the data buses; the 20 pins of the chip 13U7 are connected with a +5V power supply; the resistor 13R1 is connected between the 19 pins and the 20 pins of the chip 13U 7;

the 1 st honeycomb relay slave module circuit consists of an optocoupler 13U1, a chip 13U2, a chip 13U3, a chip 13U4, constant current sources 13D1-13D2, a triode 13Q01, a potentiometer 13RJ01, resistors 13R11-13R13, resistors 13R21-13R25 and capacitors 13C11-13C 14; the model of the optocoupler 13U1 is TLP281-4, the model of the chip 13U2 is LM393, the model of the chip 13U3 is CN5710, the model of the chip 13U4 is 74HB74, the model of the constant current source 13D1-13D2 is S-102T, and the model of the triode 13Q1 is 8550; the 5 pins of the optocoupler 13U1 are the signal input end FHn-1 of the 1 st fire relay slave module circuit through the constant current source 13D2, the 7 pins of the optocoupler 13U1 are connected with the input end of the constant current source 13D1 through the potentiometer 13RJ01, the output end of the constant current source 13D1 is the clock input end CLK of the 1 st fire relay slave module circuit, and the clock input end CLK of the 1 st fire relay slave module circuit is connected with the clock output port FHCLK of the fire relay master module circuit; the 1 pin of the optocoupler 13U1 is connected with the 5 pin of the chip 13U4 through a resistor 13R13, the 2 pin and the 3 pin of the optocoupler 13U1 are connected, the 4 pin, the 6 pin and the 8 pin of the optocoupler 13U1 are grounded, the 9 pin of the optocoupler 13U1 is grounded through a resistor 13R11, the 11 pin of the optocoupler 13U1 is grounded through a resistor 13R12, the 10 pin and the 12 pin of the optocoupler 13U1 are connected with +5V power sources, a capacitor 13C12 is connected between the 9 pin and the 12 pin of the optocoupler 13U1, a capacitor 13C11 is connected between the 11 pin and the 12 pin of the optocoupler 13U1, and the 15 pin and the 16 pin of the optocoupler 13U1 are respectively connected with the 13 pin and the 14 pin of the optocoupler 12U1 in the honeycomb fire relay main module circuit; the 15 pins of the optical coupler 13U1 are connected with the 10 pins of the chip 13U7, and the 16 pins of the optical coupler 13U1 are connected with the 19 pins of the chip 13U 7; the pin 2 and the pin 3 of the chip 13U4 are respectively connected with the pin 11 and the pin 9 of the optocoupler 13U1, and the pin 1, the pin 4 and the pin 14 of the chip 13U4 are respectively connected with a +5V power supply; the node of the resistor 13R22 and the resistor 13R21 is connected with the 7 pin of the chip 13U2, the 7 pin of the chip 13U2 is connected with the 1 pin of the chip 13U3, the 5 pin of the chip 13U2 is grounded through the resistor 13R24, the 5 pin of the chip 13U2 is connected with the 13 pin of the optocoupler 13U1, and the 2 pin, the 3 pin and the 4 pin of the chip 13U2 are all grounded; the 3 pin of the chip 13U3 is grounded through a resistor 13R25, the 5 pin of the chip 13U3 is a clock output end CLK of the beacon relay slave module circuit, and the clock output end CLK of the beacon relay slave module circuit is connected with the input end of the constant current source 13D 1; the base electrode of the triode 13Q01 is connected with the 14 pin of the optocoupler 13U1, the emitter electrode of the triode 13Q01 is connected with a +5V power supply, the collector electrode of the triode 13Q01 is a signal output end CFHn of a flame relay slave module circuit, and the signal output end CFHn of the 1 st flame relay slave module circuit is connected with the signal input end of the flame relay slave module circuit of the 2 nd slave terminal;

Pins 18 to 11 of a chip 2U7 of the IO expansion bus communication circuit in the data interaction intelligent host terminal are respectively connected to first data buses DWKZ0 to eighth data buses DWKZ7 of the data buses; and the 8 pin and the 11 pin of the 2U6 of the IO expansion bus communication circuit in the data interaction intelligent host terminal are respectively connected to a ninth data bus WKWRZ and a tenth data bus WKOEZ of the data buses.

The auxiliary machine isolating card comprises an auxiliary machine AI isolating card circuit and an auxiliary machine AO isolating card circuit, wherein the auxiliary machine AI isolating card circuit and the AI isolating card circuit have the same structure, and the auxiliary machine AO isolating card circuit and the AO isolating card circuit have the same structure; the output end of the slave machine AI isolation card circuit is singly connected with the corresponding input end of the slave machine core control unit, the output end of the slave machine core control unit is connected with the corresponding input end of the slave machine AO isolation card circuit, and the output end of the slave machine AO isolation card circuit is connected with the analog control signal port; the corresponding output ends of the slave power management unit are respectively connected with the power input ends of the slave AI isolation card circuit and the slave AO isolation card circuit.

The secondary machine isolation card comprises a secondary machine DIDO isolation card circuit, and the secondary machine DIDO isolation card circuit and the DIDO isolation card circuit have the same structure; the slave DIDO isolation card circuit is connected with the slave core control unit in a bidirectional manner; the slave DIDO isolation card circuit is connected with the switch signal port in a bidirectional manner; and the corresponding output end of the slave power management unit is connected with the power input end of the slave DIDO isolation card circuit.

The invention also relates to a method for communicating by utilizing the spliced data interaction intelligent terminal system, which utilizes the communication between the main module of the beacon relay and the slave module of the beacon relay, and comprises the following specific steps:

The working principle of this embodiment is as follows: circuit principles related to control unit: the circuit adopts a multiplexing mode of an address bus and a data bus, the output ends of the 1U2 and the 1U3 are connected with the low 16-bit address input ends (A0-A15) of the 1U4, the 1U1 firstly outputs a read-write address, the 1U2 and the 1U3 are controlled by an ADV (137 pins) to latch the low 16-bit address (IO 0-1O 15), and then data to be read and written for the 1U4 can be transmitted on the IO 0-1O 15. Control gating is performed by 1U1, and 1U4, 1U5 and 1U7 cannot be used simultaneously. Because UART4, UART5 and SD card operation pin of 1U1 are shared, in order to facilitate the secondary development, this circuit introduces the analog switch to strobe, can choose what kind of mode to use according to the need while developing secondarily; the keys are functions similar to the keyboard and can be named as keys 1, keys 2 and so on, and specific functions are determined by secondary development, just as the Windows system is only responsible for transmitting keyboard code values to application programs in the system, and nothing is related to the Windows system as to what the application programs are used for.

The technical problem to be solved by the invention is the problem of resource waste, which is mentioned above, and various requirements of an industrial field are met by using a flexibly assembled intelligent terminal. The invention takes the interface for realizing the transmission and collection of various signals as a basic unit, separates the core processing unit and the hardware processing unit of various signals into independent components, and then selectively assembles the components according to different requirements. The invention comprises a data interaction host terminal and a data interaction extension slave terminal. The main board of the data interaction host terminal is integrated with an AI interface, an AO interface, a DIDO interface, a power interface and a co-processing unit; the man-machine interaction unit, the core processing unit, the AI isolation card, the AO isolation card, the DIDO isolation card, the power isolation card, the serial port expansion card, the comprehensive communication interface card, the special GPIO expansion card, the AIAO expansion card and the DIDO expansion card are connected with the main board in a pluggable mode, and secondary development can be carried out according to requirements except the AIAO expansion card and the DIDO expansion card. The motherboard is a motherboard of each interface board, and like a computer motherboard, integrates multiple interfaces for carrying various modules. And an AI interface, an AO interface, a DIDO interface, a power interface and a co-processing unit are integrated on the interface. The co-processing unit is mainly used for detecting and transmitting internal signals, and the man-machine interaction unit is used for interacting with a user, upgrading programs and the like. The core processing unit is a programmable MCU minimum system board which is connected with the main board in a pluggable mode. The system is provided with a completely open-source NET Micro Framework embedded system, and a driving program used by the system is optimized, can process real-time tasks and is very convenient for users to use a C#, net/VB.NET programming language for application development. The AI isolation card, the AO isolation card and the DIDO isolation card are used for isolating external signals, and can be developed by users who develop secondarily according to own will. The power isolation card, i.e., the power management unit, is used to provide the required isolated DC power to the host. The serial port expansion card is used for providing a multifunctional serial port, and can be developed by a secondary development user according to own wish. The comprehensive communication interface card is used for providing an RS232 interface, a CAN interface, an Ethernet interface and a wireless communication interface to the outside, and CAN be developed by a secondary development user according to own wish. The special GPIO expansion card is used to provide PWM signals or count the input digital signals. The AIAO expansion card and the DIDO expansion card are used for connecting with corresponding data interaction expansion slave terminals.

Each data interaction extension slave terminal internally comprises a beacon relay slave module, the beacon relay slave module can control the bus controller so as to further control the on-off of the data interaction slave terminal and the data bus, and each beacon relay module is communicated through a special line so as to transmit a gating signal, so that each data interaction slave terminal can be ensured to access the data bus according to the wish of the data interaction host terminal, and further realize data interaction with the data interaction slave terminal. The beacon relay modules share a clock line, the module selection signal lines are cascaded in a first-stage and a first-stage mode, like relay events, gating signals are like relay batons, the beacon relay main module is only responsible for transmitting the relay batons to the 1 st beacon relay slave module, after data of the 1 st slave terminal are processed, a transmission signal instruction is sent, and the 1 st beacon relay slave module transmits the relay batons to the next beacon relay slave module, and the like. After the relay baton is transferred to the last module or the relay baton is not successfully transferred to the next module, the clock bus can generate a termination signal, the master module can detect the termination signal, and whether the polling system works normally is determined according to the number of the transmitted signal instructions and the number of the slave modules set in the modules. The data interaction extension slave terminals are divided into AIAO data interaction extension slave terminals and DIDO data interaction extension slave terminals.

The AIAO data interactive expansion slave terminal consists of a slave main board, an AI isolation card, an AO isolation card, a bus controller and a beacon relay slave module. The slave main board integrates an AI interface, an AO interface, a bus input/output interface, a honeycomb interface slave module input interface and an output interface; the AI isolation card and the AO isolation card interact with the same-name substances in the host terminal; the bus controller is used for cutting off or switching on the channels of the data interaction expansion slave terminal and the data bus, and the simplest implementation of the bus controller is to control the power supply of the data bus interface chip of the data interaction expansion slave terminal (only the condition that the pin of the chip, which is in butt joint with the data bus when the chip is powered off, presents a high resistance state); the DIDO data interactive expansion slave terminal consists of a slave main board, a DI isolation card, a DO feedback card, a bus controller and a tower relay slave module. The slave main board integrates a DI interface, a DO interface, a bus input/output interface, a beacon relay slave module group input interface and an output interface; the DI isolation card, the DO isolation card and the DIDO isolation card in the data interaction host terminal; the DO feedback card is used to detect whether the DO output is normal. Typical applications are: DO controls an electromagnetic valve, under the condition that the electromagnetic valve is electrified, a corresponding feedback signal is generated in a feedback channel corresponding to the channel, and a logic program can judge whether the electromagnetic valve is normally opened or not according to the signal; the honeycomb relay slave module group is a combination of a plurality of honeycomb relay modules and is used for outputting multi-path gating signals.

Claims

1. The intelligent host terminal for data interaction is characterized by comprising a core control unit, a DIDO isolation card circuit, an AI isolation card circuit, an AO isolation card circuit, a co-processing unit interface circuit, a serial port isolation card circuit, a comprehensive communication card circuit, a man-machine interaction circuit, a PWM counter isolation board circuit, an IO expansion card circuit and a power management unit; the core control unit is in bidirectional connection with a corresponding port of the serial port isolation card circuit, and the serial port isolation card circuit is in bidirectional connection with a serial port signal port to be tested; the core control unit is in bidirectional connection with a corresponding port of the integrated communication card circuit, and the integrated communication card circuit is in bidirectional connection with a serial digital signal port; the core control unit is in bidirectional connection with a corresponding port of the IO expansion card circuit, and the IO expansion card circuit is in bidirectional connection with a port of the multifunctional data interaction intelligent slave terminal; the core control unit is in bidirectional connection with a corresponding port of the co-processing unit interface circuit, a first input end of the co-processing unit interface circuit is connected with an intrusion detection and interrupt input signal port, a first output end of the co-processing unit interface circuit is connected with a corresponding input end of the man-machine interaction circuit, and a second output end of the co-processing unit interface circuit is connected with a corresponding input end of the PWM counter isolation board circuit; the man-machine interaction circuit is connected with the corresponding port of the core control unit in a bidirectional manner; the core control unit is in bidirectional connection with the corresponding port of the PWM counter isolation board circuit, and the pulse signal port to be tested is in bidirectional connection with the corresponding port of the PWM counter isolation board circuit; the output end of the core control unit is connected with the input end of a corresponding port of the AO isolation card circuit, and the output end of the AO isolation card circuit is connected with an analog control signal port; the input end of the AI isolation card circuit is connected with an analog signal port to be measured, and the output end of the AI isolation card circuit is connected with the corresponding input end of the core control unit; the DIDO isolation card circuit is in bidirectional connection with a corresponding port of the core control unit, and the DIDO isolation card circuit is in bidirectional connection with a corresponding port of the switch signal port; the output end of the power management unit is respectively connected with corresponding power ports of the core control unit, the DIDO isolation card circuit, the AI isolation card circuit, the AO isolation card circuit, the co-processing unit interface circuit, the serial port isolation card circuit, the comprehensive communication card circuit, the man-machine interaction circuit, the PWM counter isolation board circuit and the IO expansion card circuit, and the input end of the power management unit is connected with an external power supply;

The circuit board also comprises a main board and first to tenth circuit boards; the co-processing unit interface circuit is arranged on the main board; the core control unit is arranged on the first circuit board; the DIDO isolation card circuit is arranged on the second circuit board; the AI isolation card circuit is arranged on the third circuit board; the AO isolation card circuit is arranged on the fourth circuit board; the serial port isolation card circuit is arranged on the fifth circuit board; the integrated communication card circuit is arranged on the sixth circuit board; the man-machine interaction circuit is arranged on the seventh circuit board; the PWM counter isolation board circuit is arranged on the eighth circuit board; the IO expansion card circuit is arranged on the ninth circuit board; the power management unit is arranged on the tenth circuit board; the first to tenth circuit boards are connected with the main board in a plugging manner;

The core control unit further comprises a chip 1U4, a chip 1U5 and a chip 1U7;

The chip 1U7 is an external memory MT29F1G08, and pins 29-32, 41-44, 26-28, 33, 40 and 45-47 of the chip 1U7 are respectively connected with pins 86, 85, 114, 115, 58-60, 63-68 and 77-79 of the embedded chip 1U 1; the 7 pin, the 8 pin, the 9 pin and the 18 pin of the chip 1U7 are respectively connected with the 122 pin, the 118 pin, the 124 pin and the 119 pin of the embedded chip 1U 1; the 16 pins and the 17 pins of the chip 1U7 are respectively connected with the 81 pin and the 80 pin of the embedded chip 1U 1; the 19 pins of the chip 1U7 are connected with the 14 pins of the chip 1U 5; the 12 pins, 34 pins, 37 pins and 39 pins of the chip 1U7 are all connected with the output end +3.3V, and the capacitor 1C701 is connected between the 12 pins of the chip 1U7 and the ground;

the DIDO isolation card circuit comprises a DIDO isolation circuit, a DI isolation circuit, a DO isolation circuit and a DO driving circuit;

the DO driving circuit comprises eight driving circuits with the same structure, namely a first DO driving circuit to an eighth DO driving circuit; the first DO driving circuit consists of triodes Q1-Q2, a light emitting diode DS1, a voltage stabilizing tube D2 and resistors R2-R3; the collector of the triode Q1 is connected with an external driving power supply WV through a resistor R3 and a resistor R2 in sequence, the collector of the triode Q1 is an output pin O+ and is connected with a switching signal port, the emitter of the triode Q1 is an output pin O-of a first DO driving circuit, and the base of the triode Q1 is connected with the collector of the triode Q2; the emitter of the triode Q2 is connected with an external driving power supply WV through a resistor R2, and the base electrode of the triode Q2 is an input pin OC+ of the first DO driving circuit; the voltage stabilizing tube D2 is connected between an external driving power supply WV and the output pin O+, and the light emitting diode DS1 is connected between the emitter of the triode Q2 and the input pin OC+;

The DO isolation circuit comprises a first DO isolation circuit and a second DO isolation circuit; the second DO isolation circuit has the same structure as the first DO isolation circuit; the first DO isolation circuit consists of an optical coupler 3U1, an exclusion 3RP1 and light emitting diodes 3DO1-3DO 4; the 2, 4, 6 and 8 pins of the optical coupler 3U1 are connected and then grounded, the 1, 3, 5 and 7 pins of the optical coupler 3U1 are respectively connected with one end of the resistor 3RP1 through the light emitting diodes 3DO1-3DO4, the other end of the resistor 3RP1 is an input end 3 MDKI0-3 MDKI3 of the first DO isolation circuit, the 16, 14, 12 and 10 pins of the optical coupler 3U1 are respectively connected with the input pins OC+ of the first DO drive circuit to the fourth DO drive circuit, and the 15, 13, 11 and 9 pins of the optical coupler 3U1 are respectively connected with the output pins O-of the first DO drive circuit to the fourth DO drive circuit;

the second DO isolation circuit consists of an optical coupler 2-3U1, an exclusion 2-3RP1 and light emitting diodes 2-3DO1 to 2-3DO 4; 1, 3, 5 and 7 pins of the optical coupler 2-3U1 are respectively connected with one end of an arranging block 2-3RP1 through light emitting diodes 2-3DO1 to 2-3DO4, the other end of the arranging block 2-3RP1 is an input end 3 MDKI0-3 MDKI3 of a second DO isolation circuit, 16, 14, 12 and 10 pins of the optical coupler 2-3U1 are respectively connected with input pins OC+ of a fifth DO driving circuit to an eighth DO driving circuit, and 15, 13, 11 and 9 pins of the optical coupler 2-3U1 are respectively connected with output pins O-of the fifth DO driving circuit to the eighth DO driving circuit;

The DI isolation circuit comprises a first DI isolation circuit and a second DI isolation circuit; the second DI isolation circuit has the same structure as the first DI isolation circuit; the first DI isolation circuit consists of an optocoupler 3U5, an exclusion 3RP3-3RP4 and a light emitting diode 3DI1-3DI 4; the 2, 4, 6 and 8 pins of the optical coupler 3U5 are connected with the public end of the switch signal, the 1, 3, 5 and 7 pins of the optical coupler 3U5 are respectively connected with four paths of switch signal ports through the resistor 3RP4 and the light emitting diodes 3D11-3D14, the 10, 12, 14 and 16 pins of the optical coupler 3U5 are connected with the output end +3.3V, the 15, 13, 11 and 9 pins of the optical coupler 3U5 are grounded through the resistor 3RP3, and the 15, 13, 11 and 9 pins of the optical coupler 3U5 are respectively the signal output ends 3 MDKO0-3 MDKO3 of the first DI isolation circuit; the second DI isolation circuit consists of an optocoupler 2-3U5, resistors 2-3RP3 to 2-3RP4 and light emitting diodes 2-3DI1 to 2-3DI 4; the 15 pins, the 13 pins, the 11 pins and the 9 pins of the optocoupler 2-3U5 are respectively the signal output ends 3MDKO 0-3 MDKO3 of the second DI isolation circuit;

the DIDO isolation circuit consists of a chip 3U2-3U3, a digital triode 3Q1, a resistor 3R1 and a capacitor 3C1-3C2, wherein the 20 pins of the chip 3U2-3U3 are connected with the output end +3.3V, the 10 pins of the chip 3U2-3U3 are grounded, the 19 pin of the chip 3U2 is connected with the 11 pin of the chip 7U8, the 18 pin, 17 pin, 16 pin, 15 pin, 14 pin, 13 pin, 12 pin and 11 pin of the chip 3U3 are connected with the 2 pin-9 pin of the chip 3U3, the 18 pin, 17 pin, 16 pin, 15 pin, 14 pin, 13 pin, 12 pin and 11 pin of the chip 3U2 are respectively connected with the 56-57 pin, 87-92 pin and 5 pin of the embedded chip 1U1, the 5 pin of the chip 3U2 is connected with the signal output end 3 KODI 0-3 KODI 3 of the first isolation circuit, and the 6 pin 3 MDI 3U2 is connected with the second end 3 KODI 3; the 1 pin of the chip 3U3 is connected with the 3 pin of the chip 7U5, the 11 pin is connected with the collector of the digital triode 3Q1, the 19 pin, the 18 pin, the 17 pin and the 16 pin of the chip 3U3 are connected with the input end 3 MDKI0-3 MDKI3 of the first DO isolation circuit, the 15 pin, the 14 pin, the 13 pin and the 12 pin of the chip 3U3 are connected with the input end 3 MDKI0-3 MDKI3 of the second DO isolation circuit, the base of the digital triode 3Q1 is connected with the 1 pin of the chip 3U2, the emitter of the digital triode 3Q1 is connected with the 19 pin of the chip 3U2, the resistor 3R1 is connected between the 11 pin of the chip 3U3 and the ground, the capacitor 3C1 is connected between the 20 pin of the chip 3U2 and the ground, and the capacitor 3C2 is connected between the 20 pin of the chip 3U 3;

the 6 pin-7 pin of the chip 7U9 is connected with the 14 pin and the 13 pin of the chip 7U8, the 11 pin-12 pin and the 14 pin of the chip 7U9 are connected with the 75 pin, the 76 pin and the 74 pin of the embedded chip 1U1, and the 15 pin and the 1 pin-3 pin of the chip 7U9 are respectively connected with the 1 pin of the chip 10U5 of the first serial port isolation card circuit, the 1 pin of the chip 2-10U5 of the second serial port isolation card circuit, the 1 pin of the chip 3-10U5 of the third serial port isolation card circuit and the 1 pin of the chip 4-10U5 of the fourth serial port isolation card circuit; the 3 pin of the chip 7U5 is connected with the 1 pin of the optical coupler 2U5 through a resistor 2R501, and the 4 pin of the chip 7U9 is connected with the 3 pin of the optical coupler 2U5 through a resistor 2R 502;

The 1U4, 1U5 and 1U7 of the circuit cannot be used at the same time, the 1U1 is required to carry out control gating, and the multiplexing mode of an address bus and a data bus is adopted for data interaction.

2. The data interaction intelligent host terminal according to claim 1, wherein the PWM counter isolation board circuit is composed of chips 8U4-8U7, optocouplers 8U2-8U3, transistors 8Q201-8Q204, transistors 8Q301-8Q308, resistor 8RP101, resistor 8RP201, resistor 8RP202, light emitting diodes 8D301-8D304, light emitting diodes 8D201-8D204 and resistors 8R301-8R 304; the model of the chip 8U4-8U7 is an analog electronic switch BL1551, the model of the optical coupler 8U3 is TLP521-4, and the model of the optical coupler 8U4 is TLP281-4; the input pins 4 of the chips 8U4-8U7 are respectively connected with the 96 pins, 97 pins, 100 pins and 136 pins of the embedded chip 1U 1; the input pin 6 of the chip 8U4-8U7 is respectively connected with the 2 pin-5 pin of the 7U2 in the serial-parallel conversion output circuit, the output pin 3 of the chip 8U4-8U7 is respectively connected with the 1 pin, the 3 pin, the 5 pin and the 7 pin of the optical coupler 8U3 through the row resistor 8RP101 and the LED 8D301-8D304, and the 2 pin, the 4 pin, the 6 pin and the 8 pin of the optical coupler 8U3 are grounded;

3. A split-type data interaction intelligent terminal system based on the data interaction intelligent host terminal of claim 1, which is characterized in that: the intelligent data interaction system comprises a data interaction intelligent host terminal, a data bus and a 1 st slave terminal to an N slave terminal, wherein N is an integer larger than 1; the structures of the 1 st slave terminal to the N th slave terminal are the same, and the expansion forms from the 1 st slave terminal to the N th slave terminal are cascade connection; the data interaction intelligent host terminal is connected with the Nth slave terminal through the 1 st slave terminal, the 2 nd slave terminal, … and the N-1 th slave terminal in sequence; the data interaction intelligent host terminal, the 1 st slave terminal and the N th slave terminal are respectively connected to the data bus;

4. A modular data interaction intelligent terminal system according to claim 3, wherein: the auxiliary machine isolating card comprises an auxiliary machine AI isolating card circuit and an auxiliary machine AO isolating card circuit, wherein the auxiliary machine AI isolating card circuit and the AI isolating card circuit have the same structure, and the auxiliary machine AO isolating card circuit and the AO isolating card circuit have the same structure; the output end of the slave machine AI isolation card circuit is singly connected with the corresponding input end of the slave machine core control unit, the output end of the slave machine core control unit is connected with the corresponding input end of the slave machine AO isolation card circuit, and the output end of the slave machine AO isolation card circuit is connected with the analog control signal port; the corresponding output ends of the slave power management unit are respectively connected with the power input ends of the slave AI isolation card circuit and the slave AO isolation card circuit.

5. A modular data interaction intelligent terminal system according to claim 3, wherein: the secondary machine isolation card comprises a secondary machine DIDO isolation card circuit, and the secondary machine DIDO isolation card circuit and the DIDO isolation card circuit have the same structure; the slave DIDO isolation card circuit is connected with the slave core control unit in a bidirectional manner; the slave DIDO isolation card circuit is connected with the switch signal port in a bidirectional manner; and the corresponding output end of the slave power management unit is connected with the power input end of the slave DIDO isolation card circuit.

6. A method for communicating by using the spliced data interaction intelligent terminal system as claimed in claim 3, characterized in that the communication by using the beacon relay master module and the beacon relay slave module comprises the following specific steps: