CN108429894B

CN108429894B - Image sensor, electronic device, and image processing method

Info

Publication number: CN108429894B
Application number: CN201710082449.0A
Authority: CN
Inventors: 裴学用; 郭先清
Original assignee: BYD Co Ltd
Current assignee: BYD Semiconductor Co Ltd
Priority date: 2017-02-15
Filing date: 2017-02-15
Publication date: 2020-03-31
Anticipated expiration: 2037-02-15
Also published as: CN108429894A

Abstract

The invention discloses an image sensor, which comprises: a plurality of pixels including a pixel to be resolved and a reference pixel; the comparator also comprises a third switch connected between the first input end and the output end of the comparator and between the second input end and the output end; the waveform generator is connected with the second input end of the comparator through a second capacitor; the input end of the counter is connected with the output end of the comparator; the first latch is connected with the output end of the counter through a fourth switch, and the second latch is connected with the output end of the counter through a fifth switch; and the controller is used for controlling the first switch to the fifth switch so as to generate a conversion result according to the Reset Signal and the Signal output by the pixel to be analyzed and the reference pixel, thereby effectively eliminating power supply noise of the pixel array and improving the analysis precision.

Description

Image sensor, electronic device, and image processing method

Technical Field

The present invention relates to the field of image processing technologies, and in particular, to an image sensor, an electronic device, and an image processing method.

Background

CMOS Image Sensors (CIS) are increasingly widely used due to their advantages of low power consumption, integration of sensors and readout circuits on the same chip, and the like. The image sensor in the related art generally includes a pixel (pixel) array and a corresponding readout circuit, and due to the existence of metal trace parasitics, power supply inconsistency of each column in practical applications is caused, so that power supply noise is generated due to differences between columns, where the power supply noise may include power supply noise caused by power supply inconsistency of the pixel array and power supply noise caused by power supply inconsistency of the readout circuit.

However, the related art has a disadvantage in that power supply noise caused by power supply inconsistency of the pixel array cannot be eliminated.

Therefore, improvements are needed in the related art.

Disclosure of Invention

The present invention is directed to solving, at least to some extent, one of the technical problems in the art described above. To this end, an object of the present invention is to provide an image sensor capable of effectively removing power supply noise of a pixel array.

Another object of the present invention is to provide an electronic device. It is a further object of the invention to propose an image processing method.

In order to achieve the above object, an embodiment of an aspect of the present invention provides an image sensor, including: a plurality of pixels, wherein the plurality of pixels comprise a pixel to be resolved and a reference pixel; the pixel resolution control circuit comprises a comparator, a first switch, a second switch, a third switch and a control circuit, wherein the comparator comprises a first input end, a second input end and an output end, the first input end is connected with a first capacitor, the first capacitor is respectively connected with the reference pixel and the pixel to be analyzed through the first switch and the second switch, and the third switch is connected between the first input end and the output end and between the second input end and the output end; the waveform generator is connected with the second input end of the comparator through a second capacitor; the input end of the counter is connected with the output end of the comparator; the first latch is connected with the output end of the counter through a fourth switch, and the second latch is connected with the output end of the counter through a fifth switch; and the controller is used for controlling the first switch to the fifth switch so as to generate a conversion result according to the Reset Signal and the Signal output by the pixel to be analyzed and the reference pixel.

According to the image sensor provided by the embodiment of the invention, the controller controls the first switch to the fifth switch to be switched on or off, the pixel to be analyzed and the reference pixel are controlled to output the Reset Signal, then the pixel to be analyzed and the reference pixel are controlled to output the Signal, and the conversion result is generated according to the Reset Signal and the Signal output by the pixel to be analyzed and the reference pixel, so that the power supply noise of the pixel array can be effectively eliminated, the pixel to be analyzed is analyzed, and the pixel analysis precision is improved.

In order to achieve the above object, another embodiment of the present invention provides an electronic device, which includes the image sensor.

According to the electronic device provided by the embodiment of the invention, the power supply noise of the pixel can be eliminated through the image sensor, the pixel to be analyzed is analyzed, and the pixel analysis precision is improved.

In order to achieve the above object, an embodiment of a further aspect of the present invention provides an image processing method, in which an image sensor includes a plurality of pixels, a comparator, a waveform generator, a counter, a first latch and a second latch, wherein the plurality of pixels include a pixel to be resolved and a reference pixel, the comparator includes a first input terminal, a second input terminal and an output terminal, the first input terminal is connected to a first capacitor, the first capacitor is connected to the reference pixel and the pixel to be resolved through a first switch and a second switch, respectively, the comparator further includes a third switch connected between the first input terminal and the output terminal and the second input terminal and the output terminal, the waveform generator is connected to the second input terminal of the comparator through a second capacitor, and an input terminal of the counter is connected to an output terminal of the comparator, the first latch is connected to the output terminal of the counter through a fourth switch, and the second latch is connected to the output terminal of the counter through a fifth switch, wherein the method comprises the following steps: controlling the pixel to be analyzed and the reference pixel to output a Reset signal; controlling the pixel to be analyzed and the reference pixel to output a Signal; and generating a conversion result according to the Reset Signal and the Signal output by the pixel to be analyzed and the reference pixel.

According to the image processing method provided by the embodiment of the invention, the pixel to be analyzed and the reference pixel are controlled to output the Reset Signal, then the pixel to be analyzed and the reference pixel are controlled to output the Signal, and the conversion result is generated according to the Reset Signal and the Signal output by the pixel to be analyzed and the reference pixel, so that the power supply noise of the pixel array can be effectively eliminated, the analysis of the pixel to be analyzed is realized, and the pixel analysis precision is improved.

Drawings

FIG. 1 is a circuit schematic of an image sensor according to one embodiment of the present invention;

FIG. 2 is a block schematic diagram of an image sensor according to one embodiment of the invention;

FIG. 3 is a diagram illustrating a control timing of an image sensor according to an embodiment of the present invention;

FIG. 4 is a circuit schematic of an image sensor according to another embodiment of the invention;

FIG. 5 is a block diagram of an electronic device according to an embodiment of the invention; and

fig. 6 is a flowchart of an image processing method according to an embodiment of the present invention.

Description of the drawings:

a plurality of pixels 10, a comparator 20, a waveform generator 30, a counter 40, a first latch 50, a second latch 60, and a controller 70;

a pixel to be analyzed 101 and a reference pixel 102;

first to fifth switches S1 to S5; an analog-to-digital converter 1;

a comparison circuit 80; the first MOS transistor MOS1 to the fifth MOS transistor MOS 5;

electronic device 100 and image sensor 200.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

An image sensor, an electronic apparatus, and an image processing method according to embodiments of the present invention are described below with reference to the accompanying drawings.

Fig. 1 is a block diagram of an image sensor according to an embodiment of the present invention. As shown in fig. 1, an image sensor of an embodiment of the present invention includes: the method comprises the following steps: a plurality of pixels 10, a comparator 20, a waveform generator 30, a counter 40, a first latch 50, a second latch 60, and a controller 70.

The pixels 10 include pixels 101 to be analyzed and reference pixels 102; the comparator 20 comprises a first input terminal IN1, a second input terminal IN2 and an output terminal OUT, the first input terminal IN1 is connected with a first capacitor C1, the first capacitor C1 is connected with the reference pixel 102 and the pixel 101 to be resolved through a first switch S1 and a second switch S2 respectively, the comparator 20 further comprises a third switch S3 connected between the first input terminal IN1 and the output terminal OUT, and the second input terminal IN2 and the output terminal OUT; the waveform generator 30 is connected to the second input terminal IN2 of the comparator 20 via a second capacitor C2; the input terminal of the counter 40 is connected to the output terminal OUT of the comparator 20; the first latch 50 is connected to the output terminal OUT of the counter 40 through the fourth switch S4, and the second latch 60 is connected to the output terminal OUT of the counter 40 through the fifth switch S5; the controller 70 is configured to control the first switch S1 to the fifth switch S5 to generate a conversion result according to the Reset Signal and the Signal output by the pixel 101 to be analyzed and the reference pixel 102.

Specifically, in the embodiment of the present invention, the comparator 20, the waveform generator 30, the counter 40, the first latch 50, the second latch 60, and the controller 70 may constitute an Analog-to-Digital Converter (ADC) 1. Wherein, the waveform generator 30 is used to output a falling single-slope ramp Signal, and the comparator 20 receives signals output by the pixels, i.e. Reset Signal and Signal, through a first input terminal IN1, and receives the ramp Signal output by the waveform generator 30 through a second input terminal IN 2; the comparator 20 is used for comparing the signal output by the pixel with the ramp signal output by the waveform generator 30, and when the two signals are equal, the level signal output by the output end OUT of the comparator 20 is inverted; the counter 40 is configured to receive the level signal output by the output terminal OUT of the comparator 20, record a time taken for the level signal output by the comparator 20 to fall from the ramp signal, convert the time into a clock cycle number, and output the clock cycle number in a binary form, i.e., a digital signal form; the first latch 50 and the second latch 60 are used to store the digital signal output from the counter 40.

Further, in one embodiment of the present invention, as shown in fig. 2, the plurality of pixels 10 may be pixels of any column in a pixel array, and the signal output by each pixel includes a Reset signal V_rAnd Signal V_sWherein V is_rGreater than V_s. Selecting any one row in the pixel array as a reference row, and taking at least one row in the rest rows as a row to be detectedAnalyzing a line, namely a normal pixel line needing analysis, wherein the reference line comprises a plurality of reference pixels 102, the line to be analyzed comprises a plurality of pixels 101 to be analyzed, and the reference pixels 102 of the reference line are subjected to light-free processing so as to enable Reset signals V output by the reference pixels 102_r0And Signal V_s0Only the power supply noise signal of the pixel array remains.

It should be noted that the pixels are used for converting optical signals into electrical signals, so that the subsequent circuits convert the electrical signals into binary digital codes for output. In order to eliminate the fixed noise of the pixel array, the current processing method adopts a correlated double sampling method, that is, the pixel is reset once first, so that the first voltage output by the pixel is the reset signal V in the scheme_r0Wherein the reset signal V_r0Is changed with time, the first voltage is sampled so as to obtain a reset signal V_r0The voltage value is valid only for a period of time. Then, the pixel is exposed to light, so that the pixel outputs a second voltage, namely a signal V in the scheme_s0Wherein the signal V_s0The voltage value of the second voltage is also changed along with the time, and the second voltage is sampled so as to obtain a signal V_s0The voltage value is valid only for a period of time.

As shown in fig. 2, a plurality of columns of pixels in the pixel array correspond to a plurality of analog-to-digital converters 1, a reference pixel 102 and a pixel 101 to be analyzed in each column are connected to a first input terminal of the corresponding analog-to-digital converter 1 through a first switch S1 and a second switch S2, respectively, and a waveform generator 30 is connected to a second input terminal of the analog-to-digital converter 1 corresponding to each column, that is, the analog-to-digital converters 1 corresponding to the plurality of columns of pixels share the same waveform generator 30, so that, in the working process of the image sensor, the analog-to-digital converter 1 performs analog-to-digital conversion on signals output by the pixel 101 to be analyzed and the reference pixel 102, that is, a Reset Signal and a Signal, and subtracts the Signal output by the reference pixel 102 in the corresponding column from the Signal output by the pixel 101 to be analyzed in a digital circuit.

According to an embodiment of the present invention, if a plurality of pixels in the plurality of pixels 10 are selected as the pixels 101 to be analyzed, the output ends of the plurality of pixels 101 to be analyzed may be connected to the first input end of the analog-to-digital converter 1 through the second switch S2, or the plurality of pixels 101 to be analyzed may be correspondingly connected to the plurality of second switches S2, that is, each pixel 101 to be analyzed is connected to the first input end of the analog-to-digital converter 1 through the corresponding second switch S2.

It should be noted that the Reset signal V output by the pixel 101 to be analyzed_r1And Reset signal V output by reference pixel 102_r0At the same time, Signal V output by pixel 101 to be analyzed_s1And Reset signal V output by reference pixel 102_r0Occurring simultaneously. Specifically, during the operation of the image sensor, the pixel 101 to be analyzed first outputs the Reset signal V_r1While the reference pixel 102 outputs a Reset signal V_r0The controller 70 controls the first to fifth switches S1 to S5 to be turned on or off according to the control timing shown in fig. 3, wherein a high level indicates that the corresponding switch is turned on and a low level state indicates that the corresponding switch is turned off, thereby outputting a Reset signal V according to the pixel 101 to be analyzed_r1And Reset signal V output by reference pixel 102_r0A first conversion result is generated and stored in the first latch 50. Then, the pixel 101 to be analyzed outputs a Signal V_s1While the reference pixel 102 outputs a Signal V_s0The controller 70 controls the first switch S1 to the fifth switch S5 to be turned on or off according to the control timing shown in fig. 3, so as to output the Signal V according to the pixel 101 to be analyzed_s1And Signal V output by reference pixel 102_s0A second conversion result is generated and stored in the second latch 60. Further, the first conversion result stored in the first latch 50 is subtracted from the second conversion result stored in the second latch 60 to generate a final conversion result.

Therefore, power supply noise of the pixels can be eliminated, the pixels to be analyzed can be analyzed, and the accuracy of pixel analysis is improved.

The following describes a specific operation principle of the image sensor according to the embodiment of the present invention, taking a column in the pixel array as an example, with reference to fig. 1 and 3.

According to an embodiment of the present invention, the controller 70 is further configured to control the third switch S3 to be closed to reset the comparator 20, and control the first switch S1 to be closed, wherein a closing time of the first switch S1 is shorter than a closing time of the third switch S3, and sequentially control the second switch S2 and the fourth switch S4 to be closed after the third switch S3 is opened to store the first conversion result in the first latch 50.

Wherein the first conversion result may be ((V)_{ramp_max}-V_ramp0)-(V_r1-V_r0) Wherein V is_{ramp_max}Is a preset ramp level, V, of waveform generator 30_ramp0Is a preset initial level, V, of the waveform generator 30_r1Is the Reset signal, V, of the pixel 101 to be resolved_r0Is the Reset signal of the reference pixel 102, wherein the preset initial level V of the waveform generator_ramp0Less than the preset ramp level V of the waveform generator_{ramp_max}。

According to an embodiment of the present invention, the controller 70 is further configured to control the third switch S3 to be closed to reset the comparator 20, and control the first switch S1 to be closed, wherein a closing time of the first switch S1 is shorter than a closing time of the third switch S3, and sequentially control the second switch S2 and the fifth switch S5 to be closed after the third switch S3 is opened to store the second conversion result in the second latch 60.

Wherein the second conversion result may be ((V)_{ramp_max}-V_ramp0)-(V_s1-V_s0) Wherein V is_{ramp_max}Is a preset ramp level, V, of waveform generator 30_ramp0Is a preset initial level, V, of the waveform generator 30_s1Is the Signal, V, of the pixel 101 to be analyzed_s0Is the Signal of the reference pixel 102, wherein the preset initial level V of the waveform generator_ramp0Less than the preset ramp level V of the waveform generator_{ramp_max}。

Specifically, as shown in FIG. 3, the process of obtaining the conversion result includes two working phases, i.e., phase I and phase II, wherein the controller 70 is at t shown in FIG. 3₁To t₄Time of day andt shown in FIG. 3₁To t₄Time t controls the third switch S3 to close, and at t shown in fig. 3₂To t₃Time of day and t shown in FIG. 3₂To t₃Time "controls the first switch S1 to close such that the closing time of the first switch S1 is less than the closing time of the third switch S3.

In the I stage, the pixel 101 to be analyzed outputs a Reset signal V_r1The reference pixel 102 outputs a Reset signal V_r0The controller 70 is at t shown in FIG. 3₁The third switch S3 is momentarily controlled to close to connect the input and output of the comparator 20 to reset the comparator 20, when the input and output of the comparator 20 are equal and equal to the reference voltage V_refWherein the reference voltage V_refThe voltage value at the first input IN1 of the comparator 20 is denoted as V, depending on the circuit parameters_nThe voltage value at the second input IN2 of the comparator 20 is denoted as V_pThen V when the third switch S3 is closed_p＝V_n＝V_ref。

Then, the controller 70 is at t shown in fig. 3₂The first switch S1 is controlled to close again at this moment, and the reference pixel 102 will Reset the signal V_r0The voltage is output to the first capacitor C1, and assuming that the capacitance Q1 of the first capacitor C1 is equal to the capacitance Q2 of the second capacitor C2 and is denoted as Q, the charge on the first capacitor C1 is Q (V × (V)_ref-V_r0). At this time, the initial level output by the waveform generator 30 is recorded as the preset initial level V_ramp0The charge on the second capacitor C2 is Q (V)_ref-V_ramp0) Wherein an initial level V is preset_ramp0Lower than a preset slope level V_{ramp_max}。

Further, the controller 70 first starts at t shown in fig. 3₃The first switch S1 is turned off at time t shown in FIG. 3₄At time t, the third switch S3 is turned off, and then at time t shown in fig. 3₅The second switch S2 is controlled to close at the moment, and the pixel 101 to be analyzed sends a Reset signal V_r1Output to the first capacitor C1, and the output of the waveform generator 30 is made to preset a ramp level V_{ramp_max}At this time, the voltage value of the first input terminal IN1 of the comparator 20 is recordedIs a V_n1The voltage value at the second input IN2 of the comparator 20 is denoted as V_p1Then, the charge on the first capacitor C1 is Q (V) at this time_n1-V_r1) The charge on the second capacitor C2 is Q (V)_p1-V_{ramp_max}). According to the law of conservation of charge, before and after the third switch S3 is turned off, the charges on the first capacitor C1 and the second capacitor C2 are respectively kept unchanged, and then

For the first capacitance C1, the following equation (1) is satisfied, namely:

Q*(V_ref-V_r0)＝Q*(V_n1-V_r1) (1)

from the formula (1), V_n1＝V_ref+(V_r1-V_r0) (2)

For the second capacitance C2, the following equation (3) is satisfied, namely:

Q*(V_ref-V_ramp0)＝Q*(V_p1-V_{ramp_max}) (3)

from the formula (3), V_p1＝V_ref+(V_{ramp_max}-V_ramp0) (4)

As can be seen from the above equations (2) and (4), the preset ramp level V is output from the waveform generator 30_{ramp_max}At time t shown in fig. 3₅At the moment, the voltage V of the first input IN1 of the comparator 20_n1And the voltage V of the second input terminal IN2 of the comparator 20_p1Satisfies the following formula (5), i.e.

V_p1-V_n1＝(V_{ramp_max}-V_ramp0)-(V_r1-V_r0) (5)

At this time, the comparator 20 outputs a first level, for example, a high level, to the counter 40, and the counter 40 receives the high level and starts counting from zero. Since waveform generator 30 outputs a falling single-slope ramp signal, at t₅After the time, the output level of the waveform generator 30 starts to fall, and when the input voltage V of the comparator 20 is exceeded_p1-V_n1When the output level is equal to 0, the output level of the comparator 20 is inverted, and the counter 40 is controlled to stop counting, thereby obtaining a first conversion result (V)_{ramp_max}-V_ramp0)-(V_r1-V_r0). Further, controlThe brake 70 is at t shown in FIG. 3₆The second switch S2 is controlled to be opened at the moment t shown in FIG. 3₇The timing controls the fourth switch S4 to be closed to store the first conversion result in the first latch 50.

It should be noted that, in the phase I, the input voltage V of the comparator 20 can be used_r0-V_r1The first conversion result is obtained, however, due to the uncertainty of the circuit, V_r0-V_r1The value of (c) may be positive or negative, and eventually a correct conversion result may not be obtained. The image sensor of the embodiment of the present invention introduces (V) through the second input terminal IN2 of the comparator 20_{ramp_max}-V_ramp0) Can ensure the input voltage V of the comparator 20_p1-V_n1And is greater than 0, thereby accurately obtaining the first conversion result.

In stage II, the pixel 101 to be analyzed outputs a Signal V_s1The reference pixel 102 outputs a Signal V_s0The controller 70 is at t shown in FIG. 3₁Moment controlling the third switch S3 to close to connect the input and the output of the comparator 20 to reset the comparator 20, when the input and the output of the comparator 20 are equal and equal to the reference voltage V_refWherein the reference voltage V_refThe voltage value at the first input IN1 of the comparator 20 is denoted as V, depending on the circuit parameters_nThe voltage value at the second input IN2 of the comparator 20 is denoted as V_pThen V when the third switch S3 is closed_p＝V_n＝V_ref。

Then, the controller 70 is at t shown in fig. 3₂At time point I again controlling the first switch S1 to close, the reference pixel 102 will output the Signal Signal V_s0The voltage is output to the first capacitor C1, and assuming that the capacitance Q1 of the first capacitor C1 is equal to the capacitance Q2 of the second capacitor C2 and is denoted as Q, the charge on the first capacitor C1 is Q (V × (V)_ref-V_s0). At this time, the initial level output by the waveform generator 30 is recorded as the preset initial level V_ramp0The charge on the second capacitor C2 is Q (V)_ref-V_ramp0) Wherein an initial level V is preset_ramp0Lower than a preset slope level V_{ramp_max}。

Further, the controller 70 first starts at t shown in fig. 3₃The first switch S1 is turned off at time t shown in FIG. 3₄Moment t controls the third switch S3 to open, then at t shown in fig. 3₅At time point, the second switch S2 is controlled to be closed, and at this time point, the pixel to be analyzed 101 outputs a Signal V_s1Output to the first capacitor C1, and the output of the waveform generator 30 is made to preset a ramp level V_{ramp_max}At this time, the voltage value at the first input terminal IN1 of the comparator 20 is denoted as V_n1The voltage value at the second input IN2 of the comparator 20 is denoted as V_p1Then, the charge on the first capacitor C1 is Q (V) at this time_n1-V_s1) The charge on the second capacitor C2 is Q (V)_p1-V_{ramp_max}). According to the law of conservation of charge, before and after the third switch S3 is turned off, the charges on the first capacitor C1 and the second capacitor C2 are respectively kept unchanged, and then

For the first capacitance C1, the following equation (6) is satisfied, namely:

Q*(V_ref-V_s0)＝Q*(V_n1-V_s1) (6)

from the formula (6), V_n1＝V_ref+(V_s1-V_s0) (7)

For the second capacitance C2, the following equation (3) is satisfied, namely:

Q*(V_ref-V_ramp0)＝Q*(V_p1-V_{ramp_max}) (3)

from the formula (3), V_p1＝V_ref+(V_{ramp_max}-V_ramp0) (8)

As can be seen from the above equations (7) and (3), the preset ramp level V is output from the waveform generator 30_{ramp_max}At time t shown in fig. 3₅Time, the voltage V of the first input IN1 of the comparator 20_n1And the voltage V of the second input terminal IN2 of the comparator 20_p1Satisfies the following formula (9), i.e.

V_p1-V_n1＝(V_{ramp_max}-V_ramp0)-(V_s1-V_s0) (9)

At this time, the comparator 20 outputs a first level, for example, a high level, to the counter 40The counter 40 receives a high level and starts counting from zero. Since waveform generator 30 outputs a falling single-slope ramp signal, at t₅After time point, the output level of the waveform generator 30 starts to fall when the input voltage V of the comparator 20_p1-V_n1When the output level is equal to 0, the output level of the comparator 20 is inverted, and the counter 40 is controlled to stop counting, thereby obtaining a second conversion result (V)_{ramp_max}-V_ramp0)-(V_s1-V_s0). Further, the controller 70 is at t shown in fig. 3₆At time t shown in fig. 3, the second switch S2 is controlled to be opened₇Time-point controls the fifth switch S5 to close to store the second conversion result in the second latch 60.

It should be noted that, in the phase II, the input voltage V of the comparator 20 can be used_s0-V_s1Obtain a second conversion result, however, due to the uncertainty of the circuit, V_s0-V_s1The value of (c) may be positive or negative, and eventually a correct conversion result may not be obtained. The image sensor of the embodiment of the present invention introduces (V) through the second input terminal IN2 of the comparator 20_{ramp_max}-V_ramp0) Can ensure the input voltage V of the comparator 20_p1-V_n1And is greater than 0, thereby accurately obtaining a second conversion result.

According to one embodiment of the present invention, the conversion result may be ((V)_r1-V_s1)-(V_r0-V_s0))。

Specifically, the first conversion result is (V)_{ramp_max}-V_ramp0)-(V_r1-V_r0) And a second conversion result, i.e., (V)_{ramp_max}-V_ramp0)-(V_s1-V_s0) Both being digital signals, e.g. binary strings, the controller 70, after having obtained the first and second conversion results, implements the second conversion result minus the first conversion result in the digital circuit, i.e., ((V)_{ramp_max}-V_ramp0)-(V_s1-V_s0))-((V_{ramp_max}-V_ramp0)-(V_r1-V_r0))＝(V_r1-V_s1)-(V_r0-V_s0) So as to be output according to the pixel 101 to be analyzedGoes out Reset signal V_r1The reference pixel 102 outputs a Reset signal V_r0And the pixel 101 to be analyzed outputs a Signal V_s1And the reference pixel 102 outputs a Signal V_s0Obtaining a conversion result ((V)_r1-V_s1)-(V_r0-V_s0))。

As described above, the conversion result finally acquired by the controller 70 may be ((V)_r1-V_s1)-(V_r0-V_s0) Wherein (V)_r1-V_s1) Can represent the conversion result of the pixel 101 to be analyzed, (V)_r0-V_s0) Can represent the conversion result of the reference pixel 102 due to the Reset signal V output by the reference pixel 102_r0And Signal V_s0Only the power supply noise signal is retained, will (V)_r1-V_s1) And (V)_r0-V_s0) In contrast, the power supply noise held in the reference pixel 102 can be removed from the conversion result of the pixel 101 to be analyzed, that is, the power supply noise of the pixel can be eliminated.

According to another embodiment of the present invention, the comparator 20 may employ the comparison circuit 80 shown in fig. 4. The comparison circuit 80 includes: the first MOS transistor MOS1 to the fifth MOS transistor MOS 5.

The drain D of the first MOS transistor MOS1 is connected to a preset power supply VDD, and the gate G of the first MOS transistor MOS1 is connected to the bias generation circuit 90; the drain D of the second MOS transistor MOS2 is connected to the drain D of the third MOS transistor MOS3, a first node is provided between the drain D of the second MOS transistor MOS2 and the drain D of the third MOS transistor MOS3, the first node is connected to the source S of the first MOS transistor MOS1, and the gate G of the second MOS transistor MOS2 is connected to the first capacitor C1, wherein the gate G of the second MOS transistor MOS2 is equivalent to the first input terminal IN1 IN the circuit shown IN fig. 1, which is connected to the first capacitor C1, and the gate G of the third MOS transistor MOS3 is equivalent to the second input terminal IN2 IN the circuit shown IN fig. 1, which is connected to the second capacitor C2. The drain D of the fourth MOS transistor MOS4 is connected with the source S of the second MOS transistor MOS2, and a second node V is arranged between the drain D of the fourth MOS transistor MOS4 and the source S of the second MOS transistor MOS2_oSecond node V_oThe source S of the fourth MOS tube MOS4 is grounded and is connected with the grid G of the second MOS tube MOS2 through a third switch S3; drain D and third of the fifth MOS transistor MOS5The source S of the MOS transistor MOS3 is connected, and a third node v is arranged between the drain D of the fifth MOS transistor MOS5 and the source S of the third MOS transistor MOS3_obThird node v_obThe third switch S3 is connected to the gate G of the third MOS transistor MOS3, the source S of the fifth MOS transistor MOS5 is grounded, the fifth MOS transistor MOS5 is connected to the gate G of the fourth MOS transistor MOS4, a fourth node is provided between the gate G of the fifth MOS transistor MOS5 and the gate G of the fourth MOS transistor MOS4, and the fourth node is connected to the drain D of the fifth MOS transistor MOS 5. Wherein the second node V_oEquivalent to the output OUT of the circuit shown in fig. 1, which is connected to the counter 40.

According to an embodiment of the present invention, the first MOS transistor MOS1 to the third MOS transistor MOS3 may be P-channel MOS transistors, and the fourth MOS transistor MOS4 and the fifth MOS transistor MOS5 may be N-channel MOS transistors.

Specifically, when the third switch S3 is turned on, the comparator circuit 80 enters a reset state, and the first input terminal IN1, the second input terminal IN2, and the second node V_oAnd a third node V_obThe voltages at the four terminals are equal, and the voltage value is equal to the reference voltage V in the above embodiment_ref. Wherein the reference voltage V_refThe value of (c) is determined by the current flowing through the fifth MOS transistor MOS5 and its size.

In summary, according to the image sensor provided in the embodiment of the present invention, the controller controls the first switch to the fifth switch to be turned on or off, the pixel to be analyzed and the reference pixel are controlled to output the Reset Signal, the pixel to be analyzed and the reference pixel are controlled to output the Signal, and the conversion result is generated according to the Reset Signal and the Signal output by the pixel to be analyzed and the reference pixel, so that power supply noise of the pixel array can be effectively eliminated, the pixel to be analyzed is analyzed, and the accuracy of pixel analysis is improved.

Fig. 5 is a block diagram of an electronic device according to an embodiment of the invention. As shown in fig. 5, the electronic device 100 includes an image sensor 200.

In summary, according to the electronic device of the embodiment of the invention, the power supply noise of the pixel array can be effectively eliminated through the image sensor, so that the resolution of the pixels to be resolved is realized, and the precision of the pixel resolution is improved.

Fig. 6 is a flowchart of an image processing method according to an embodiment of the present invention. The image sensor comprises a plurality of pixels, a comparator, a waveform generator, a counter, a first latch and a second latch, wherein the pixels comprise pixels to be analyzed and reference pixels, the comparator comprises a first input end, a second input end and an output end, the first input end is connected with a first capacitor, the first capacitor is respectively connected with the reference pixels and the pixels to be analyzed through a first switch and a second switch, the comparator further comprises a third switch connected between the first input end and the output end and between the second input end and the output end, the third switch waveform generator is connected with the second input end of the comparator through the second capacitor, the input end of the counter is connected with the output end of the comparator, the first latch is connected with the output end of the counter through a fourth switch, and the second latch is connected with the output end of the counter through a fifth switch.

As shown in fig. 6, the image processing method includes the steps of:

s10: and controlling the pixel to be analyzed and the reference pixel to output a Reset signal.

S20: and controlling the pixel to be analyzed and the reference pixel to output a Signal.

S30: and generating a conversion result according to the Reset Signal and the Signal output by the pixel to be analyzed and the reference pixel.

Specifically, in an embodiment of the present invention, the comparator, the waveform generator, the counter, the first latch, and the second latch may constitute an analog-to-digital converter. The comparator receives signals output by the pixels, namely Reset signals and Signal signals, through a first input end and receives the ramp signals output by the waveform generator through a second input end; the comparator is used for comparing the signal output by the pixel with the ramp signal output by the waveform generator, and when the signal output by the pixel is equal to the ramp signal output by the waveform generator, the level signal output by the output end of the comparator is inverted; the counter is used for receiving the level signal output by the output end of the comparator, recording the time for the level signal output by the comparator to turn over from the beginning of the ramp signal, converting the time into the number of clock cycles, and outputting the number of clock cycles in a binary form, namely a digital signal form; the first latch and the second latch are used for storing the digital signal output by the counter.

Further, in one embodiment of the present invention, the plurality of pixels may be pixels of any column in the pixel array, and the signal output by each pixel includes a Reset signal V_rAnd Signal V_sWherein V is_rGreater than V_s. Selecting any one row in the pixel array as a reference row, taking at least one row in the rest rows as a row to be analyzed, namely a normal pixel row needing analysis, wherein the reference row comprises a plurality of reference pixels, the row to be analyzed comprises a plurality of pixels to be analyzed, and carrying out matte processing on the reference pixels of the reference row so as to enable Reset signals V output by the reference pixels_r0And Signal V_s0Only the power supply noise signal remains. The reference pixels and the pixels to be analyzed in the same column are respectively connected with the first input ends of the analog-to-digital converters through the first switches and the second switches, the waveform generator is connected with the second input ends of the analog-to-digital converters in all columns, namely the analog-to-digital converters in all columns share the same waveform generator, therefore, in the working process of the image sensor, the analog-to-digital converters perform analog-to-digital conversion on signals output by the pixels to be analyzed and the reference pixels, namely Reset signals and Signal signals, and subtract the signals output by the reference pixels in the corresponding columns from the signals output by the pixels to be analyzed in a digital circuit so as to eliminate power supply noise of the pixels.

According to an embodiment of the present invention, if a plurality of pixels in the plurality of pixels are selected as pixels to be analyzed, the output ends of the plurality of pixels to be analyzed may be connected to the first input end of the analog-to-digital converter through the second switch, or the plurality of pixels to be analyzed may be correspondingly connected to the plurality of second switches, that is, each pixel to be analyzed is respectively connected to the first input end of the analog-to-digital converter through the corresponding second switch.

It should be noted that the Reset signal V output by the pixel to be analyzed_r1And Reset signal V output from reference pixel_r0Simultaneous appearance of Signal V output by pixel to be analyzed_s1And Reset signal V output from reference pixel_r0Occur simultaneously。

More specifically, the pixel to be resolved first outputs a Reset signal V_r1The reference pixel outputs a Reset signal V_r0And controlling the first to fifth switches to be turned on or off according to the control timing shown in fig. 3, wherein a high level indicates that the corresponding switch is turned on, and a low level state indicates that the corresponding switch is turned off, so as to output a Reset signal V according to the pixel to be analyzed_r1And Reset signal V output from reference pixel_r0A first conversion result is generated and stored in a first latch. Then, the pixel to be analyzed outputs a Signal V_s1The reference pixel outputs a Signal V_s0And controlling the first to fifth switches to be turned on or off according to the control timing shown in FIG. 3, so as to output Signal V according to the pixel to be analyzed_s1And Signal V output by reference pixel_s0A second conversion result is generated and stored in a second latch. Further, the first conversion result stored in the first latch is subtracted from the second conversion result stored in the second latch to generate a final conversion result.

The following describes a specific operation principle of the image sensor according to the embodiment of the present invention, taking a column in the pixel array as an example, with reference to fig. 3.

According to an embodiment of the present invention, generating a first conversion result according to Reset signals output by a pixel to be resolved and a reference pixel comprises: controlling the third switch to be closed to reset the comparator, and controlling the first switch to be closed, wherein the closing time of the first switch is less than that of the third switch; after the third switch is turned off, the second switch and the fourth switch are sequentially controlled to be turned on and off to store the first conversion result in the first latch.

Wherein the first conversion result may be ((V)_{ramp_max}-V_ramp0)-(V_r1-V_r0) Wherein V is_{ramp_max}Is a preset ramp level, V, of the waveform generator_ramp0Is a preset initial level, V, of the waveform generator_r1Is the Reset signal, V, of the pixel to be resolved_r0Is Reset signal of reference pixel, wherein the preset initial level V of waveform generator_ramp0Less than the preset ramp level V of the waveform generator_{ramp_max}。

According to an embodiment of the present invention, generating a second conversion result according to a Signal output by a pixel to be analyzed and a reference pixel includes: controlling the third switch to be closed to reset the comparator, and controlling the first switch to be closed, wherein the closing time of the first switch is less than that of the third switch; after the third switch is opened, the second switch and the fifth switch are sequentially controlled to be closed to store the second conversion result in the second latch.

According to an embodiment of the present invention, the second conversion result may be ((V)_{ramp_max}-V_ramp0)-(V_s1-V_s0) Wherein V is_{ramp_max}Is a preset ramp level, V, of the waveform generator_ramp0Is a preset initial level, V, of the waveform generator_s1Signal, V, for the pixel to be resolved_s0Is Signal of reference pixel, wherein the preset initial level V of waveform generator_ramp0Less than the preset ramp level V of the waveform generator_{ramp_max}。

In one embodiment according to the present invention, as shown in FIG. 3, the process of obtaining the conversion result includes two working phases, i.e., phase I and phase II, where t is shown in FIG. 3₁To t₄Time of day and t shown in FIG. 3₁To t₄Time t controls the third switch to close, and at t shown in fig. 3₂To t₃Time of day and t shown in FIG. 3₂To t₃Moment-time controls the first switch to close such that the closing time of the first switch is less than the closing time of the third switch.

In the I stage, the pixel to be analyzed outputs a Reset signal V_r1The reference pixel outputs a Reset signal V_r0At t shown in FIG. 3₁The third switch is controlled to be closed at any time to connect the input end and the output end of the comparator so as to carry out the complex operation on the comparatorBit, when the input and output of the comparator are equal and equal to the reference voltage V_refWherein the reference voltage V_refThe voltage value of the first input end of the comparator is recorded as V according to the parameters of the circuit_nThe voltage value of the second input end of the comparator is marked as V_pWhen the third switch is closed, V_p＝V_n＝V_ref。

Then, at t shown in FIG. 3₂The first switch is controlled to be closed at the moment, and the Reset signal V is sent by the reference pixel_r0Output to the first capacitor, and assuming that the capacitance Q1 of the first capacitor is equal to the capacitance Q2 of the second capacitor and both are denoted as Q, the charge on the first capacitor is Q (V)_ref-V_r0). At this time, the initial level output by the waveform generator is recorded as a preset initial level V_ramp0The charge on the second capacitor is Q (V)_ref-V_ramp0) Wherein an initial level V is preset_ramp0Lower than a preset slope level V_{ramp_max}。

Furthermore, first, t shown in FIG. 3₃The first switch S1 is turned off at time t shown in FIG. 3₄The third switch is controlled to be turned off at time t, and then at t shown in fig. 3₅The second switch is controlled to be closed at the moment, and the pixel to be analyzed sends a Reset signal V at the moment_r1Output to the first capacitor, and at the same time, output of the waveform generator is enabled to preset a slope level V_{ramp_max}At this time, the voltage value of the first input terminal of the comparator is marked as V_n1The voltage value of the second input end of the comparator is marked as V_p1Then the charge on the first capacitor is Q (V) at this time_n1-V_r1) The charge on the second capacitor is Q (V)_p1-V_{ramp_max}). According to the law of conservation of charge, before and after the third switch is switched off, the charges on the first capacitor and the second capacitor are respectively kept unchanged, and then

For the first capacitance, the following equation (1) is satisfied, namely:

Q*(V_ref-V_r0)＝Q*(V_n1-V_r1) (1)

from the formula (1), V_n1＝V_ref+(V_r1-V_r0) (2)

For the second capacitance, the following equation (3) is satisfied, namely:

Q*(V_ref-V_ramp0)＝Q*(V_p1-V_{ramp_max}) (3)

from the formula (3), V_p1＝V_ref+(V_{ramp_max}-V_ramp0) (4)

As can be seen from the above equations (2) and (4), the preset ramp level V is outputted from the waveform generator_{ramp_max}At time t shown in fig. 3₅At the moment, the voltage V of the first input terminal of the comparator_n1And the voltage V of the second input terminal of the comparator_p1Satisfies the following formula (5), i.e.

V_p1-V_n1＝(V_{ramp_max}-V_ramp0)-(V_r1-V_r0) (5)

At this time, the comparator outputs a first level, for example, a high level, to the counter, and the counter receives the high level and starts counting from zero. Since the waveform generator outputs a falling single-slope ramp signal at t₅After the time, the output level of the waveform generator begins to drop, when the input voltage V of the comparator_p1-V_n1When the voltage is equal to 0, the output level of the comparator is inverted, the counter is controlled to stop counting, and a first conversion result, namely (V) is obtained_{ramp_max}-V_ramp0)-(V_r1-V_r0). Further, at t shown in FIG. 3₆The second switch is controlled to be turned off at the moment t shown in figure 3₇The fourth switch is controlled to be turned on and off at a time to store the first conversion result in the first latch.

It should be noted that, in the stage I, the input voltage V of the comparator can be used_r0-V_r1The first conversion result is obtained, however, due to the uncertainty of the circuit, V_r0-V_r1The value of (c) may be positive or negative, and eventually a correct conversion result may not be obtained. The image sensor of the embodiment of the invention introduces (V) through the second input end of the comparator_{ramp_max}-V_ramp0) Can ensure the input voltage V of the comparator_p1-V_n1And is greater than 0, thereby accurately obtaining the first conversion result.

In the II stage, the pixel to be analyzed outputs a Signal V_s1The reference pixel outputs a Signal V_s0At t shown in FIG. 3₁Moment-control the third switch to close to connect the input and the output of the comparator to reset the comparator, when the input and the output of the comparator are equal and equal to the reference voltage V_refWherein the reference voltage V_refThe voltage value of the first input end of the comparator is recorded as V according to the parameters of the circuit_nThe voltage value of the second input end of the comparator is marked as V_pWhen the third switch is closed, V_p＝V_n＝V_ref。

Then, the controller 70 is at t shown in fig. 3₂At time point the first switch is again controlled to be closed, and the reference pixel 102 sends a Signal V_s0Output to the first capacitor, and assuming that the capacitance Q1 of the first capacitor is equal to the capacitance Q2 of the second capacitor and both are denoted as Q, the charge on the first capacitor is Q (V)_ref-V_s0). At this time, the initial level output by the waveform generator is recorded as a preset initial level V_ramp0The charge on the second capacitor is Q (V)_ref-V_ramp0) Wherein an initial level V is preset_ramp0Lower than a preset slope level V_{ramp_max}。

Furthermore, first, t shown in FIG. 3₃The first switch S1 is turned off at time t shown in FIG. 3₄Moment t controls the third switch to open, then at t shown in fig. 3₅At time point, the second switch is controlled to be closed, and the pixel to be analyzed sends a Signal V_s1Output to the first capacitor, and at the same time, output of the waveform generator is enabled to preset a slope level V_{ramp_max}At this time, the voltage value of the first input terminal of the comparator is marked as V_n1The voltage value of the second input end of the comparator is marked as V_p1Then the charge on the first capacitor is Q (V) at this time_n1-V_s1) The charge on the second capacitor is Q (V)_p1-V_{ramp_max}). According to the law of conservation of charge, before and after the third switch is switched off, the charges on the first capacitor and the second capacitor are respectively kept unchanged, and then

For the first capacitance, the following equation (6) is satisfied, namely:

Q*(V_ref-V_s0)＝Q*(V_n1-V_s1) (6)

from the formula (6), V_n1＝V_ref+(V_s1-V_s0) (7)

For the second capacitance, the following equation (3) is satisfied, namely:

Q*(V_ref-V_ramp0)＝Q*(V_p1-V_{ramp_max}) (3)

from the formula (3), V_p1＝V_ref+(V_{ramp_max}-V_ramp0) (8)

As can be seen from the above equations (7) and (3), the preset ramp level V is outputted from the waveform generator_{ramp_max}At time t shown in fig. 3₅At time, the voltage V of the first input of the comparator_n1And the voltage V of the second input terminal of the comparator_p1Satisfies the following formula (9), i.e.

V_p1-V_n1＝(V_{ramp_max}-V_ramp0)-(V_s1-V_s0) (9)

At this time, the comparator outputs a first level, for example, a high level, to the counter, and the counter receives the high level and starts counting from zero. Since the waveform generator outputs a falling single-slope ramp signal at t₅After time point, the output level of the waveform generator starts to fall when the input voltage V of the comparator is exceeded_p1-V_n1When the voltage is equal to 0, the output level of the comparator is inverted, the counter is controlled to stop counting, and a second conversion result, namely (V) is obtained_{ramp_max}-V_ramp0)-(V_s1-V_s0). Further, at t shown in FIG. 3₆At time t shown in FIG. 3₇Time controls the fifth switch to close to store the second conversion result in the second latch.

It should be noted that, in the phase II, the input voltage V of the comparator can be used_s0-V_s1Obtain a second conversion result, however, due to the uncertainty of the circuit, V_s0-V_s1The value of (c) may be positive or negative, and eventually a correct conversion result may not be obtained. The image sensor of the embodiment of the invention introduces (V) through the second input end of the comparator_{ramp_max}-V_ramp0) Can ensure the input voltage V of the comparator_p1-V_n1And is greater than 0, thereby accurately obtaining a second conversion result.

Specifically, the first conversion result is (V)_{ramp_max}-V_ramp0)-(V_r1-V_r0) And a second conversion result, i.e., (V)_{ramp_max}-V_ramp0)-(V_s1-V_s0) Both digital signals, e.g. binary strings, and after obtaining the first and second conversion results, the first conversion result is subtracted from the second conversion result, i.e., ((V)_{ramp_max}-V_ramp0)-(V_s1-V_s0))-((V_{ramp_max}-V_ramp0)-(V_r1-V_r0))＝(V_r1-V_s1)-(V_r0-V_s0) Thereby outputting a Reset signal V according to the pixel to be analyzed_r1Reference pixel output Reset signal V_r0Outputting Signal V to the pixel to be analyzed_s1And a reference pixel output Signal Signal V_s0Obtaining a conversion result ((V)_r1-V_s1)-(V_r0-V_s0))。

As described above, the conversion result finally obtained may be ((V)_r1-V_s1)-(V_r0-V_s0) Wherein (V)_r1-V_s1) Can represent the conversion result of the pixel to be analyzed, (V)_r0-V_s0) Can represent the conversion result of the reference pixel due to the Reset signal V output by the reference pixel_r0And Signal V_s0Only the power supply noise signal is retained, will (V)_r1-V_s1) And (V)_r0-V_s0) In contrast, the power supply noise held in the reference pixel can be removed from the conversion result of the pixel to be analyzed, that is, the power supply noise of the pixel can be eliminated.

In summary, according to the image processing method provided by the embodiment of the present invention, the pixel to be analyzed and the reference pixel are controlled to output the Reset Signal, the pixel to be analyzed and the reference pixel are controlled to output the Signal, and the conversion result is generated according to the Reset Signal and the Signal output by the pixel to be analyzed and the reference pixel, so that power noise of the pixel array can be effectively eliminated, the pixel to be analyzed can be analyzed, and the pixel analysis accuracy is improved.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims

1. An image sensor, comprising:

a plurality of pixels, wherein the plurality of pixels comprise a pixel to be resolved and a reference pixel;

the pixel resolution control circuit comprises a comparator, a first switch, a second switch, a third switch and a control circuit, wherein the comparator comprises a first input end, a second input end and an output end, the first input end is connected with a first capacitor, the first capacitor is respectively connected with the reference pixel and the pixel to be analyzed through the first switch and the second switch, and the third switch is connected between the first input end and the output end and between the second input end and the output end;

the waveform generator is connected with the second input end of the comparator through a second capacitor;

the input end of the counter is connected with the output end of the comparator;

the first latch is connected with the output end of the counter through a fourth switch, and the second latch is connected with the output end of the counter through a fifth switch;

the controller is used for controlling the first switch to the fifth switch so as to generate a conversion result according to a Reset Signal and a Signal output by the pixel to be analyzed and the reference pixel;

the controller is used for controlling the third switch to be closed so as to reset the comparator, controlling the first switch to be closed, wherein the closing time of the first switch is shorter than that of the third switch, and sequentially controlling the second switch and the fourth switch to be closed after the third switch is opened so as to store a first conversion result in the first latch;

the first conversion result is ((V)_{ramp_max}-V_ramp0)-(V_r1-V_r0) Wherein V is_{ramp_max}Is a preset ramp level, V, of the waveform generator_ramp0Is a preset initial level, V, of the waveform generator_r1Is the Reset signal, V, of the pixel to be resolved_r0A Reset signal for the reference pixel, wherein the preset initial level V of the waveform generator_ramp0Less than the preset ramp level V of the waveform generator_{ramp_max}。

2. The image sensor of claim 1,

the controller is configured to control the third switch to be closed to reset the comparator, and control the first switch to be closed, where a closing time of the first switch is shorter than a closing time of the third switch, and sequentially control the second switch and the fifth switch to be closed after the third switch is opened, so as to store a second conversion result in the second latch.

3. The image sensor of claim 2, wherein the second conversion result is ((V)_{ramp_max}-V_ramp0)-(V_s1-V_s0) Wherein V is_{ramp_max}Is a preset ramp level, V, of the waveform generator_ramp0Is a preset initial level, V, of the waveform generator_s1Is Signal of the pixel to be analyzed, V_s0Signal of the reference pixel, wherein the preset initial level V of the waveform generator_ramp0Less than the preset ramp level V of the waveform generator_{ramp_max}。

4. The image sensor of claim 3, wherein the conversion result is ((V)_r1-V_s1)-(V_r0-V_s0))。

5. An electronic device, characterized in that it comprises an image sensor according to any one of claims 1-4.

6. An image processing method is characterized in that an image sensor comprises a plurality of pixels, a comparator, a waveform generator, a counter, a first latch and a second latch, the plurality of pixels comprise a pixel to be analyzed and a reference pixel, the comparator comprises a first input end, a second input end and an output end, the first input end is connected with a first capacitor, the first capacitor is respectively connected with the reference pixel and the pixel to be analyzed through a first switch and a second switch, the comparator further comprises a third switch connected between the first input end and the output end and between the second input end and the output end, the waveform generator is connected with the second input end of the comparator through a second capacitor, the input end of the counter is connected with the output end of the comparator, the first latch is connected with the output end of the counter through a fourth switch, the second latch is connected to the output of the counter via a fifth switch, wherein the method comprises the steps of:

controlling the pixel to be analyzed and the reference pixel to output a Reset signal;

controlling the pixel to be analyzed and the reference pixel to output a Signal;

generating a conversion result according to the Reset Signal and the Signal output by the pixel to be analyzed and the reference pixel;

generating a first conversion result according to Reset signals output by the pixel to be analyzed and the reference pixel, wherein the first conversion result comprises the following steps:

controlling the third switch to close to reset the comparator and controlling the first switch to close, wherein the closing time of the first switch is less than the closing time of the third switch;

sequentially controlling the second switch and the fourth switch to be turned on after the third switch is turned off to store a first conversion result in the first latch;

7. The image processing method of claim 6, wherein generating a second conversion result from Signal signals output by the pixel to be analyzed and the reference pixel comprises:

after the third switch is opened, the second switch and the fifth switch are sequentially controlled to be closed so as to store a second conversion result in the second latch.

8. The image processing method according to claim 7, wherein the second conversion result is ((V)_{ramp_max}-V_ramp0)-(V_s1-V_s0) Wherein V is_{ramp_max}Is a preset ramp level, V, of the waveform generator_ramp0Is a preset initial level, V, of the waveform generator_s1Is Signal of the pixel to be analyzed, V_s0Signal of the reference pixel, wherein the preset initial level V of the waveform generator_ramp0Less than the preset ramp level V of the waveform generator_{ramp_max}。

9. The image processing method according to claim 8, wherein the conversion result is ((V)_r1-V_s1)-(V_r0-V_s0))。