CN108429537B - Photovoltaic inverter fault processing circuit and electronic equipment - Google Patents
Photovoltaic inverter fault processing circuit and electronic equipment Download PDFInfo
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- CN108429537B CN108429537B CN201810301825.5A CN201810301825A CN108429537B CN 108429537 B CN108429537 B CN 108429537B CN 201810301825 A CN201810301825 A CN 201810301825A CN 108429537 B CN108429537 B CN 108429537B
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- 238000001514 detection method Methods 0.000 claims abstract description 44
- 238000006243 chemical reaction Methods 0.000 claims abstract description 20
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- 239000003990 capacitor Substances 0.000 claims description 13
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02S—GENERATION OF ELECTRIC POWER BY CONVERSION OF INFRARED RADIATION, VISIBLE LIGHT OR ULTRAVIOLET LIGHT, e.g. USING PHOTOVOLTAIC [PV] MODULES
- H02S50/00—Monitoring or testing of PV systems, e.g. load balancing or fault identification
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
- H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
- H02H7/122—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for inverters, i.e. dc/ac converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/56—Power conversion systems, e.g. maximum power point trackers
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- Inverter Devices (AREA)
Abstract
The invention discloses a photovoltaic inverter fault processing circuit and electronic equipment. The fault processing circuit comprises a main control board, a PWM anti-through and level conversion module, a fault detection module and a fault processing module, wherein the main control board comprises a processor and a PWM wave generation module which are mutually connected, and PWM signals sent by the PWM wave generation module are sent to the photovoltaic inverter through the PWM anti-through and level conversion module; the output end of the fault detection module is connected with the input end of the fault processing module, and the output end of the fault processing module is connected with the connecting end of the PWM anti-through and level conversion module and the photovoltaic inverter; the fault detection module is used for sending a fault signal to the fault processing module when the fault of the photovoltaic system is detected; the fault processing module is used for blocking the PWM signals sent to the photovoltaic inverter by the PWM wave generating module after receiving the fault signals sent by the fault detection module. The invention can improve the fault processing speed and ensure the safe operation of the photovoltaic inverter system.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a photovoltaic inverter fault processing circuit and electronic equipment.
Background
In order to enable safe operation of the power electronics system, technical means of providing a fault protection circuit are generally employed in order to provide effective protection in the event of a system failure. Most of the current systems only provide a software protection function, namely, fault information is directly provided to a processor (such as a DSP) of a main control board, and then the processor starts an external hardware structure to perform fault processing. In the whole fault processing process, software programs in a processor of the main control board must participate in cooperation, and some faults (such as faults of overvoltage and overcurrent of bus voltage) cannot be processed in time due to the limitation of software in the processor, so that the safety of the system is reduced. In addition, many fault handling circuits currently employ integrated chips, which are expensive, resulting in high production costs.
Disclosure of Invention
The invention provides a photovoltaic inverter fault processing circuit and electronic equipment, which are used for solving the problems.
According to one aspect of the invention, a fault processing circuit of a photovoltaic inverter is provided, the fault processing circuit comprises a main control board, a PWM anti-through and level conversion module, a fault detection module and a fault processing module, the main control board comprises a processor and a PWM wave generation module which are connected with each other, and PWM signals sent by the PWM wave generation module are sent to the photovoltaic inverter through the PWM anti-through and level conversion module; the output end of the fault detection module is connected with the input end of the fault processing module, and the output end of the fault processing module is connected with the connecting end of the PWM anti-through and level conversion module and the photovoltaic inverter;
the fault detection module is used for sending a fault signal to the fault processing module when the fault of the photovoltaic system is detected;
the fault processing module is used for blocking the PWM signals sent to the photovoltaic inverter by the PWM wave generating module after receiving the fault signals sent by the fault detection module.
According to another aspect of the present invention, there is provided an electronic device comprising a photovoltaic inverter fault handling circuit as described above.
The beneficial effects of the invention are as follows: according to the technical scheme, the fault detection module detects faults in the photovoltaic system, and once the faults of the photovoltaic system are detected, fault signals are immediately sent to the fault processing module, the fault processing module directly locks the PWM signals sent to the photovoltaic inverter by the PWM wave generation module, so that the photovoltaic inverter stops working, the fault signals are effectively processed in time directly through a hardware structure, and compared with the prior art, the fault processing speed is improved, and the safe operation of the photovoltaic inverter system is ensured. In addition, the photovoltaic inverter fault processing circuit disclosed by the invention is composed of conventional hardware circuits, so that high-cost integrated chips are prevented from being applied, the production cost is reduced, and the fault processing circuit can be used for photovoltaic inverters with different power levels and has a wide application range.
Drawings
FIG. 1 is a schematic functional block diagram of a photovoltaic inverter fault handling circuit according to one embodiment of the present invention;
FIG. 2 is a circuit diagram of a fault detection module according to one embodiment of the present invention;
FIG. 3 is a circuit diagram of a fault handling module according to one embodiment of the present invention;
FIG. 4 is a circuit diagram of a PWM anti-pass and level shift module according to one embodiment of the present invention;
fig. 5 is a functional structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The design concept of the invention is as follows: aiming at the problems that in the prior art, fault signals can only be processed by external hardware controlled by a software program, and some faults can not be processed in time due to the limitation of software in a processor, the inventor thinks that a fault processing circuit is constructed, and when a photovoltaic system breaks down, a PWM signal sent to a photovoltaic inverter by a PWM wave generating module is directly blocked by the fault processing circuit.
Example 1
Fig. 1 is a functional schematic diagram of a fault handling circuit of a photovoltaic inverter according to an embodiment of the present invention, as shown in fig. 1, the fault handling circuit of a photovoltaic inverter includes a main control board 110, a PWM anti-pass and level conversion module 120, a fault detection module 130 and a fault handling module 140, the main control board 110 includes a processor 111 and a PWM wave generation module 112 that are connected to each other, and PWM signals sent by the PWM wave generation module 112 are sent to a photovoltaic inverter 200 through the PWM anti-pass and level conversion module 120; the output end of the fault detection module 130 is connected with the input end of the fault processing module 140, and the output end of the fault processing module 140 is connected with the connection end of the PWM anti-through and level conversion module 120 and the photovoltaic inverter 200; the fault detection module 130 is configured to send a fault signal to the fault processing module 140 when a fault of the photovoltaic system is detected; the fault processing module 140 is configured to block the PWM signal sent to the photovoltaic inverter 200 by the PWM wave generating module 112 after receiving the fault signal sent by the fault detecting module 130.
Therefore, the fault detection module in the technical scheme of the invention detects faults in the photovoltaic system, and immediately sends fault signals to the fault processing module once the faults of the photovoltaic system are detected, the fault processing module directly locks the PWM signals sent to the photovoltaic inverter by the PWM wave generation module, so that the photovoltaic inverter stops working, the fault signals are effectively processed in time directly through a hardware structure, and compared with the prior art, the fault processing speed is improved, and the safe operation of the photovoltaic inverter system is ensured. In addition, the photovoltaic inverter fault processing circuit disclosed by the invention is composed of conventional hardware circuits, so that high-cost integrated chips are prevented from being applied, the production cost is reduced, and the fault processing circuit can be used for photovoltaic inverters with different power levels and has a wide application range.
In this embodiment, as shown in fig. 1, the output end of the fault detection module 130 is further connected to the input end of the processor 111, and the first control end of the fault processing module 140 is connected to the blocking instruction output end of the processor 111; the fault detection module 130 is further configured to send a fault signal to the processor 111 when a fault of the photovoltaic system is detected; the processor 111 is configured to send a control instruction for blocking the PWM signal to the fault processing module 140 after receiving the fault signal sent by the fault detection module 130, so as to control the fault processing module 140 to perform blocking processing on the PWM signal sent by the PWM wave generating module 112 to the photovoltaic inverter 200 again.
Therefore, when the photovoltaic system fails, the technical scheme of the invention realizes soft and hard parallel processing, namely, the PWM wave can be blocked directly through a hardware structure, the hardware structure can be blocked again according to the control instruction of the blocking PWM signal sent by the processor, double protection is realized, the first blocking failure is prevented, and the safety of the photovoltaic inverter system is further improved.
In this embodiment, the fault handling module 140 is connected to the dc breaker 150, the photovoltaic inverter 200 is connected to the dc power supply 300 through the dc breaker 150, and the fault handling module 140 is further configured to send a disconnection control instruction to the dc breaker 150 after receiving the fault signal sent by the fault detection module 130, so as to control the dc breaker 150 to disconnect the photovoltaic inverter 200 from the dc power supply 300. As is well known, the primary function of a photovoltaic inverter is to convert the direct current of a direct current power supply into alternating current, and once the connection between the photovoltaic inverter and the direct current power supply is broken, the photovoltaic inverter stops operating. Therefore, after the fault processing module receives the fault signal sent by the fault detection module, a disconnection control instruction is sent to the direct current breaker so as to control the direct current breaker to disconnect the connection between the photovoltaic inverter and the direct current power supply, and the photovoltaic inverter stops working and is protected multiply, so that the two blockage failures are prevented, and the safety of the photovoltaic inverter system is further improved.
The second control end of the fault handling module 140 is connected to the fault reset signal output end of the processor 111, and the fault handling module 140 is further configured to control the fault reset signal to fail when the fault signal of the fault detection module 130 and the fault reset signal of the processor 111 are received at the same time, so as to prevent false triggering of the processor 111. For the power electronic system, the serious fault signals include overvoltage and overcurrent faults of the direct current bus, direct current leakage current detection faults, alternating current leakage current detection faults, IGBT faults, emergency stop state monitoring signals and the like, and when the serious faults do not occur, the fault processing module 140 performs reset processing according to the fault reset signals sent by the received processor 111, that is, the fault reset signals sent by the processor 111 are valid at the moment. When a serious fault occurs, the fault processing module 140 starts an interlocking function, so that a fault reset signal sent by the processor 111 does not play any role, and the processor is prevented from being triggered by mistake, and plays a role of protecting a circuit. That is, once the system is judged to have serious faults, the fault signals do not eliminate the failure of the main control panel, and the power supply is required to be controlled to be electrified again to eliminate the faults, so that the safety of the system is improved.
In this embodiment, the processor 111 is further configured to send a control instruction for stopping operation to the PWM wave generating module 112 after receiving the fault signal sent by the fault detecting module 130, so as to control the PWM wave generating module 112 to stop sending the PWM signal. If the system fails, the PWM wave generating module 112 stops sending PWM signals, and the whole photovoltaic inverter system stops working, and multiple protection is performed, so that the safety of the system operation is further ensured.
In order to make the technical solution of the present invention more clear, a specific example is explained below.
Fig. 2 is a circuit diagram of a fault detection module according to an embodiment of the present invention, as shown in fig. 2, the fault detection circuit monitors a direct current bus overvoltage (dc_overvolt), an OverCurrent fault (dc_overcurrent), a direct current leakage current detection fault (GFDI), an alternating current leakage current detection fault (GFDI), IGBT faults (e.g., a_igbt_fault, b_igbt_fault, and c_igbt_fault) and an emergency STOP state (EMERG STOP), compares hardware protection circuits through a conventional operation, compares output signals after occurrence of corresponding faults to be valid as low level signals, and as long as any fault information is low level, forcibly pulls a 3.3V voltage of a subsequent circuit to be the low level signals through a diode connected in series with the fault detection circuit for processing by the fault processing module. Specifically, in fig. 2, the single_input is a fault signal to be detected, taking a direct current bus overvoltage (dc_overvolt) fault detection circuit as an example, when no direct current bus overvoltage (dc_overvolt) fault occurs, the forward terminal voltage of D1 is higher than the reverse terminal voltage of D1, and when the direct current bus overvoltage (dc_overvolt) fault detection circuit detects that the fault signal to be detected includes the direct current bus overvoltage signal, the forward terminal voltage of the diode D1 is lower than the reverse terminal voltage of D1, the voltage across the R1 is forced to be pulled to a low level, that is, the single_output is low level, as long as one of the branches where D1-D9 is located is low, and the single_output is low level. It should be noted that single_output in fig. 2 is single_input in fig. 3.
Fig. 3 is a circuit diagram of a fault handling module according to an embodiment of the present invention, where, as shown in fig. 3, the fault handling module 140 includes a fault handling sub-module 141, the fault handling sub-module 141 includes a first nand logic chip (U1C), a second nand logic chip (U1D), a first resistor (R12) and a first capacitor (C4), two input terminals of the first nand logic chip (U1C) are connected to an output terminal of the fault detection module 130, two input terminals of the first nand logic chip (U1C) are connected to an input terminal single_input of the fault handling module in fig. 3, and an output terminal of the first nand logic chip (U1C) is connected to a first input terminal of the second nand logic chip (U1D); the second input end of the second NAND gate logic chip (U1D) is connected with the blocking instruction output end of the processor 111, and is grounded through a first resistor (R12) and a first capacitor (C4) which are connected in parallel; the output end of the second nand gate logic chip (U1D) is connected to the connection end of the PWM anti-pass and level conversion module 120 and the photovoltaic inverter 200. When the fault detection module 130 detects that the system fails, the single_input is at a low level, the output end 8 of the first nand logic chip (U1C) is at a high level, the first input end 12 of the second nand logic chip (U1D) is at a high level, at this time, the second input end 13 of the second nand logic chip (U1D) is at a low level, and the output end 11 of the second nand logic chip (U1D) is at a high level, so as to realize hardware blocking of PWM waves.
Meanwhile, the blocking command output end of the processor 111 sends a blocking control command to the first control end (software_lock) of the fault handling module 140, and the blocking control command is at a low level, that is, the second input end 13 of the second nand gate logic chip (U1D) is at a low level, and then the output end of the second nand gate logic chip (U1D) is at a high level again, so that the hardware blocking PWM wave is realized again. Thus, PWM waves are blocked twice, and the safety of the system is improved.
In this embodiment, as shown in fig. 3, the fault handling module 140 further includes a dc breaker control submodule 142, where the dc breaker control submodule 142 includes a third nand gate logic chip (U10C); a first input terminal of the third nand gate logic chip (U10C) is connected to a feedback port (dc_break_feedback) of the DC breaker 150; the second input end of the third NAND gate logic chip (U10C) is connected with the output end of the first NAND gate logic chip (U1C) and the connecting end of the first input end of the second NAND gate logic chip (U1D); the output end of the third nand gate logic chip (U10C) is connected to the connection end of the photovoltaic inverter 200 and the dc power supply 300. As described above, the photovoltaic inverter 200 is connected to the dc power supply 300 via the dc breaker 150, and if the dc breaker 150 is opened, the photovoltaic inverter 200 stops operating. The feedback port (dc_break_feedback) of the DC breaker 150 in fig. 3 is low, i.e., the first input 9 of the third nand gate logic chip (U10C) is low; as described above, since the second input terminal of the third nand logic chip (U10C) is connected to the output terminal of the first nand logic chip (U1C), and when a fault occurs, the output terminal of the first nand logic chip (U1C) is at a high level, the second input terminal 10 of the third nand logic chip (U10C) is at a high level, and according to the characteristics of the nand gate, the output terminal 8 of the third nand logic chip (U10C) is at a high level, the high level signal is an off control command, and the connection between the photovoltaic inverter and the dc power supply is disconnected after the dc circuit breaker receives the high level signal, so that the photovoltaic inverter stops working, thereby playing a role of a protection circuit.
In this embodiment, as shown in fig. 3, the fault handling module 140 further includes an interlocking sub-module 143, where the interlocking sub-module 143 includes a fourth nand logic chip (U1A), a fifth nand logic chip (U1B), a second resistor (R10), and a second capacitor (C3); a first input end of the fourth nand gate logic chip (U1A) is connected to an output end of the fault detection module 130; the second input end of the fourth NAND gate logic chip (U1A) is connected with the output end of the fifth NAND gate logic chip (U1B); the output end of the fourth NAND gate logic chip (U1A) is respectively connected with the first input end of the fifth NAND gate logic chip (U1B) and the connecting ends of the two input ends of the first NAND gate logic chip (U1C); the second input end of the fifth NAND gate logic chip (U1B) is connected with the fault reset signal output end of the processor 111, and is grounded through a second resistor (R10) and a second capacitor (C3) which are connected in parallel. Specifically, the fault_reset in fig. 3 is a Fault Reset signal, and during normal operation, the main control board processor 111 sends out a low-level Fault Reset signal to perform Fault Reset; when a serious Fault occurs, the "single_input" is at a low level, that is, the first input terminal 1 of the fourth nand logic chip (U1A) is at a low level, the output terminal 1 of the fourth nand logic chip (U1A) is at a high level, and since the output terminal of the fourth nand logic chip (U1A) is connected to the first input terminal of the fifth nand logic chip (U1B), the first input terminal 4 of the fifth nand logic chip (U1B) is at a high level, and when the processor is transmitting the Fault Reset signal to the fault_reset, the second input terminal 5 of the fifth nand logic chip (U1B) is at a high level, the output terminal 6 of the fifth nand logic chip (U1B) is at a low level, and since the second input terminal 2 of the fourth nand logic chip (U1A) is connected to the output terminal 6 of the fifth nand logic chip (U1B), the second input terminal 2 of the fourth nand logic chip (U1A) is at a low level. When the processor sends out the fault reset signal, the second input terminal 5 of the fifth nand gate logic chip (U1B) is at a low level, the output terminal 6 of the fifth nand gate logic chip (U1B) is at a high level, and the output terminal 3 of the fourth nand gate logic chip (U1A) is still at a high level. When serious faults occur, the fault processing module starts an interlocking function, and controls the fault reset signal to fail, namely the processor cannot perform fault reset, so that false triggering of the processor is prevented, the function of protecting a circuit is achieved, and the safety of the system is improved.
When the fault handling module 140 includes the interlocking sub-module 143, the output end 8 of the first nand gate logic chip (U1C) is at a low level, and the output end of the second nand gate logic chip (U1D) is at a high level, so as to realize PWM wave blocking; however, when the first input end 9 of the third nand gate logic chip (U10C) is defined to be at a high level, the output end 8 of the third nand gate logic chip (U10C) is at a high level, so as to control the disconnection of the direct current breaker, ensure that when the system fails, the direct current breaker is controlled to disconnect the connection between the photovoltaic inverter and the direct current power supply, and the photovoltaic inverter stops working, thereby playing a role of a protection circuit.
In addition, as shown in fig. 3, in order to stabilize the voltages at the input terminals of the respective nand logic chips and to eliminate the influence of alternating current on the circuit, a pull-up resistor R9 and a filter capacitor C1 are provided at the first input terminal 1 of the fourth nand logic chip (U1A), a capacitor C2 is provided at the power supply terminal of the fourth nand logic chip (U1A), a pull-down resistor is provided at the connection terminal of the two input terminals of the first nand logic chip (U1C), a pull-up resistor R14 and a filter capacitor C7 are provided at the first input terminal 12 of the second nand logic chip (U1D), a pull-up resistor is provided at the output terminal 11 of the second nand logic chip (U1D), a resistor R12 and a filter capacitor C5 are provided at the first input terminal 9 of the third nand logic chip (U10C), and a filter capacitor C6 and a resistor R13 are provided at the first input terminal 10 of the third nand logic chip (U10C).
In this embodiment, the PWM anti-pass and level conversion module 120 is configured to perform an interlocking process on the three-phase full-bridge PWM wave signal sent by the PWM wave generation module, prevent the upper bridge arm and the lower bridge arm of the power device in the photovoltaic inverter from being simultaneously turned on, obtain the PWM signal after the interlocking process, and convert the voltage of the PWM signal after the interlocking process into the working voltage of the power device (e.g. IGBT) of the photovoltaic inverter. Specifically, fig. 4 is a circuit diagram of a PWM anti-pass and level conversion module according to an embodiment of the present invention, and as shown in fig. 4, the first portion 121 is a PWM anti-pass circuit, where a+, b+, and c+ are PWM wave high level signals; the A-, B-, and C-are PWM wave low-level signals, the U10D NAND gate and the U10A NAND gate form an RS first trigger, the U10B NAND gate and the U9C NAND gate form a second RS trigger, the U9D NAND gate and the U9A NAND gate form a third RS trigger, and the RS triggers have an interlocking function. The circuit performs interlocking processing on two paths of PWM signals of each phase of IGBT through the first RS trigger, the second RS trigger and the third RS trigger, so that upper and lower bridge arms are prevented from being conducted simultaneously, and a protection effect is achieved; the second part 122 is a PWM wave level conversion processing circuit, which converts the signals a1+, A1-, b1+, B1-, c1+, C1-outputted from the PWM anti-pass-through circuit 121, into 5V voltages required by a power unit driving board (e.g., a power device of an optical inverter) through a level conversion chip, and converts the 3.3V voltage of the PWM wave signal outputted from the PWM wave generation module 112.
Example two
Fig. 5 is a functional schematic diagram of an electronic device according to an embodiment of the present invention, and as shown in fig. 5, the electronic device 500 includes the photovoltaic inverter fault handling circuit 100 shown in fig. 1.
It should be noted that, the operation and the operation principle of the photovoltaic inverter fault handling circuit 100 are described in detail above, and are not described herein.
In summary, according to the technical scheme provided by the invention, the fault detection module detects faults in the photovoltaic system, and once the faults of the photovoltaic system are detected, fault signals are immediately sent to the fault processing module, and the fault processing module directly locks PWM signals sent to the photovoltaic inverter by the PWM wave generation module, so that the photovoltaic inverter stops working, the fault signals are effectively processed in time directly through a hardware structure, and compared with the prior art, the fault processing speed is improved, and the safe operation of the photovoltaic inverter system is ensured. In addition, the photovoltaic inverter fault processing circuit disclosed by the invention is composed of conventional hardware circuits, so that high-cost integrated chips are prevented from being applied, the production cost is reduced, and the fault processing circuit can be used for photovoltaic inverters with different power levels and has a wide application range.
The foregoing is merely a specific embodiment of the invention and other modifications and variations can be made by those skilled in the art in light of the above teachings. It is to be understood by persons skilled in the art that the foregoing detailed description is provided for the purpose of illustrating the invention more fully, and that the scope of the invention is defined by the appended claims.
Claims (4)
1. The fault processing circuit comprises a main control board, a PWM anti-through and level conversion module, a fault detection module and a fault processing module, wherein the main control board comprises a processor and a PWM wave generation module which are connected with each other, and PWM signals sent by the PWM wave generation module are sent to the photovoltaic inverter through the PWM anti-through and level conversion module; the PWM anti-pass and level conversion module is characterized in that the output end of the fault detection module is connected with the input end of the fault processing module, and the output end of the fault processing module is connected with the connecting end of the PWM anti-pass and level conversion module and the photovoltaic inverter;
the fault detection module is used for sending a fault signal to the fault processing module when the fault of the photovoltaic system is detected;
the fault processing module is used for blocking the PWM signals sent to the photovoltaic inverter by the PWM wave generating module after receiving the fault signals sent by the fault detection module;
the output end of the fault detection module is also connected with the input end of the processor, and the first control end of the fault processing module is connected with the blocking instruction output end of the processor;
the fault detection module is further used for sending the fault signal to the processor when the fault of the photovoltaic system is detected;
the processor is used for sending a control instruction for blocking the PWM signal to the fault processing module after receiving the fault signal sent by the fault detection module so as to control the fault processing module to block the PWM signal sent to the photovoltaic inverter by the PWM wave generation module again;
the second control end of the fault processing module is connected with the fault reset signal output end of the processor, and the fault processing module is further used for controlling the fault reset signal to fail when the fault signal of the fault detection module and the fault reset signal of the processor are received at the same time so as to prevent false triggering of the processor;
the fault processing module is connected with a direct current breaker, the photovoltaic inverter is connected with a direct current power supply through the direct current breaker, and the fault processing module is further used for sending a disconnection control instruction to the direct current breaker after receiving a fault signal sent by the fault detection module so as to control the direct current breaker to disconnect the connection between the photovoltaic inverter and the direct current power supply;
the fault processing module comprises a first NAND gate logic chip, a second NAND gate logic chip, a first resistor and a first capacitor, wherein two input ends of the first NAND gate logic chip are connected with the output end of the fault detection module, and the output end of the first NAND gate logic chip is connected with the first input end of the second NAND gate logic chip;
the second input end of the second NAND gate logic chip is connected with the blocking instruction output end of the processor, and is grounded through the first resistor and the first capacitor which are connected in parallel;
the output end of the second NAND gate logic chip is connected with the connecting end of the PWM anti-through and level conversion module and the photovoltaic inverter;
the fault processing module further comprises a third NAND gate logic chip;
the first input end of the third NAND gate logic chip is connected with the feedback port of the direct current breaker;
the second input end of the third NAND gate logic chip is connected with the output end of the first NAND gate logic chip and the connection end of the first input end of the second NAND gate logic chip;
the output end of the third NAND gate logic chip is connected with the connecting end of the photovoltaic inverter and the direct current power supply;
the fault processing module further comprises a fourth NAND gate logic chip, a fifth NAND gate logic chip, a second resistor and a second capacitor;
the first input end of the fourth NAND gate logic chip is connected with the output end of the fault detection module;
the second input end of the fourth NAND gate logic chip is connected with the output end of the fifth NAND gate logic chip;
the output end of the fourth NAND gate logic chip is respectively connected with the first input end of the fifth NAND gate logic chip and the connecting ends of the two input ends of the first NAND gate logic chip;
and the second input end of the fifth NAND gate logic chip is connected with the fault reset signal output end of the processor, and is grounded through the second resistor and the second capacitor which are connected in parallel.
2. The photovoltaic inverter fault handling circuit of claim 1,
the processor is further used for sending a control instruction for stopping working to the PWM wave generating module after receiving the fault signal sent by the fault detecting module so as to control the PWM wave generating module to stop sending PWM signals.
3. The photovoltaic inverter fault handling circuit of claim 1,
and the PWM anti-through and level conversion module is used for carrying out interlocking processing on the PWM signals sent by the PWM wave generation module, preventing the upper bridge arm and the lower bridge arm of the power device in the photovoltaic inverter from being simultaneously conducted, obtaining the PWM signals after the interlocking processing, and converting the voltage of the PWM signals after the interlocking processing into the working voltage of the power device of the photovoltaic inverter.
4. An electronic device comprising the photovoltaic inverter fault handling circuit of any of claims 1-3.
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| CN113608145B (en) * | 2021-07-14 | 2023-04-11 | 厦门科华数能科技有限公司 | Multi-path photovoltaic module ground fault detection device and detection method |
| CN114115043A (en) * | 2021-11-27 | 2022-03-01 | 沃太能源股份有限公司 | MCU reset system and have its reserve power supply |
| CN115206067A (en) * | 2022-07-11 | 2022-10-18 | 上海茵特格锐科技有限公司 | PWM signal alarm circuit for inverter |
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