CN108428732B - Super junction device and manufacturing method thereof - Google Patents

Super junction device and manufacturing method thereof Download PDF

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CN108428732B
CN108428732B CN201710080068.9A CN201710080068A CN108428732B CN 108428732 B CN108428732 B CN 108428732B CN 201710080068 A CN201710080068 A CN 201710080068A CN 108428732 B CN108428732 B CN 108428732B
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contact
contact hole
oxide film
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CN108428732A (en
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肖胜安
曾大杰
李东升
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Shenzhen Shangyangtong Technology Co ltd
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Shenzhen Sanrise Tech Co ltd
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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Abstract

The invention discloses a super junction device, wherein a charge flowing area is exposed by a protection ring oxidation film, a transition area is completely covered by the protection ring oxidation film, and a terminal area is completely or mostly covered by the protection ring oxidation film, so that a second contact hole at the top of a P-type ring of the transition area penetrates through the thickness of a protection ring oxidation film more than a first contact hole at the top of a P-type well of the charge flowing area, the junction depth of a second P + contact area at the bottom of the second contact hole is shallower than that of a first P + contact area at the bottom of the first contact hole, the distance from a hole collected by the P-type ring to the second P + contact area is increased, and the softness factor of reverse recovery of a body diode of the device is increased. The invention also discloses a manufacturing method of the super junction device. The invention can improve the reverse recovery characteristic of the device and enhance the avalanche tolerance of the device.

Description

Super junction device and manufacturing method thereof
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a super junction (super junction) device.
Background
The super junction structure is a structure formed by alternately arranged N-type columns and P-type columns. If a super junction structure is used for replacing an N-type drift region in a Vertical Double-diffused Metal-Oxide-Semiconductor (VDMOS) device, a conduction path is provided through an N-type column in a conduction state, and the P-type column does not provide the conduction path when the conduction state is conducted; under the cut-off state, the PN upright posts bear the reverse bias voltage together, so that a super-junction Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is formed. The super-junction MOSFET can greatly reduce the on-resistance of the device by using an epitaxial layer with low resistivity under the condition that the reverse breakdown voltage is consistent with that of a traditional VDMOS device.
In the existing super junction device, in a current flowing region, there are P-type columns and N-type columns which are alternately arranged, taking the structure of a strip-shaped P-N column, that is, a P-type column and an N-type column which are alternately arranged as an example, there is a polysilicon gate above each N column, the polysilicon gate may partially cover the peripheral P column or not, there is a P-type Well (P Well) above each P column, there is an N + source region in the P-type Well, there is a contact hole, source metal is connected with a source region through the contact hole, the source metal is connected with the P region, that is, the P-type Well through a high concentration P + contact region, and the source metal is a front metal layer constituting the source. In the transition region, there is a P-type ring, which covers 1 to many P-type columns, and the P-type ring can be completed by the same process as the P-type well, and there is a high concentration P + contact region in the P-type ring, and the P + contact region in the P-type ring and the P + contact region in the current flowing region are formed by the same process, and the concentration and junction depth are the same.
In the above conventional superjunction device structure, in order to improve the avalanche current tolerance of the device, a higher dose of P + contact region implantation is usually adopted, for example, the implantation dose is 1E15cm-2～3E15cm-2Such that the body concentration of the P + high concentration region of the P + contact region is higher than 1E19cm-3Therefore, Rb of a Pwell area, namely parasitic resistance of the Pwell is reduced, the avalanche tolerance of the device is enhanced, and the avalanche current tolerance is improved because: the Pwell resistance is reduced to reduce the base resistance of a parasitic NPN (negative-positive-negative), namely Rb, formed by a source region, a P-type well, an N-type column and a drain region, and the parasitic NPN tube can be started only when Vbe is larger than the threshold voltage of a diode formed by the Pwell, namely the P-type well, an N + region, namely the source region, so that the current reaching the same Vbe is increased after the Rb is reduced. However, since the P + contact region in the P-type ring in the transition region is also very dense, and the capability of collecting holes in the forward direction Vds is very strong, for the body diode of the device in the process from normal conduction to reverse bias, i.e. in the reverse recovery process, since the holes are quickly extracted through the P + region through the contact hole, the reverse recovery is fast, and the softness factor is poor.
Disclosure of Invention
The invention aims to provide a super junction device, which can improve the reverse recovery characteristic of the device and enhance the avalanche tolerance of the device. The invention also provides a manufacturing method of the super junction device.
In order to solve the technical problem, in the super junction device provided by the invention, the middle area of the super junction device is a charge flowing area, a terminal area surrounds the periphery of the charge flowing area, and a transition area is positioned between the charge flowing area and the terminal area; the method comprises the following steps:
the N-type epitaxial layer is subjected to dry etching to form a plurality of grooves; and filling a P-type epitaxial layer in the groove to form a P-type column, forming an N-type column by the N-type epitaxial layer among the P-type columns, and forming a super junction structure by a plurality of alternately arranged N-type columns and P-type columns.
Forming a P-type well in a selected region of the charge flow region and a P-type ring in a selected region of the transition region; one P-type well is formed at the top of each P-type column in the charge flowing region, and each P-type well extends to the surface of the corresponding N-type column on two sides of the P-type column.
A protective epoxy film that exposes the charge flow region and covers the transition region entirely, the protective epoxy film also extending to the termination region surface and exposing the termination region entirely or only an outermost peripheral portion of the termination region, the protective epoxy film surrounding a peripheral side of the charge flow region.
And a planar gate structure formed by overlapping a gate oxide film and a polysilicon gate is formed on the surface of the super junction structure of the charge flowing area, each polysilicon gate covers the corresponding P-type well, and the surface of the P-type well covered by the polysilicon gate is used for forming a channel.
And respectively forming active regions at two sides of the polysilicon gate in the charge flowing region.
And an interlayer film is formed on the front surface of the N-type epitaxial layer, and covers the surfaces of the protective epoxy film in the source region and the polysilicon gate of the charge flowing region, the transition region and the termination region.
A front metal layer is formed on the surface of the interlayer film; the grid electrode and the source electrode are formed by patterning the front metal layer; each of the source regions and the corresponding P-type well in the charge flow region are connected to the source electrode through a first contact hole having the same top, the P-type ring in the transition region is connected to the source electrode through a second contact hole having the same top, and the polysilicon gate is connected to the gate electrode through a third contact hole having the same top.
Each of the first contact holes is contacted through the interlayer film and the source region at the bottom and the P-type well at the bottom, each of the second contact holes is contacted through the lamination of the interlayer film and the guard ring oxide film and the P-type ring at the bottom, forming a first P + contact region at the bottom of each first contact hole, forming a second P + contact region at the bottom of each second contact hole, and making the junction depth of each second P + contact region shallower than that of the first P + contact region by utilizing the characteristic that each second contact hole needs to penetrate through the protective epoxy film so that the depth of the bottom of each second contact hole penetrating into the N-type epitaxial layer is shallower than that of the first contact hole penetrating into the N-type epitaxial layer, thereby increasing the distance that the holes collected by the P-type ring reach the second P + contact region, increasing the softness factor of the reverse recovery of the body diode of the device.
In a further improvement, the doping concentration of the first P + contact region and the second P + contact region are the same.
In a further improvement, the doping concentration of the second P + contact region is less than that of the first P + contact region, thereby reducing the hole collecting capability of the second P + contact region and increasing the reverse recovery softness factor of the body diode of the device.
In a further improvement, the peak value of the doping concentration of the second P + contact region is 1/2-1/10 of the peak value of the doping concentration of the first P + contact region.
A further improvement is that after the opening of the first contact hole is etched to a depth required for penetrating through the source region, the bottom of the second contact hole still retains a part of the thickness of the guard ring oxide film, the first P + contact region and the second P + contact region are simultaneously formed by adopting the same P + implantation process, the doping concentration of the second P + contact region is smaller than that of the first P + contact region due to the characteristic that the P + implantation of the second P + contact region can penetrate through the retained guard ring oxide film, and then the retained guard ring oxide film is removed.
Or, the opening of the first contact hole and the opening of the second contact hole are etched simultaneously by the same process, after the doping concentration required by forming the second P + contact region by overall P + injection is carried out, the second contact hole is protected by a photoetching process, and the concentration required by forming the first P + contact region by adding one P + injection to the bottom of each first contact hole.
In a further improvement, the width of the second contact hole is smaller than that of the first contact hole, so that the width of the second P + contact region is reduced, the distance from the P-type ring collected holes to the second P + contact region is increased from the transverse direction, and the softness factor of the reverse recovery of the body diode of the device is increased.
In a further improvement, the P-type ring covers more than two P-type columns, and the number of holes required to be collected in the reverse recovery process is increased, so that the softness factor of the reverse recovery of the body diode of the device is increased.
In a further improvement, the processes of the P-type ring and the P-type well are the same.
Or the process of the P-type ring is independent of the process of the P-type well, and the junction depth of the P-type ring is larger than that of the P-type well, so that the distance from the hole collected by the P-type ring to the second P + contact region is increased, and the reverse recovery softness factor of the body diode of the device is increased.
The further improvement is that the depth of the bottom of each second contact hole penetrating into the N-type epitaxial layer is 0-500 angstroms, and the depth of the first contact hole penetrating into the N-type epitaxial layer is more than 2000 angstroms.
In order to solve the technical problem, the middle area of the super junction device of the manufacturing method of the super junction device provided by the invention is a charge flowing area, a terminal area surrounds the periphery of the charge flowing area, and a transition area is positioned between the charge flowing area and the terminal area; the method comprises the following steps:
step one, providing an N-type epitaxial layer, defining a forming area of a groove by carrying out a first photoetching process, and then carrying out dry etching on the N-type epitaxial layer to form a plurality of grooves.
And filling a P-type epitaxial layer in the groove to form a P-type column, forming an N-type column by the N-type epitaxial layer among the P-type columns, and forming a super junction structure by a plurality of alternately arranged N-type columns and P-type columns.
Step two, defining a forming area of a P-type well in the charge flowing area and the transition area by carrying out a second photoetching process, and then carrying out P-type ion implantation to form the P-type well; a P-type ring is formed in the transition region.
One P-type well is formed at the top of each P-type column in the charge flowing region, and each P-type well extends to the surface of the corresponding N-type column on two sides of the P-type column.
And thirdly, growing a first oxide film on the surface of the N-type epitaxial layer on which the P-type well is formed, defining an etching area of the first oxide film by a third photoetching process, etching the first oxide film to form a guard ring oxide film, exposing the charge flowing area and completely covering the transition area by the guard ring oxide film, extending the guard ring oxide film to the surface of the terminal area and exposing the terminal area or only exposing the outermost periphery of the terminal area, wherein the guard ring oxide film surrounds the periphery of the charge flowing area.
And carrying out overall first N-type ion implantation by taking the guard ring oxide film as a self-alignment condition to form a JFET region in the charge flowing region, and simultaneously forming a terminal first N-type implantation region in or outside the terminal region outside the protection epoxy film covering region.
And step four, sequentially forming a gate oxide film and a first layer of N-type heavily doped polysilicon, defining a forming area of a polysilicon gate by performing a fourth photoetching process, etching the first layer of polysilicon to form polysilicon gates, wherein each polysilicon gate is of a planar gate structure, covers the corresponding P-type well, and is used for forming a channel on the surface of the P-type well covered by the polysilicon gate.
And carrying out comprehensive second N-type ion implantation by taking the polysilicon gate and the guard ring oxide film as self-alignment conditions to form source regions on two sides of the polysilicon gate in the charge flowing region respectively, and simultaneously forming a terminal second N-type implantation region in or outside the terminal region outside the protection epoxy film covering region.
And step five, depositing an interlayer film, defining a forming area of the contact hole by a fifth photoetching process, and then etching to form an opening of the contact hole.
The contact holes comprise first contact holes positioned at the tops of the source regions and the corresponding P-type wells in the charge flowing regions, second contact holes positioned at the tops of the P-type rings in the transition regions and third contact holes positioned at the tops of the polysilicon gates; each of the first contact holes passes through the interlayer film and the source region at the bottom and the P-type well contact at the bottom, and each of the second contact holes passes through the lamination of the interlayer film and the guard ring oxide film and the P-type ring contact at the bottom.
Performing P + implantation to form a first P + contact region at the bottom of each first contact hole and a second P + contact region at the bottom of the second contact hole; and by utilizing the characteristic that each second contact hole needs to penetrate through the protective epoxy film so that the depth of the bottom of each second contact hole penetrating into the N-type epitaxial layer is shallower than the depth of the first contact hole penetrating into the N-type epitaxial layer, the junction depth of the second P + contact region is shallower than the junction depth of the first P + contact region, so that the distance from a hole collected by the P-type ring to the second P + contact region is increased, and the reverse recovery softness factor of a body diode of the device is increased.
And filling metal in the opening of the contact hole to form the contact hole.
And sixthly, depositing front metal to form a front metal layer, defining forming areas of a grid electrode and a source electrode by carrying out a sixth photoetching process, etching the front metal layer to form the grid electrode and the source electrode, connecting each source region in the charge flowing region and the corresponding P-type well to the source electrode through the first contact hole with the same top, connecting the P-type ring in the transition region to the source electrode through the second contact hole on the top, and connecting the polysilicon gate to the grid electrode through the third contact hole on the top.
In a further improvement, in the fifth step, the opening of the first contact hole and the opening of the second contact hole are etched simultaneously by the same process, and the P + implantation processes of the first P + contact region and the second P + contact region are performed simultaneously and are the same, so that the doping concentrations of the first P + contact region and the second P + contact region are the same.
The further improvement is that in the fifth step, the opening of the first contact hole and the opening of the second contact hole are etched simultaneously by the same process, after the doping concentration required by forming the second P + contact region by overall P + injection is carried out, the second contact hole is protected by a photoetching process, the concentration required by forming the first P + contact region by one P + injection is added at the bottom of each first contact hole, so that the doping concentration of the second P + contact region is smaller than that of the first P + contact region, the capability of the second P + contact region for collecting holes is weakened, and the softness factor of the reverse recovery of the body diode of the device is increased.
Or after the opening of the first contact hole is etched to a depth required by penetrating through the source region, the bottom of the second contact hole also retains a part of thickness of the protection ring oxide film, the first P + contact region and the second P + contact region are simultaneously formed by adopting the same P + injection process, and the P + injection of the second P + contact region can penetrate through the retained characteristic of the protection ring oxide film to ensure that the doping concentration of the second P + contact region is smaller than that of the first P + contact region, so that the capability of the second P + contact region for collecting holes is weakened, and the softness factor of the reverse recovery of a body diode of the device is increased; and removing the remaining guard ring oxide film.
In a further improvement, the peak value of the doping concentration of the second P + contact region is 1/2-1/10 of the peak value of the doping concentration of the first P + contact region.
In a further improvement, in the second step, the P-type ring is formed simultaneously by the same process as the P-type well.
Or, in the second step, the P-type ring is formed by separately adopting a photoetching and ion implantation process, and the junction depth of the P-type ring is greater than that of the P-type well, so that the distance from the hole collected by the P-type ring to the second P + contact region is increased, and the reverse recovery softness factor of the body diode of the device is increased.
In a further improvement, the width of the second contact hole is smaller than that of the first contact hole, so that the width of the second P + contact region is reduced, the distance from the P-type ring collected holes to the second P + contact region is increased from the transverse direction, and the softness factor of the reverse recovery of the body diode of the device is increased.
In a further improvement, the P-type ring covers more than two P-type columns, and the number of holes required to be collected in the reverse recovery process is increased, so that the softness factor of the reverse recovery of the body diode of the device is increased.
The invention is specially arranged by the protective epoxy film, the protective epoxy film can expose the charge flowing area, completely cover the transition area and completely or mostly cover the terminal area; the characteristic that the guard ring oxide film covers the transition region is utilized, so that the contact hole at the top of the guard ring formed in the transition region, namely the second contact hole can simultaneously penetrate through the interlayer film and the guard ring oxide film, compared with the characteristic that the first contact hole at the top of the source region and the P-type well in the charge flow region only penetrates through the interlayer film, the first contact hole and the second contact hole are usually formed simultaneously by adopting the same process, therefore, the first contact hole can well over-etch the N-type epitaxial layer at the bottom and penetrate through the source region, the second contact hole only needs to over-etch the N-type epitaxial layer at the bottom and only needs to expose the top of the P-type ring, the junction depth of the second P + contact region formed at the bottom of the second contact hole can be shallower than the junction depth of the first P + contact region formed at the bottom of the first contact hole, and the distance of a hole collected by the P-type ring to the second P + contact region, increasing the reverse recovery softness factor of the body diode of the device, wherein the increase of the softness factor is to improve the reverse recovery characteristic of the device; in addition, the junction depth and doping of the first P + contact region are not influenced while the junction depth of the second P + contact region is reduced, and the avalanche resistance of the device can be enhanced simultaneously by utilizing the junction depth and doping conditions of the first P + contact region.
In addition, the invention can also utilize the characteristic that the top of the guard ring has a guard ring oxide film, when the openings of the first contact hole and the second contact hole are formed by etching, the first contact hole penetrates through the interlayer film and is over-etched to a required depth, a protective epoxy film with partial thickness is reserved at the opening of the second contact hole, and P + implantation is simultaneously carried out to form a first P + contact region and a second P + contact region, because the P + implantation of the second P + contact region needs to penetrate through the reserved guard ring oxide film, the peak position of the P + implantation of the second P + contact region is generally positioned in the guard ring oxide film, so that the concentration of the second P + contact region implanted into the guard ring can be reduced, the concentration of the second P + contact region can be further reduced on the basis of reducing the junction depth of the second P + contact region, and the capability of the second P + contact region for collecting holes can be weakened, increasing the softness factor of the reverse recovery of the body diode of the device.
The invention can also be realized by injecting P + of the P + contact area in two times, after the first full P + injection is carried out to form the doping concentration required by the second P + contact area, the second contact hole is protected by adopting a photoetching process, and the concentration required by forming the first P + contact area by injecting P + is increased once at the bottom of each first contact hole, so that the softness factor of the reverse recovery of the body diode of the device can be further increased, and the avalanche tolerance of the device is enhanced.
The invention can also increase the quantity of holes needed to be collected in the reverse recovery process by covering more P-type columns with the P-type ring, thereby increasing the softness factor of the reverse recovery of the body diode of the device.
The invention can also increase the distance of the cavity collected by the P-type ring to the second P + contact region and increase the reverse recovery softness factor of the body diode of the device by making the process of the P-type ring independent of the process of the P-type well and making the junction depth of the P-type ring greater than that of the P-type well.
The method not only can realize the beneficial effects of increasing the softness factor of the reverse recovery of the body diode of the device and simultaneously enhancing the avalanche tolerance of the device, but also can realize the first comprehensive N-type ion implantation in the charge flowing region by taking the protective ring oxide film as the self-alignment condition to form the JFET region by utilizing the special arrangement of the protective ring oxide film, namely the formation of the JFET region in the method does not need to be defined by adopting a photoetching process independently, namely the method can reduce the photoetching corresponding to the JFET region.
Meanwhile, in the first N-type ion implantation (JFET implantation) corresponding to the JFET area, because the protection ring oxide film can completely cover the transition area and completely or mostly cover the terminal area, the ions of the first N-type ion implantation cannot be implanted into the transition area and the internal area of the terminal area, and if the N-type ions of the JFET implantation are implanted into the internal area of the terminal area, the breakdown voltage (BVds) of the device can be obviously reduced; and if the JFET-injected N-type ions are injected into the transition region, the current impact resistance of the device, namely EAS (electronic article Surveillance) is reduced, so that the performance and the reliability of the device can be maintained under the condition of reducing the photoetching corresponding to the JFET region.
In addition, in the fourth step of the method, after the polysilicon gate is formed, comprehensive second N-type ion implantation is carried out by taking the polysilicon gate and the protection ring oxide film as self-alignment conditions, namely, source regions are respectively formed on two sides of the polysilicon gate in the charge flowing region by source implantation, namely, the method can be realized by self-alignment when the source regions are formed, and a photoetching process is not required to be independently adopted for definition, so that photoetching for defining the source regions once is saved.
Meanwhile, the method can form a terminal first N-type injection region and a terminal second N-type injection region in or outside the terminal region outside the protective epoxy film covered region, and the terminal first N-type injection region and the terminal second N-type injection region can be cut-off regions, so that the surface inversion of the terminal region can be prevented, and the stability of the breakdown characteristic of the device can be better improved.
Meanwhile, ions implanted by the source are also not implanted into the transition region and the inner region of the terminal region, so that the performance and reliability of the device can be maintained.
Therefore, the method can realize the overall injection of the JFET area and the self-aligned injection of the JFET area and the source area by specially arranging the protective ring oxide film, namely the method can reduce two photoetching processes, maintain the performance and the reliability of the device, reduce the manufacturing cost and shorten the production period.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a top view of an existing superjunction device;
fig. 2 is a schematic cross-sectional view of a prior art first superjunction device;
fig. 3 is a schematic cross-sectional view of a second prior art superjunction device;
fig. 4 is a schematic cross-sectional view of a super junction device of a first embodiment of the present invention;
fig. 5 is a schematic cross-sectional view of a superjunction device of a second embodiment of the present invention;
fig. 6 is a schematic cross-sectional view of a superjunction device of a third embodiment of the present invention;
fig. 7 is a schematic cross-sectional view of a superjunction device according to a fourth embodiment of the present invention;
fig. 8A to 8H are schematic cross-sectional views of devices at steps of a method of manufacturing a super junction device according to the first embodiment of the present invention;
fig. 9A-9D are schematic cross-sectional views of a superjunction device at steps of a method of manufacturing the device according to a second embodiment of the present invention; .
Detailed Description
As shown in fig. 1, is a top view of an existing superjunction device; the general super junction device structure comprises a charge flowing region, a terminal region which is transversely subjected to reverse bias voltage and a transition region which is arranged between the charge flowing region and the terminal region, wherein the terminal region surrounds the periphery of the charge flowing region, and in the figure 1, a region 1 represents the charge flowing region, a region 2 represents the transition region, and a region 3 represents the terminal region.
Region 1 includes a super junction structure composed of alternately arranged P-type columns 22 and N-type columns 23, and both P-type columns 22 and N-type columns 23 in fig. 1 have a stripe structure. N-type column 23 provides a conduction path when the superjunction device is turned on, and P-type column 22 and N-type column 23 are mutually depleted when the superjunction device is reversely biased to commonly bear a reverse bias.
And the area 2 and the area 3 are positioned at the terminal of the super junction device and are used as a terminal protection structure for representing the super junction device together. The regions 2 and 3 provide no current when the device is turned on, and in a reverse bias state are used to bear a voltage from the surface of the region 1 peripheral cell to the substrate at the outermost end surface of the device, which is a lateral voltage, and a voltage from the surface of the region 1 peripheral cell to the substrate, which is a vertical voltage.
There is at least one P-type ring 25 in region 2, fig. 1 is a P-type ring 25, and the P-type ring 25 is typically connected to the back gate P-type well in region 1; in the prior art, a field plate dielectric film with a certain inclination angle is generally arranged in the region 2, a field plate 24 for slowing down the abrupt change of a surface electric field is also arranged in the region 2, and the field plate 24 is a polycrystalline field plate or a metal field plate and a P-type column 22; the metal field plate may not be provided in region 2.
Region 3 includes a super junction structure composed of alternately arranged P-type columns 22 and N-type columns 23, and in fig. 1, P-type columns 22 and N-type columns 23 in region 3 are respectively formed by extending and expanding P-type columns 22 and N-type columns 23 in region 1, and the alternately arranged directions are the same. In other configurations, the 3-zone P-type pillars 22 and N-type pillars 23 can also be in an end-to-end ring-type configuration.
A metal field plate is arranged in the region 3, and the metal field plate is not arranged in the region 3; there may or may not be a P-type ring 25 in the 3 region, where the P-type ring is not connected (floating) to the P-type back gate connection of the charge flow region in the presence of the P-type ring 25; and a terminal stop ring 21 is arranged at the outermost end of the 3 region, and the terminal stop ring 21 is composed of an N + injection region or an N + injection region and a medium formed on the N + injection region or the medium and a metal.
As shown in fig. 2, is a schematic cross-sectional view of a conventional superjunction device; the middle region of the existing super junction device is a charge flowing region, namely a region 1, a terminal region, namely a region 3, surrounds the periphery of the charge flowing region, and a transition region, namely a region 2, is positioned between the charge flowing region and the terminal region; the existing super junction device includes:
the N-type epitaxial layer 2 is subjected to dry etching to form a plurality of grooves 41,42 and 43; the trenches 41,42,43 are filled with a P-type epitaxial layer and form P- type columns 51,52,53, an N-type column is formed by the N-type epitaxial layer 2 between the P- type columns 51,52,53, and a super junction structure is formed by a plurality of alternately arranged N-type columns and P- type columns 51,52, 53.
The N-type epitaxial layer 2 is formed on the surface of the semiconductor substrate 1, and the semiconductor substrate 1 adopts an N-type heavily doped structure.
A P-type well 6 is formed in the charge flow region. The transition region is formed with a P-type ring 6a in selected regions, typically, the P-type ring 6a is also comprised of a P-type well 6, both formed in the same process and at the same time.
A termination dielectric film, generally a termination oxide film 7, is formed on the surface of the N-type epitaxial layer 2 in the termination region, and the transition region is usually exposed by the termination oxide film 7 in the prior art, so that the contact hole at the top of the P-type ring 6a, i.e., the P-type ring 6a, in the transition region, i.e., the second contact hole 12b, and the contact hole in the charge flowing region, i.e., the first contact hole 12a, in the subsequent contact hole process can be formed by the same process.
A planar gate structure formed by superposing a gate oxide film 8 and a polysilicon gate 9 is formed on the surface of the super junction structure of the charge flowing region, the forming region of the polysilicon gate 9 is defined by a photoetching process, each polysilicon gate 9 covers the corresponding P-type well 6, and the surface of the P-type well 6 covered by the polysilicon gate 9 is used for forming a channel.
In the super junction device, an N-type column and an N-type epitaxial layer 2 at the bottom of the super junction structure are generally used as a drift region of the device, and a JFET region is formed on the surface of the N-type column, namely the drift region, between the P-type wells 6 in a charge flowing region by adopting photoetching and injection processes and used for reducing parasitic resistance at the position so as to reduce the on-resistance of the whole device.
Active regions 10 are respectively formed on two sides of the polysilicon gate 9 in the charge flow region, one side of each source region 10 in the existing device is self-aligned to the corresponding polysilicon gate 9, but the source regions 10 between the side faces of two adjacent polysilicon gates 9 need to have an interval, so that the first contact hole 12a and the P-type well 6 at the bottom can be in good contact, and therefore the source regions 10 in the existing process need to be defined by adopting photoetching. Typically, the cut-off region 10 consisting of an N + region located outside the termination region and the source region 10 are formed simultaneously using the same process.
An interlayer film 11 is formed on the surface of the super junction structure; contact holes are formed in the interlayer film 11 through the interlayer film 11, the contact holes including first and second contact holes 12a and 12b and a contact hole at the top of the polysilicon gate 9, the contact holes being defined by a photolithography process.
The grid electrode and the source electrode are formed by patterning the front metal layer 14, and the forming areas of the grid electrode and the source electrode are defined through a photoetching process; each of the source regions 10 and the corresponding P-type well 6 in the charge flow region are connected to the source through the same top contact hole first contact hole 12a, the P-type ring 6a in the transition region is also connected to the source through the top contact hole second contact hole 12b, and the polysilicon gate 9 is connected to the gate through the top contact hole.
A first P + contact region 131a is formed at the bottom of each of the first contact holes 12a, and the contact resistance between the first contact hole 12a and the P-type well 6 is reduced by the first P + contact region 131 a. A second P + contact region 132a is formed at the bottom of the second contact hole 12b, and the contact resistance between the second contact hole 12b and the P-type ring 6a is reduced by the second P + contact region 132 a.
A back metal layer 15 is formed on the back surface of the thinned semiconductor substrate 1, and a drain is led out from the back metal layer 15.
In the structure shown in fig. 2, the first contact hole 12a and the second contact hole 12b are both over-etched with respect to the N-type epitaxial layer 2, typically a silicon epitaxial layer. Fig. 3 is a schematic cross-sectional view of a second prior art superjunction device; the first contact hole is individually designated 12c and the second contact hole is individually designated 12d, and both the first contact hole 12a and the second contact hole 12b are over-etched with respect to the N-type epitaxial layer 2. The first P + contact area at the bottom of the first contact hole 12a is separately labeled 131b and the second P + contact area at the bottom of the second contact hole 12b is separately labeled 132b, and it can be seen that the junction depth of the first P + contact area 131b and the second P + contact area 132b is deeper than the first P + contact area 131a and the second P + contact area 132a shown in fig. 2. The deeper first P + contact region 131b, while being advantageous in reducing the contact resistance of the P-well 6 and achieving enhanced avalanche resistance of the device, the second P + contact region 132b, which is formed by the same process as the first P + contact region 131b, may reduce the reverse recovery characteristics of the device.
The first embodiment of the invention is a super junction device:
fig. 4 is a schematic cross-sectional view of a super junction device according to a first embodiment of the present invention; the middle region of the super junction device in the first embodiment of the present invention is a charge flowing region, i.e. region 1, a terminal region, i.e. region 3, surrounds the periphery of the charge flowing region, and a transition region, i.e. region 2, is located between the charge flowing region and the terminal region; the structure of the top view of the superjunction device can also be referred to as shown in fig. 1. A super junction device of a first embodiment of the present invention includes:
the N-type epitaxial layer 2 is subjected to dry etching to form a plurality of grooves 41,42 and 43; the trenches 41,42,43 are filled with a P-type epitaxial layer and form P- type columns 51,52,53, an N-type column is formed by the N-type epitaxial layer 2 between the P- type columns 51,52,53, and a super junction structure is formed by a plurality of alternately arranged N-type columns and P- type columns 51,52, 53.
In the super junction device according to the first embodiment of the present invention, in order to clearly distinguish the trenches and the P-type columns in the region 1, the region 2, and the region 3, the trenches in each region are separately marked, specifically: trench 41 is a trench formed in region 1, trench 42 is a trench formed in region 2, and trench 43 is a trench formed in region 3; p-type column 51 is a P-type column formed in region 1, P-type column 52 is a P-type column formed in region 1, and P-type column 53 is a P-type column formed in region 1. The width may be set to be different between different trenches, where Wp1 in fig. 4 indicates the width of the trench 41, and also the width of the subsequent P-type pillar 51; wp2 indicates the width of trench 42, which is also the width of subsequent P-type pillar 52, Wp3 indicates the width of trench 43, which is also the width of subsequent P-type pillar 53; wn1 denotes the width of the N-type pillars in the region 1, Wn2 denotes the width of the N-type pillars in the region 2, and Wn3 denotes the width of the N-type pillars in the region 3.
In the super junction device according to the first embodiment of the present invention, the super junction device is described in detail by taking the super junction MOSFET as an example: the N-type epitaxial layer 2 is formed on the surface of the semiconductor substrate 1, and the semiconductor substrate 1 adopts an N-type heavily doped structure; preferably, the N-type epitaxial layer 2 is a silicon epitaxial layer, and the semiconductor substrate 1 is a silicon substrate, which is also known as a silicon wafer or a silicon wafer. The drain region of the super junction MOSFET is usually formed on the back surface of the semiconductor substrate 1, so the heavily doped semiconductor substrate 1 is directly adopted, and in the method of the first embodiment of the invention, the resistivity of the semiconductor substrate 1 is 0.001-0.003 ohm cm; the resistance of the N-type epitaxial layer 2 is 1-2 ohm.cm, the thickness is 30-70 micrometers, and preferably 40-60 micrometers; P-N column region is super junction structure region: when the source-drain breakdown voltage BVds of the corresponding device is 600V-700V, the height of the super junction structure is 35 micrometers-45 micrometers, namely the depth of the trenches 41,42 and 43 is 35 micrometers-45 micrometers. In the super junction device according to the first embodiment of the present invention, to ensure that a buffer layer with a certain thickness, for example, more than 5 μm, is provided between the trench trenches 41,42,43 and the high-concentration semiconductor substrate 1 to maintain the device with a good current surge resistance, the buffer layer is generally directly formed by the N-type epitaxial layer 2 located at the bottom of the trench trenches 41,42, 43.
Forming a P-type well 6 in a selected region of the charge flow region, the selected region forming the P-type well 6 being defined by lithography; a P-type ring 6a is formed in a selected region of the transition zone; in the first embodiment of the present invention, the P-type ring 6a is formed simultaneously by the same process as the P-type well 6, i.e., the P-type ring 6a is formed by a P-type well. One P-type well 6 is formed at the top of each P-type pillar 51 in the charge flowing region and each P-type well 6 extends to the surface of the corresponding N-type pillar on both sides of the P-type pillar 51.
A first oxide film 7 is formed on the surface of the N-type epitaxial layer 2 on which the P-type well 6 is formed, the first oxide film 7 is formed by performing photolithography etching on the first oxide film 7, and the protective epoxy film 7 exposes the charge flowing region and covers the transition region completely, which can be specifically shown by a dashed box T2 in fig. 4; the guard ring oxide film 7 also extends to the surface of the termination region and exposes the termination region entirely or only the outermost peripheral portion of the termination region, and the protective epoxy film 7 is surrounded on the peripheral side of the charge flow region.
Forming a JFET region in the charge flow region, the JFET region being formed by a first N-type ion implantation of the whole surface with the guard ring oxide film 7 as a self-aligned condition; the first N-type ion implantation simultaneously forms a terminal first N-type implanted region in or outside the terminal region outside the region covered by the protective epoxy film 7.
A planar gate structure formed by superposing a gate oxide film 8 and a polysilicon gate 9 is formed on the surface of the super junction structure of the charge flowing region, the forming region of the polysilicon gate 9 is defined by a photoetching process, each polysilicon gate 9 covers the corresponding P-type well 6, and the surface of the P-type well 6 covered by the polysilicon gate 9 is used for forming a channel.
An active region 10 is formed on each of both sides of the polysilicon gate 9 in the charge flow region, and the active region 10 is formed by a second N-type ion implantation on the whole with the polysilicon gate 9 and the guard ring oxide film 7 as a self-aligned condition, and the second N-type ion implantation simultaneously forms a second N-type implantation terminal region 10 in or outside the terminal region outside the region covered by the guard ring oxide film 7. A terminal second N-type implant region is also indicated at 10 in fig. 4 and is formed simultaneously with the source region 10 using the same process and is N + doped. The termination second N-type implanted region 10 can be used to prevent surface inversion of the termination region, which better improves the stability of the breakdown characteristics of the device. The terminal second N-type implant 10 overlaps the terminal first N-type implant and serves as a stop region, also referred to as terminal stop ring 21 in fig. 1.
An interlayer film 11 is formed on the front surface of the N-type epitaxial layer 2, and the interlayer film 11 covers the surfaces of the source region 10 and the polysilicon gate 9 of the charge flow region and the surfaces of the protective epoxy film 7 of the transition region and the termination region.
A front metal layer 14 is formed on the surface of the interlayer film 11; the grid electrode and the source electrode are formed by patterning the front metal layer 14; each of the source regions 10 and the corresponding P-type well 6 in the charge flow region are connected to the source through a first contact hole 121a having the same top, the P-type ring 6a in the transition region is connected to the source through a second contact hole 121b having the same top, and the polysilicon gate 9 is connected to the gate through a third contact hole having the same top.
Each of the first contact holes 121a is contacted to the P-type well 6 through the interlayer film 11 and the source region 10 at the bottom, each of the second contact holes 121b is contacted to the P-type well 6 at the bottom through the stack of the interlayer film 11 and the guard ring oxide film 7, a first P + contact region 131c is formed at the bottom of each of the first contact holes 121a, a second P + contact region 132c is formed at the bottom of the second contact hole 121b, and the junction depth of the second P + contact region 132c is made shallower than that of the first P + contact region 131c by utilizing the characteristic that each of the second contact holes 121b needs to pass through the protective epoxy film 7 so that the bottom of each of the second contact holes 121b penetrates into the N-type epitaxial layer 2 than the second contact hole 121b penetrates into the N-type epitaxial layer 2, thereby increasing the distance that the hole collected by the P-type well 6a reaches the second P + contact region 132c, increasing the softness factor of the reverse recovery of the body diode of the device.
The doping concentrations of the first P + contact region 131c and the second P + contact region 132c are the same.
In addition, the bottom of the first contact hole 121a in the charge flowing region passes through the source region 10, and the influence of the fully implanted source region 10 on the contact of the first contact hole 121a and the P-type well 6 at the bottom can be eliminated. In the transition region, the interlayer film 11 and the guard ring oxide film 7 need to be sequentially etched to form an opening of the second contact hole 121b, and an over-etching amount of the N-type epitaxial layer 2 at the bottom of the second contact hole 121b in the transition region is greater than or equal to 0 angstroms, that is, the second contact hole 121b only needs to expose the top surface of the P-type ring 6a at the bottom, and the touch pad 121a needs to pass through the source region 10 at the bottom. Preferably, the bottom of each second contact hole 121b penetrates into the N-type epitaxial layer 2 to a depth of 0 to 500 angstroms, and the depth of the first contact hole 121a penetrates into the N-type epitaxial layer 2 to a depth of more than 2000 angstroms.
Preferably, a polysilicon bus line 9a is formed on the top of the protective epoxy film 7 in the transition region, the polysilicon bus line 9a and the polysilicon gate 9 are simultaneously formed by the same process, each polysilicon gate 9 is in contact connection with the polysilicon bus line 9a, and the polysilicon bus line 9a is connected to the gate through a contact hole 121c on the top. In the first embodiment superjunction device of the present invention, each of the polysilicon gates 9 is not directly connected to the gate through a contact hole, but is connected to the gate through the polysilicon bus 9a, connected to a contact hole 121c through the polysilicon bus 9a, and by connecting each of the polysilicon gates 9 to the polysilicon bus 9 a. In this way, the contact hole connected with the gate is not directly arranged at the top of the polysilicon gate 9, but arranged at the top of the polysilicon bus 9a, so that the reliability of the device is not affected by the contact hole process.
A back metal layer 15 is formed on the back of the thinned semiconductor substrate 1, and a drain is led out of the back metal layer 15.
As can be seen from the above, in the device according to the first embodiment of the present invention, by designing the structure of the guard ring oxide film 7, so that the protective epoxy film 7 completely covers the transition region, and utilizing the characteristic that the second contact hole 121b penetrates through the protective epoxy film 7 more than the first contact hole 121a, the junction depth of the second P + contact region 132c is shallower than the junction depth of the first P + contact region 131c, so as to increase the distance from the hole collected by the P-type ring 6a to the second P + contact region 132c, and increase the softness factor of the reverse recovery of the body diode of the device.
In addition, the protective epoxy film 7 is designed to realize self-aligned implantation of the JFET area and the source area, so that two photoetching processes can be reduced.
The second embodiment of the invention is a super junction device:
fig. 5 is a schematic cross-sectional view of a superjunction device according to a second embodiment of the present invention; the second embodiment superjunction device of the present invention is different from the first embodiment superjunction device of the present invention in that: in the superjunction device according to the second embodiment of the present invention, the width of the second contact hole 121b is smaller than that of the first contact hole 121a, so that the width of the second P + contact region 132d is reduced, and thus the distance from the hole collected by the P-type ring 6a to the second P + contact region 132d is increased in the lateral direction, and the softness factor of the body diode of the device in the reverse recovery is increased. The first P + contact region is designated solely by reference numeral 131d and the second P + contact region is designated solely by reference numeral 132d in fig. 5.
The third embodiment of the invention is a super junction device:
as shown in fig. 6, is a schematic cross-sectional view of a super junction device according to a third embodiment of the present invention; the third embodiment superjunction device of the present invention is different from the second embodiment superjunction device of the present invention in that:
in the third embodiment of the present invention, the coverage area of the P-type ring 6a is enlarged, in fig. 5, the P-type ring 6a covers two P-type pillars 52, and in fig. 6, the P-type ring 6a covers 4P-type pillars 52. The number of the P-type columns 52 covered by the P-type ring 6a is usually set to be more than two, and after the number of the P-type columns 52 covered by the P-type ring 6a is increased, the number of holes required to be collected in the reverse recovery process can be increased, so that the softness factor of the reverse recovery of the body diode of the device is increased.
The fourth embodiment of the invention is a super junction device:
fig. 7 is a schematic cross-sectional view of a superjunction device according to a fourth embodiment of the present invention; the fourth embodiment superjunction device of the present invention is different from the first embodiment superjunction device of the present invention in that: in fig. 7, the first P + contact region is separately denoted by reference numeral 131f and the second P + contact region is separately denoted by reference numeral 132f, in the super junction device according to the fourth embodiment of the present invention, the doping concentration of the second P + contact region 132f is less than that of the first P + contact region 131f, so that the ability of the second P + contact region 132f to collect holes is reduced, and the softness factor of the reverse recovery of the body diode of the device is increased. Preferably, the peak value of the doping concentration of the second P + contact region 132f is 1/2-1/10 of the peak value of the doping concentration of the first P + contact region 131 f.
In the superjunction device according to the fourth embodiment of the present invention, after the opening of the first contact hole 121a is etched to a depth required to penetrate through the source region 10, the protective epoxy film 7 is still remained at the bottom of the second contact hole 121b, the first P + contact region 131c and the second P + contact region 132c are simultaneously formed by using the same P + implantation process, the doping concentration of the second P + contact region 132c is made smaller than that of the first P + contact region 131c by the characteristic that the P + implantation of the second P + contact region 132c penetrates through the remained protective ring oxide film 7, and then the remained protective epoxy film 7 is removed.
In other embodiments, the opening of the first contact hole 121a and the opening of the second contact hole 121b are etched simultaneously by the same process, after the doping concentration required for forming the second P + contact region 132c is performed by the global P + implantation, the second contact hole 121b is protected by the photolithography process, and the concentration required for forming the first P + contact region 131c is added to the bottom of each first contact hole 121a by one P + implantation.
The super junction device of the fifth embodiment of the present invention:
the fifth embodiment superjunction device of the present invention is different from the first embodiment superjunction device of the present invention in that: in the super junction device according to the fifth embodiment of the present invention, the process of the P-type ring 6a is independent of the process of the P-type well 6, and the junction depth of the P-type ring 6a is made larger than the junction depth of the P-type well 6, so as to increase the distance from the hole collected by the P-type ring 6a to the second P + contact region 132c, and increase the softness factor of the body diode of the device for reverse recovery.
The manufacturing method of the super junction device of the first embodiment of the invention comprises the following steps:
the method for manufacturing a superjunction device according to the first embodiment of the present invention is described by taking as an example the case of manufacturing a superjunction device according to the first embodiment of the present invention as shown in fig. 4, and is a schematic cross-sectional view of the device in each step of the method for manufacturing a superjunction device according to the first embodiment of the present invention, as shown in fig. 8A to 8H; in the manufacturing method of the super junction device in the embodiment of the invention, the middle area of the super junction device is a charge flowing area, namely area 1, a terminal area, namely area 3, surrounds the periphery of the charge flowing area, and a transition area, namely area 2, is positioned between the charge flowing area and the terminal area; the structure of the top view of the superjunction device can also be referred to as shown in fig. 1. The method of the first embodiment of the invention comprises the following steps:
step one, as shown in fig. 8A, providing an N-type epitaxial layer 2, performing a first photolithography process to define formation regions of trenches 41,42,43, and then performing dry etching on the N-type epitaxial layer 2 to form a plurality of trenches 41,42, 43.
P-type epitaxial layers are filled in the trenches 41,42 and 43 to form P- type columns 51,52 and 53, an N-type column is formed by the N-type epitaxial layer 2 between the P- type columns 51,52 and 53, and a super junction structure is formed by a plurality of alternately arranged N-type columns and P- type columns 51,52 and 53.
In the method according to the first embodiment of the present invention, in order to clearly distinguish the trenches and the P-type pillars in the region 1, the region 2, and the region 3, the trenches in the respective regions are separately marked, specifically: trench 41 is a trench formed in region 1, trench 42 is a trench formed in region 2, and trench 43 is a trench formed in region 3; p-type column 51 is a P-type column formed in region 1, P-type column 52 is a P-type column formed in region 1, and P-type column 53 is a P-type column formed in region 1. The width may be set to be different between different trenches, where Wp1 in fig. 8A indicates the width of the trench 41, and also the width of the subsequent P-type pillar 51; wp2 indicates the width of trench 42, which is also the width of subsequent P-type pillar 52, Wp3 indicates the width of trench 43, which is also the width of subsequent P-type pillar 53; wn1 denotes the width of the N-type pillars in the region 1, Wn2 denotes the width of the N-type pillars in the region 2, and Wn3 denotes the width of the N-type pillars in the region 3.
In the method of the first embodiment of the present invention, the manufactured super junction device is a super junction MOSFET as an example for detailed description: the N-type epitaxial layer 2 is formed on the surface of the semiconductor substrate 1, and the semiconductor substrate 1 adopts an N-type heavily doped structure; preferably, the N-type epitaxial layer 2 is a silicon epitaxial layer, and the semiconductor substrate 1 is a silicon substrate, which is also known as a silicon wafer or a silicon wafer. The drain region of the super junction MOSFET is usually formed on the back surface of the semiconductor substrate 1, so the heavily doped semiconductor substrate 1 is directly adopted, and in the method of the first embodiment of the invention, the resistivity of the semiconductor substrate 1 is 0.001-0.003 ohm cm; the resistance of the N-type epitaxial layer 2 is 1-2 ohm.cm, the thickness is 30-70 micrometers, and preferably 40-60 micrometers; P-N column region is super junction structure region: when the source-drain breakdown voltage BVds of the corresponding device is 600V-700V, the height of the super junction structure is 35 micrometers-45 micrometers, namely the depth of the trenches 41,42 and 43 is 35 micrometers-45 micrometers. In the first embodiment of the method of the present invention, to ensure that a buffer layer with a certain thickness, for example, more than 5 μm, is provided between the trench trenches 41,42,43 and the high-concentration semiconductor substrate 1 to maintain the device with a good current surge resistance, the buffer layer is generally directly formed by the N-type epitaxial layer 2 located at the bottom of the trench trenches 41,42, 43.
In the method according to the first embodiment of the present invention, before the first photolithography process, a step of forming a first dielectric film 3 on the surface of the N-type epitaxial layer 2 is further included, and after the first photolithography process, dry etching is sequentially performed on the first dielectric film 3 and the N-type epitaxial layer 2 to form a plurality of trenches 41,42, 43.
As shown in fig. 8B, after the P-type epitaxial layers are filled in the trenches 41,42,43, a Chemical Mechanical Polishing (CMP) process is performed to remove the P-type epitaxial layer on the surface of the N-type epitaxial layer 2, so that the P-type epitaxial layer is only filled in the corresponding trenches 41,42,43 and constitutes the P- type pillars 51,52, 53; the first dielectric film 3 is removed or partially remained after the chemical mechanical polishing process is completed.
In the method according to the first embodiment of the present invention, the composition materials of the first dielectric film 3 and the corresponding process method can be selected as follows:
the first option is: the first dielectric film 3 is a single oxide film, for example, an oxide film with a thickness exceeding 1 micron, the oxide film can be used as a hard mask during trench etching, an oxide film with a certain thickness is left after trench formation, for example, an oxide film with a thickness of 0.1 micron to 0.2 micron, and during the process of performing epitaxial filling and CMP, the oxide film is used as a protective layer of the N-type epitaxial layer 2 during CMP, so that silicon at the position cannot form defects in the CMP process, and leakage or quality problems are caused.
The second option is: the first dielectric film 3 is composed of a layer of oxide film with the thickness of 0.1-0.15 micron, a layer of SIN film with the thickness of 0.1-0.2 micron and an oxide film with the thickness of the top layer larger than 1 micron-the multilayer film structure is obtained; this allows for better control of uniformity during fabrication: for example, after the trench etching is completed, at least a part of the SIN film is remained on the oxide film thereunder, and before the epitaxial growth, the SIN film is removed, so that the uniformity of the oxide film before the epitaxial growth is good, and the uniformity of CMP for the epitaxy can be improved. A further improvement of the above-described multilayer film structure is that the first oxide film is formed by thermal oxidation, which further improves uniformity.
Step two, as shown in fig. 8C, a second photolithography process is performed to define a formation region of the P-type well 6 in the charge flowing region and the transition region, and then P-type ion implantation is performed to form the P-type well 6; in the method according to the first embodiment of the present invention, the P-type ring 6a is formed in the transition region by the same process as the P-type well 6, that is, the P-type ring 6a is also a P-type well.
One P-type well 6 is formed at the top of each P-type pillar 51 in the charge flowing region and each P-type well 6 extends to the surface of the corresponding N-type pillar on both sides of the P-type pillar 51. In the method of the first embodiment of the present invention, one P-well 6 is formed in the region 2, and the P-well 6 covers 2 the P-type pillars 52.
And after the P-type ion implantation of the P-type well 6 is finished, carrying out an annealing process on the P-type well 6, wherein the annealing process has the temperature of more than 1000 ℃ and the time of more than 30 minutes.
In the method of the first embodiment of the present invention, the process conditions of the P-type well 6 need to meet the requirement of the threshold voltage of the device, and for the device with the threshold voltage requirement of 2 v to 4 v, the process conditions of B30-100 KEV and 3-10E13/cm2 may be adopted, that is, the impurity is implanted as boron (B), the implantation energy is 30KEV to 100KEV, and the implantation dose is 3E13cm-2～10E13cm-2(ii) a Meanwhile, when the breakdown voltage of the device occurs, source-drain Punch-through (Punch through) does not occur at the channel, otherwise, the device has large leakage and low breakdown voltage.
Step three, as shown in fig. 8D, growing a first oxide film 7 on the surface of the N-type epitaxial layer 2 on which the P-type well 6 is formed, performing a third photolithography process to define an etching region of the first oxide film 7, then etching the first oxide film 7 to form a guard ring oxide film 7, exposing the charge flow region and covering all the transition region by the guard ring oxide film 7, extending the guard ring oxide film 7 to the surface of the termination region and exposing all or only the outermost periphery of the termination region, and surrounding the guard ring oxide film 7 around the periphery of the charge flow region. The structure of the guard ring oxide layer 7 surrounding the charge flow region can be understood with reference to fig. 1.
Preferably, the first oxide film 7 is formed by a thermal oxidation process at a temperature higher than 800 ℃, so that dangling bonds and unstable interface states can be reduced at the Si-SiO2 interface, the voltage-withstanding capability of the termination region can be further improved, and the uniformity of the breakdown voltage of the device can be improved. The thickness of the first oxide film 7 needs to be set according to the magnitude of the device BVds, i.e., the source-drain breakdown voltage, and generally, the larger the BVds is, the thicker the thickness of the first oxide film 7 needs to be, and generally, the thickness of the first oxide film 7 needed for a device with 600V or more exceeds 0.6 μm.
And carrying out overall first N-type ion implantation by taking the protective epoxy film 7 as a self-alignment condition to form a JFET (junction field effect transistor) region in the charge flowing region, and simultaneously forming a terminal first N-type implantation region in or outside the terminal region outside the coverage region of the protective epoxy film 7. In the method of the first embodiment of the present invention, since the transition region and the termination region are protected by the guard ring oxide film 7, JFET implantation can be performed without photolithography, which saves the cost of the photolithography process, because if a JFET is implanted into the termination region, BVds of the device is significantly reduced, and if a JFET is implanted into the transition region, the current impact resistance of the device is reduced.
In the method according to the first embodiment of the present invention, the process condition of the first N-type ion implantation corresponding to the JFET region is phosphorus (phos),30-100Kev 1-4E13/cm2, that is: the implantation impurity is phosphorus, the implantation energy is 30 Kev-100 Kev, and the implantation dosage is 1E13cm-2～4E13cm-2(ii) a Or, in the third step, the first N-type ion implantation corresponding to the JFET region is formed by a combination of two implantations with implantation energies of 30Kev to 60Kev and 1Mev to 1.5Mev, and the high-energy implantation can further reduce the specific on-resistance of the device, improve the charge balance around the P-type well 6, increase the Bvds of the device, and perform experimental verification to obtain: for a 600V device, Bvds can be improved by 10V-20V.
Step four, as shown in fig. 8E, sequentially forming a gate oxide film 8 and a first layer of N-type heavily doped polysilicon, performing a fourth photolithography process to define a formation region of a polysilicon gate 9, then etching the first layer of polysilicon to form polysilicon gates 9, wherein each polysilicon gate 9 is a planar gate structure, each polysilicon gate 9 covers the corresponding P-type well 6, and the surface of the P-type well 6 covered by the polysilicon gate 9 is used for forming a channel.
In the method according to the first embodiment of the present invention, the gate oxide film 8 is formed by thermal oxidation, and then the first layer of polysilicon is formed by a deposition process. The gate oxide film 8 is a thermal oxide film, and the thickness of the gate oxide film 8 of a MOSFET of 500V to 700V is generally set to
Figure BDA0001225625950000191
The first layer of polysilicon has a thickness of
Figure BDA0001225625950000192
The fourth photolithography process simultaneously defines a formation region of a polysilicon bus 9a (bus), and then the polysilicon bus 9a is simultaneously etched when the first layer of polysilicon is etched, the polysilicon bus 9a is located on the top of the protective epoxy film 7 in the transition region, and each polysilicon gate 9 is in contact connection with the polysilicon bus 9 a.
The method can also comprise the following steps: and defining a forming area of a polysilicon field plate by the fourth photoetching process, and then simultaneously forming the polysilicon field plate when etching the first layer of polysilicon, wherein the polysilicon field plate is positioned at the top of the protection ring oxide film 7 and is isolated from the polysilicon gate 9.
As shown in fig. 8F, a second N-type ion implantation is performed on the polysilicon gate 9 and the guard ring oxide film 7 as a self-aligned condition to form source regions 10 on both sides of the polysilicon gate 9 in the charge flowing region, and a terminal second N-type implantation region 10 is formed in or outside the terminal region outside the region covered by the protective epoxy film 7, and the terminal second N-type implantation region is also denoted by reference numeral 10 in fig. 8, and the source regions 10 are formed simultaneously by the same process. The termination second N-type implanted region 10 can be used to prevent surface inversion of the termination region, which better improves the stability of the breakdown characteristics of the device. The termination second N-type implant region 10 can also be formed in the outermost peripheral termination region of the device, also serving as a termination region.
Preferably, the implantation impurities of the second N-type ion implantation corresponding to the source region 10 are arsenic, phosphorus, or a combination of arsenic and phosphorus, and the process conditions of the second N-type ion implantation including arsenic implantation during arsenic implantation are as follows: the implantation energy is 30 Kev-100 Kev, and the implantation dosage is 1E15cm-2～5E15cm-2。
Step five, as shown in fig. 8G, depositing an interlayer film 11, performing a fifth photolithography process to define a formation region of a contact hole, and then performing etching to form an opening of the contact hole.
The contact holes include a first contact hole 121a located at the top of each source region 10 in the charge flow region and the corresponding P-type well 6, a second contact hole 121b located at the top of the P-type ring 6a in the transition region, and a third contact hole 121c located at the top of each polysilicon gate 9, wherein in fig. 8G, the third contact hole 121c is shown as being located at the top of a polysilicon bus 9a, and the third contact hole 121c at the top of the polysilicon gate 9 is not shown in fig. 8G, and each polysilicon gate 9 and the polysilicon bus 9a are also connected to a gate to be formed subsequently through the contact hole 121c at the top; each of the first contact holes 121a is in contact with the P-type well 6 at the bottom through the interlayer film 11 and the source region 10 at the bottom, and each of the second contact holes 121b is in contact with the P-type well 6a at the bottom through the stack of the interlayer film 11 and the guard ring oxide film 7.
Performing a P + implantation to form a first P + contact region 131c at the bottom of each of the first contact holes 121a and a second P + contact region 132c at the bottom of the second contact hole 121 b; by utilizing the characteristic that each second contact hole 121b needs to penetrate through the protective epoxy film 7, so that the depth of the bottom of each second contact hole 121b penetrating into the N-type epitaxial layer 2 is shallower than the depth of the second contact hole 121b penetrating into the N-type epitaxial layer 2, the junction depth of the second P + contact region 132c is shallower than the junction depth of the first P + contact region 131c, thereby increasing the distance from the hole collected by the P-type ring 6a to the second P + contact region 132c, and increasing the softness factor of the reverse recovery of the body diode of the device.
The openings of the contact holes 121a, 121b,121c are filled with metal to form the contact holes 121a, 121b,121 c.
In the method of the first embodiment of the present invention, the interlayer film 11 is a combination of an undoped oxide film and a BPSG film.
Preferably, the P + implantation impurities corresponding to the first P + contact region 131c and the second P + contact region 132c are B, BF2, or a combination of B and BF2, with a typical implantation energy of 40Kev to 80Kev and an implantation dose of 1E15cm-2～3E15cm-2The current impact resistance of the device can be improved by optimizing the implantation conditions, and the energy and dose of the P-type implantation can be reduced for better improving the softness of the reverse recovery process of the body diode, for example, the energy can be BF2, 5-40KEV, 5E14-2E15/cm2, and the dose can be selected so that the energy is mainly selected by considering the capability of an ion implantation device in order to ensure the lowest dose for forming ohmic contact.
Preferably, when the openings of the contact holes 121a, 121b, and 121c are etched, the N-type epitaxial layer 2 at the bottom of the contact hole 121a needs to be over-etched in the charge flowing region, and the over-etching amount needs to satisfy that the bottom of the contact hole 121a passes through the source region 10, the interlayer film 11 and the guard ring oxide film 7 need to be sequentially etched in the transition region to form the opening of the contact hole 121b, and the over-etching amount of the N-type epitaxial layer 2 at the bottom of the contact hole 121b in the transition region is greater than or equal to 0 angstrom, that is, the contact hole 121b only needs to expose the top surface of the P-type well 6 at the bottom, and the touch contact 121a needs to pass through the source region 10 at the bottom. Preferably, the bottom of each second contact hole 121b penetrates into the N-type epitaxial layer 2 to a depth of 0 to 500 angstroms, and the depth of the first contact hole 121a penetrates into the N-type epitaxial layer 2 to a depth of more than 2000 angstroms.
The thickness of the interlayer film 11 is generally set to
Figure BDA0001225625950000211
The contact hole 121b realizes the connection between the source electrode formed by the subsequent front metal layer 14 and the region of the protective ring P-type well 6 in the transition region, so that the device terminal structure with the same size can bear the same voltage as that of the conventional process in the method of the first embodiment of the invention.
Because the contact hole 121a in the charge flowing region penetrates through the N +, i.e. the range of the source region 10, the contact problem between the P-type well 6 and the metal caused by the overall injection of the source region 10 outside the polysilicon gate 9 can be avoided, and the normal electrical characteristics can be ensured.
And sixthly, as shown in fig. 4, depositing front metal to form a front metal layer 14, performing a sixth photolithography process to define forming regions of the gate and the source, and then etching the front metal layer 14 to form the gate and the source. Each of the source regions 10 and the corresponding P-type well 6 in the charge flow region are connected to the source through the first contact hole 121a having the same top, the P-type ring 6a in the transition region is connected to the source through the second contact hole 121b having the same top, each of the polysilicon gates 9 is connected to the gate through a contact hole 121c formed at the top of the polysilicon bus 9a and connected to the gate through a contact hole 9a, and the gate can be directly connected to the gate through a contact hole 121c at the top of each of the polysilicon gates 9.
The front side metal layer 14 can be of a material such as ALSi or AlSiCu, and can have a barrier layer, which can be Ti/TIN or TIN. The total thickness of the front metal layer 14 is generally 4 μm to 6 μm.
And then, thinning the back surface of the semiconductor substrate 1, and depositing a back metal layer 15 on the back surface to form a drain electrode.
Such a super junction MOSFET device is formed.
In the manufacturing process corresponding to the method of the first embodiment of the present invention, the device that can be obtained only by 8 times of photolithography in the prior art is realized by using six times of photolithography including trench photolithography, i.e., first photolithography, P-type well photolithography, i.e., second photolithography, protective epoxy film photolithography, i.e., third photolithography, polycrystalline photolithography, i.e., fourth photolithography, contact hole photolithography, i.e., fifth photolithography, and front metal photolithography, i.e., sixth photolithography, that is, the method of the first embodiment of the present invention saves JFET implantation photolithography and source implantation photolithography. Therefore, the method of the first embodiment of the invention reduces the manufacturing cost, and in order to ensure the production stability in the production, a 0-layer photoetching and/or a mark layer photoetching can be added before the groove photoetching, so as to form an alignment mark and an alignment precision test mark by photoetching and etching; the process for layer 0 may be deposition
Figure BDA0001225625950000212
Then photolithography, etching the oxide film, and then etching silicon
Figure BDA0001225625950000213
Forming a step; in order to better protect the front side of the device and improve the reliability of the device, a passivation layer may be deposited after the front side metal pattern is formed, and then the passivation layer of the metal region to be opened is etched away by the passivation layer lithography and etching. While in other areas the passivation layer is left to protect the device, which may be SIN, SION, SIO2, typically 0.8 μm to 2 μm thick.
The superjunction device shown in fig. 5 according to the second embodiment of the present invention can also be implemented by the above-mentioned method according to the first embodiment of the present invention, and it is only necessary to reduce the width of the second contact hole 121b when performing the photolithography etching of the contact hole in step five, for example, the width of the second contact hole 121b is smaller than the width of the first contact hole 121a, and the width of the second P + contact region 132c is reduced, so that the distance from the hole collected by the P-type ring 6a to the second P + contact region 132c is increased laterally, and the softness factor of the body diode of the device in reverse recovery is increased.
The super junction device shown in fig. 6 according to the third embodiment of the present invention can also be implemented by the above-mentioned method according to the first embodiment of the present invention, and only the area of the P-type pillar 52 covered by the P-type ring 6a needs to be increased when the P-type well 6a is formed by the P-type well 6 process in the second step, generally, the P-type ring 6a covers more than two P-type pillars 52, so as to increase the number of holes that need to be collected in the reverse recovery process, thereby increasing the softness factor of the reverse recovery of the body diode of the device.
The superjunction device shown in fig. 7 according to the fourth embodiment of the present invention can also be implemented by correspondingly modifying the method according to the first embodiment of the present invention, specifically: in the fifth step, the opening of the first contact hole 121a and the opening of the second contact hole 121b are etched simultaneously by the same process, after the doping concentration required for forming the second P + contact region 132c by full P + implantation is performed, the second contact hole 121b is protected by a photolithography process, the concentration required for forming the first P + contact region 131c by one P + implantation is increased at the bottom of each first contact hole 121a, so that the doping concentration of the second P + contact region 132c is smaller than that of the first P + contact region 131c, thereby weakening the hole collection capability of the second P + contact region 132c, and increasing the reverse recovery softness factor of the body diode of the device. Preferably, the peak value of the doping concentration of the second P + contact region 132c is 1/2-1/10 of the peak value of the doping concentration of the first P + contact region 131 c.
The super junction device according to the fifth embodiment of the present invention can also be implemented by correspondingly modifying the method according to the first embodiment of the present invention: in the second step, the P-type ring 6a is formed by adopting a single photoetching and ion implantation process, and the junction depth of the P-type ring 6a is greater than that of the P-type well 6, so that the distance from the hole collected by the P-type ring 6a to the second P + contact region 132c is increased, and the reverse recovery softness factor of the body diode of the device is increased.
The method for manufacturing the super junction device comprises the following steps:
the method for manufacturing a superjunction device according to the second embodiment of the present invention is described by taking as an example the case of manufacturing a superjunction device according to the fourth embodiment of the present invention as shown in fig. 7, and is a schematic cross-sectional view of the device in each step of the method for manufacturing a superjunction device according to the second embodiment of the present invention, as shown in fig. 9A to 8D; the method of the second embodiment of the present invention is formed by improving the method of the first embodiment of the present invention, and mainly improves the step five, and other steps are the same, and please refer to the method of the first embodiment of the present invention for other steps, in the step five of the method of the second embodiment of the present invention:
when etching an opening of a contact hole, first, as shown in fig. 9A, etching the contact hole with a photoresist, completely etching an oxide film, i.e., an interlayer film 11, in a charge flow region, and forming the photoresist on the surface of the interlayer film 11; and the transition region contact hole, i.e. the second contact hole, has a certain thickness of oxide film, which is the remaining protective epoxy film 7, in which case the etching of the oxide film is stopped, and for the sake of clarity and convenience of illustration, an example with specific data is as follows: the thickness of the protective epoxy film 7 is set to 0.8 micron, the interlayer film 11 is set to 1 micron, and then the etching amount of the etching is set to 1.5 micron, the over-etching amount of the interlayer film in the charge flowing region is 0.5 micron, the process can completely meet the requirement of the process window, and at this time, an oxide film of 0.3 micron, namely the reserved guard ring oxide film 7, is still arranged below the contact hole of the transition region.
Then, as shown in fig. 9B, Silicon (SI) etching is performed, that is, the N-type epitaxial layer 2 is etched, in the method according to the second embodiment of the present invention, the N-type epitaxial layer 2 is a silicon epitaxial layer, and for the sake of more clearly and conveniently describing the etching, an example with specific data is as follows: the thickness of the etched SI is 3000 angstroms, and the SI etching rate is set to be 10 times of the oxide film etching rate in the SI etching process (the selection ratio is 10: 1, the process is easy to realize), so in the charge flow region, the SI is etched by the depth of N < + >, namely the source region 1 < - >, and the oxide film 7 on the transition region is still left to be 0.23 microns.
Thereafter, as shown in FIG. 9C, P + implantation, e.g., B implantation, is performed to 50Kev to 60Kev, 1E15cm-2～2E15cm-2Then, since the oxide film 7 is protected in the transition region, the peak value of B ions falls in the oxide film 7, so that the concentration of ions in the transition region is significantly lower than that in the charge flow region, and by adjusting the thickness of the oxide film 0 and the energy of P + implantation, the P-type dose in the transition region, i.e., the peak value of the second P + contact region 132f, can be 1/2 to 1/10 of the peak value of the first P + contact region 131 f. If the concentration of the P-type impurity in the charge flow region is 1E19cm-3Then the impurity dose in the transition region would be 5E18cm-3～1E18cm-3,Therefore, the value is greatly reduced, the capacity of collecting holes is reduced, and the softness factor of the body diode can be effectively increased.
Thereafter, as shown in fig. 9D, the oxide film 7 remaining in the second contact hole 121b is removed and the photoresist on the top of the interlayer film 11 is removed.
The fourth embodiment superjunction device of the present invention as shown in fig. 7 can be formed by the same subsequent steps as the first embodiment method of the present invention.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (16)

1. A super junction device is provided, wherein the middle region of the super junction device is a charge flowing region, a terminal region surrounds the periphery of the charge flowing region, and a transition region is positioned between the charge flowing region and the terminal region; it is characterized by comprising:
the N-type epitaxial layer is subjected to dry etching to form a plurality of grooves; the groove is filled with a P-type epitaxial layer to form a P-type column, the N-type epitaxial layer between the P-type columns forms an N-type column, and the super junction structure is formed by a plurality of alternately arranged N-type columns and P-type columns;
forming a P-type well in a selected region of the charge flow region and a P-type ring in a selected region of the transition region; one P-type well is formed at the top of each P-type column in the charge flowing region, and each P-type well extends to the surface of the corresponding N-type column on two sides of the corresponding P-type column;
a protective epoxy film that exposes the charge flow region and entirely covers the transition region, the protective epoxy film further extending to the surface of the termination region and entirely covering the termination region or partially covering the termination region so as to expose only an outermost peripheral portion of the termination region, the protective epoxy film surrounding the periphery side of the charge flow region;
a planar gate structure formed by overlapping a gate oxide film and a polysilicon gate is formed on the surface of the super junction structure of the charge flowing area, each polysilicon gate covers the corresponding P-type well, and the surface of the P-type well covered by the polysilicon gate is used for forming a channel;
forming active regions on two sides of the polysilicon gate in the charge flowing region respectively;
forming an interlayer film on the front surface of the N-type epitaxial layer, wherein the interlayer film covers the surfaces of the protective epoxy film in the source region and the polysilicon gate of the charge flowing region and the transition region and the termination region;
a front metal layer is formed on the surface of the interlayer film; the grid electrode and the source electrode are formed by patterning the front metal layer; each of the source regions and the corresponding P-type well in the charge flow region are connected to the source electrode through a first contact hole with the same top, the P-type ring in the transition region is connected to the source electrode through a second contact hole with the same top, and the polysilicon gate is connected to the gate electrode through a third contact hole with the same top;
each first contact hole penetrates through the interlayer film and the source region at the bottom to be contacted with the P-type well at the bottom, each second contact hole penetrates through the lamination of the interlayer film and the protection ring oxide film to be contacted with the P-type ring at the bottom, a first P + contact region is formed at the bottom of each first contact hole, a second P + contact region is formed at the bottom of each second contact hole, the characteristic that each second contact hole needs to penetrate through the protection epoxy film so that the bottom of each second contact hole penetrates into the N-type epitaxial layer with the super junction structure to a depth which is shallower than the depth of the first contact hole penetrating into the N-type epitaxial layer with the super junction structure is utilized, the junction depth of the second P + contact region is shallower than the junction depth of the first P + contact region, and therefore the distance of a cavity collected by the P-type ring to reach the second P + contact region is increased, increasing the softness factor of the reverse recovery of the body diode of the device.
2. The superjunction device of claim 1, wherein: the doping concentration of the first P + contact region and the doping concentration of the second P + contact region are the same.
3. The superjunction device of claim 1, wherein: the doping concentration of the second P + contact region is smaller than that of the first P + contact region, so that the capability of the second P + contact region for collecting holes is weakened, and the softness factor of reverse recovery of a body diode of the device is increased.
4. The superjunction device of claim 3, wherein: the peak value of the doping concentration of the second P + contact region is 1/2-1/10 of the peak value of the doping concentration of the first P + contact region.
5. The superjunction device of claim 3 or 4, wherein: after the opening of the first contact hole is etched to a depth required by penetrating through the source region, the bottom of the second contact hole is also provided with a protective ring oxide film with a partial thickness, the first P + contact region and the second P + contact region are simultaneously formed by adopting the same P + implantation process, the P + implantation of the second P + contact region can penetrate through the characteristic of the reserved protective ring oxide film to enable the doping concentration of the second P + contact region to be smaller than that of the first P + contact region, and then the reserved protective ring oxide film is removed;
or, the opening of the first contact hole and the opening of the second contact hole are etched simultaneously by the same process, after the doping concentration required by forming the second P + contact region by overall P + injection is carried out, the second contact hole is protected by a photoetching process, and the concentration required by forming the first P + contact region by adding one P + injection to the bottom of each first contact hole.
6. The superjunction device of claim 1, wherein: the width of the second contact hole is smaller than that of the first contact hole, so that the width of the second P + contact region is reduced, the distance from the hole collected by the P-type ring to the second P + contact region is increased from the transverse direction, and the softness factor of the reverse recovery of the body diode of the device is increased.
7. The superjunction device of claim 1, wherein: the P-type ring covers more than two P-type columns, and the number of holes needing to be collected in the reverse recovery process is increased, so that the softness factor of the reverse recovery of the body diode of the device is increased.
8. The superjunction device of claim 1, wherein: the processes of the P-type ring and the P-type well are the same;
or the process of the P-type ring is independent of the process of the P-type well, and the junction depth of the P-type ring is larger than that of the P-type well, so that the distance from the hole collected by the P-type ring to the second P + contact region is increased, and the reverse recovery softness factor of the body diode of the device is increased.
9. The superjunction device of claim 1, wherein: the depth of the bottom of each second contact hole penetrating into the N-type epitaxial layer is 0-500 angstroms, and the depth of the first contact hole penetrating into the N-type epitaxial layer is larger than 2000 angstroms.
10. A manufacturing method of a super junction device is provided, wherein the middle area of the super junction device is a charge flowing area, a terminal area surrounds the periphery of the charge flowing area, and a transition area is positioned between the charge flowing area and the terminal area; the method is characterized by comprising the following steps:
step one, providing an N-type epitaxial layer, defining a forming area of a groove by a first photoetching process, and then carrying out dry etching on the N-type epitaxial layer to form a plurality of grooves;
filling a P-type epitaxial layer in the groove to form a P-type column, forming an N-type column by the N-type epitaxial layer between the P-type columns, and forming a super junction structure by a plurality of alternately arranged N-type columns and P-type columns;
step two, defining a forming area of a P-type well in the charge flowing area and the transition area by carrying out a second photoetching process, and then carrying out P-type ion implantation to form the P-type well; forming a P-type ring in the transition region;
one P-type well is formed at the top of each P-type column in the charge flowing region, and each P-type well extends to the surface of the corresponding N-type column on two sides of the corresponding P-type column;
performing first oxide film growth on the surface of the N-type epitaxial layer on which the P-type well is formed, performing a third photolithography process to define an etching region of the first oxide film, and then etching the first oxide film to form a guard ring oxide film, wherein the guard ring oxide film exposes the charge flow region and completely covers the transition region, the guard ring oxide film further extends to the surface of the termination region and completely covers the termination region or partially covers the termination region so as to expose only the outermost periphery of the termination region, and the guard ring oxide film surrounds the periphery of the charge flow region;
carrying out overall first N-type ion implantation by taking the guard ring oxide film as a self-alignment condition to form a JFET (junction field effect transistor) region in the charge flowing region, and simultaneously forming a terminal first N-type implantation region in or outside the terminal region outside the protection epoxy film covering region;
sequentially forming a gate oxide film and a first layer of N-type heavily doped polysilicon, defining a forming region of a polysilicon gate by a fourth photoetching process, etching the first layer of polysilicon to form polysilicon gates, wherein each polysilicon gate is of a planar gate structure, covers the corresponding P-type well, and is used for forming a channel on the surface of the P-type well covered by the polysilicon gate;
carrying out comprehensive second N-type ion implantation by taking the polysilicon gate and the guard ring oxide film as self-alignment conditions to form source regions on two sides of the polysilicon gate in the charge flowing region respectively, and simultaneously forming a terminal second N-type implantation region in or outside the terminal region outside the protection epoxy film covering region;
depositing an interlayer film, defining a forming area of a contact hole by a fifth photoetching process, and etching to form an opening of the contact hole;
the openings of the contact holes comprise an opening of a first contact hole positioned at the top of each source region in the charge flowing region and the corresponding P-type well, an opening of a second contact hole positioned at the top of the P-type ring in the transition region and an opening of a third contact hole positioned at the top of each polysilicon gate passing part; openings of the first contact holes penetrate through the interlayer film and the source region at the bottom and the P-type well contact at the bottom, and openings of the second contact holes penetrate through the lamination of the interlayer film and the guard ring oxide film and the P-type well contact at the bottom;
performing P + implantation to form a first P + contact region at the bottom of the opening of each first contact hole and a second P + contact region at the bottom of the opening of the second contact hole; utilizing the characteristic that the opening of each second contact hole needs to penetrate through the protective epoxy film so that the bottom of the opening of each second contact hole penetrates into the N-type epitaxial layer with the super junction structure to a depth which is shallower than the depth of the opening of the first contact hole penetrating into the N-type epitaxial layer with the super junction structure, so that the junction depth of the second P + contact region is shallower than the junction depth of the first P + contact region, the distance from a hole collected by the P-type ring to the second P + contact region is increased, and the softness factor of reverse recovery of a body diode of the device is increased;
filling metal into the opening of the contact hole to form the contact hole;
and sixthly, depositing front metal to form a front metal layer, defining forming areas of a grid electrode and a source electrode by carrying out a sixth photoetching process, etching the front metal layer to form the grid electrode and the source electrode, connecting each source region in the charge flowing region and the corresponding P-type well to the source electrode through the first contact hole with the same top, connecting the P-type ring in the transition region to the source electrode through the second contact hole on the top, and connecting the polysilicon gate to the grid electrode through the third contact hole on the top.
11. The method of manufacturing a superjunction device of claim 10, wherein: and fifthly, simultaneously etching the opening of the first contact hole and the opening of the second contact hole by adopting the same process, and simultaneously performing the P + injection processes of the first P + contact region and the second P + contact region to ensure that the doping concentrations of the first P + contact region and the second P + contact region are the same.
12. The method of manufacturing a superjunction device of claim 10, wherein: in the fifth step, the opening of the first contact hole and the opening of the second contact hole are etched simultaneously by adopting the same process, after the doping concentration required by forming the second P + contact region by overall P + injection is carried out, the opening of the second contact hole is protected by adopting a photoetching process, the concentration required by forming the first P + contact region by one P + injection is added at the bottom of the opening of each first contact hole, so that the doping concentration of the second P + contact region is smaller than that of the first P + contact region, the capability of collecting holes by the second P + contact region is weakened, and the softness factor of the reverse recovery of the body diode of the device is increased;
or after the opening of the first contact hole is etched to a depth required by penetrating through the source region, the bottom of the second contact hole also retains a part of thickness of the protection ring oxide film, the first P + contact region and the second P + contact region are simultaneously formed by adopting the same P + injection process, and the P + injection of the second P + contact region can penetrate through the retained characteristic of the protection ring oxide film to ensure that the doping concentration of the second P + contact region is smaller than that of the first P + contact region, so that the capability of the second P + contact region for collecting holes is weakened, and the softness factor of the reverse recovery of a body diode of the device is increased; and removing the remaining guard ring oxide film.
13. The method of manufacturing a superjunction device of claim 12, wherein: the peak value of the doping concentration of the second P + contact region is 1/2-1/10 of the peak value of the doping concentration of the first P + contact region.
14. The method of manufacturing a superjunction device of claim 10, wherein: in the second step, the P-type ring is formed simultaneously by adopting the same process as the P-type well;
or, in the second step, the P-type ring is formed by separately adopting a photoetching and ion implantation process, and the junction depth of the P-type ring is greater than that of the P-type well, so that the distance from the hole collected by the P-type ring to the second P + contact region is increased, and the reverse recovery softness factor of the body diode of the device is increased.
15. The method of manufacturing a superjunction device of claim 10, wherein: the width of the second contact hole is smaller than that of the first contact hole, so that the width of the second P + contact region is reduced, the distance from the hole collected by the P-type ring to the second P + contact region is increased from the transverse direction, and the softness factor of the reverse recovery of the body diode of the device is increased.
16. The method of manufacturing a superjunction device of claim 10, wherein: the P-type ring covers more than two P-type columns, and the number of holes needing to be collected in the reverse recovery process is increased, so that the softness factor of the reverse recovery of the body diode of the device is increased.
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