CN108428691A - The forming method of contact plunger and semiconductor devices - Google Patents
The forming method of contact plunger and semiconductor devices Download PDFInfo
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- CN108428691A CN108428691A CN201810210995.2A CN201810210995A CN108428691A CN 108428691 A CN108428691 A CN 108428691A CN 201810210995 A CN201810210995 A CN 201810210995A CN 108428691 A CN108428691 A CN 108428691A
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- contact plunger
- barrier material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
Abstract
The forming method of a kind of contact plunger and semiconductor devices provided by the present invention, when forming metal silicide barrier layer, make to be formed with larger-size first gap on the bottom of metal silicide barrier layer respective protrusions structure side wall, to make interlayer dielectric layer that can also form larger-size Second gap accordingly on the position of first gap in subsequently filling interlayer dielectric layer, and it is connected to completely with contact hole.Thus, in conjunction with baking process, residual gas or liquid etc. in Second gap can be effectively removed, and then Second gap is made to be emptied, so that no longer having the condition for forming cavity in the filling process of conductive material, to be conducive to improve the filling effect of conductive material layer, avoid forming cavity in finally formed contact plunger, and then realize semiconductor devices and contacted with the good of metal interconnecting layer, ensure the normal work of device.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to the forming methods of a kind of contact plunger and semiconductor devices.
Background technology
In the preparation process of integrated circuit, in order to realize the electrical extraction of the elements such as CMOS, need semiconductor devices
Be electrically connected with the metal interconnecting wires on upper layer, currently, most common method be semiconductor devices and metal interconnecting wires it
Between interlayer dielectric layer (Inter-Layer Dielectric, ILD) in formed contact hole, and in the contact hole fill tungsten, copper
Or the conductive materials such as aluminium are electrically connected to form contact plunger (contact) with realizing.
However, the present inventor when using prior art preparation contact plunger, has found in filling conductive material
The situation for easily occurring cavity in the process, to seriously affect the company for being formed by contact plunger and element and metal interconnecting wires
The problem of connecing performance, and then leading to entire semiconductor device failure.
Invention content
The purpose of the present invention is to provide a kind of forming methods of contact plunger, to solve in existing forming method, pole
It easily leads to be formed by and has cavity in contact plunger.
The present invention provides a kind of forming methods of contact plunger, including：
One substrate is provided, there is a bulge-structure in the substrate, and be arranged on at least side of the bulge-structure
Wait for draw-out area；
A barrier material layer is formed on the substrate, and the barrier material layer covers the side wall of the bulge-structure and prolongs
The surface for covering the substrate is stretched, so as to cover the part of the bulge-structure side wall and the blocking in the barrier material layer
The part that the substrate surface is covered in material layer is connected with each other in the bottom of the bulge-structure；
A mask layer is formed on the barrier material layer, the mask layer covers the top of the bulge-structure and exposure
Wait for that draw-out area and the side wall of the bulge-structure expose on the direction for be parallel to substrate surface described in going out；
Etching technics is executed to the barrier material layer, with expose it is described wait for draw-out area, and make the barrier material layer
In be covered in part on the bulge-structure side wall and be retained, the barrier material layer after etching constitutes metal silicide barrier layer,
And when etching the barrier material layer, correspondence generates in the part of the bulge-structure bottom in the barrier material layer
There is first gap；
An interlayer dielectric layer is formed on the metal silicide barrier layer, the interlayer dielectric layer covers the metal silicide
Barrier layer, and the interlayer dielectric layer is formed with Second gap accordingly on the position of the first gap, and in institute
It states and is also formed with a contact hole in interlayer dielectric layer, the contact hole is connected to and is exposed with the Second gap and described waits drawing
Area；
Baking process is executed to the substrate；
Conductive material is filled into the contact hole to form the contact plunger.
Optionally, include to the method for barrier material layer execution etching technics:
Using the mask layer be mask to the barrier material layer execute dry etch process, and be etched to predetermined thickness with
Member-retaining portion barrier material layer；
It removes the mask layer and wet-etching technology is executed to the barrier material layer, removal waits for the whole on draw-out area
Barrier material layer waits for draw-out area to expose, and forms the metal silicide barrier layer.
Optionally, the etch period for extending the wet-etching technology, to increase the size of the first gap, and it is corresponding
Increase the size of the Second gap, until so that the Second gap is connected to completely with the contact hole.
Optionally, the interlayer dielectric layer is formed using high density plasma CVD technique.
Optionally, it after forming metal silicide barrier layer, and is formed before interlayer dielectric layer, draw-out area is waited for described
One metal silicide layer of upper formation.
Optionally, the material on the metal silicide barrier layer is silica.
Optionally, the interlayer dielectric layer is the laminated construction of silicon nitride layer and silica glass layer.
Optionally, the material of the contact plunger includes tungsten, aluminium or copper.
The present invention also provides a kind of forming methods of semiconductor devices, use the formation side of above-mentioned contact plunger
Method.
The forming method of a kind of contact plunger and semiconductor devices provided by the present invention, analyzes in contact plunger and fills
Conductive material there is the reason in cavity, and when forming metal silicide barrier layer, make metal silicide barrier layer respective protrusions knot
Larger-size first gap is formed on the bottom of structure side wall, to which inter-level dielectric can be made in subsequently filling interlayer dielectric layer
Layer can also form larger-size Second gap accordingly on the position of first gap, and be connected to completely with contact hole.Such as
This one, residual gas or liquid etc. in conjunction with baking process, can effectively removed in Second gap (for example, graphical
When interlayer dielectric layer, reagent etc. remaining when the residues such as photoresist is further removed), and then Second gap is made to be emptied, make
The condition for no longer having in the filling process of conductive material and forming cavity is obtained, to be conducive to improve the filling of conductive material layer
Effect avoids forming cavity in finally formed contact plunger, and then realizes the good of semiconductor devices and metal interconnecting layer
Good contact, has ensured the normal work of device.
Description of the drawings
Fig. 1 is the shape appearance figure of the contact plunger formed using the prior art；
Fig. 2 is the local shape appearance figure of the contact plunger formed using the prior art；
Fig. 3 is the flow diagram of the forming method of contact plunger in the present invention；
Fig. 4~Fig. 6 is the structural schematic diagram of the forming method of contact plunger in one embodiment of the invention.
Specific implementation mode
The inventors found that the semiconductor devices prepared by forming method with existing contact plunger, meeting
There is the problem of disabler.Specifically, inventor is during preparing a kind of flash element, experimentally to the flash memory
After element is wiped, it is found that the storage state of a part of flash cell is not restored to its due state (i.e. flash memory list
Storage position in member still keeps low potential, the state without being restored to high potential after being erased), and then inventor is directed to and deposits
Physical failure analysis has been carried out in the flash cell of problem.
Fig. 1 is the shape appearance figure of the contact plunger formed using the prior art, refering to what is shown in Fig. 1, being not difficult to find out connecing for right side
It is very poor to touch packing material uniformity in plug, wherein more cavity is contained, so that the gold of semiconductor devices and upper layer
It is poor to belong to interconnection line contact, is electrically connected and cannot be satisfied requirement, it is clear that the contact for resulting in right side just because of this reason is inserted
Semiconductor device failure where filling in.On this basis, the present inventor has further probed into and has filled material in contact plunger
The reason in cavity is generated in material.
Fig. 2 is the local shape appearance figure of the contact plunger formed using the prior art, refering to what is shown in Fig. 2, inventor carefully sees
After the pattern for having examined the contact plunger and its peripheral structure, send out now close to the contact plunger bottom interlayer dielectric layer it
It is middle there are hole (region being circled in Fig. 2), which may generate between contact hole and be connected to.Inventor proposes immediately
A kind of imagination, it is believed that cavity in the contact plunger to primarily form reason related with described hole.Further, in conjunction with
The forming method of contact plunger in the prior art, inventor give the explanation that a kind of hole causes contact plunger cavity.
First, described hole is formed as caused by the wet-etching technology on metal silicide barrier layer, since wet etching is one
The isotropic lithographic method of kind, and then at the bottom of etch stopper material layer, inevitably will produce certain overetch, make
It obtains the side wall close to bottom and also receives a degree of etching, to form a groove (i.e. first gap) in bottom,
And the interlayer dielectric layer being subsequently formed is likely to preferably to be bonded and be filled into the interior groove, so as to cause the hole
The formation in hole (i.e. Second gap)；Secondly, in the etching process of forming process, that is, interlayer dielectric layer of contact hole, described hole
It is easy to be connected to contact hole generation, and then during removing photoresist, the reagents such as glue is caused to flow into the hole
Hole；Finally, when filling conductive material in the contact hole (what is be generally filled with is the metal material such as tungsten, aluminium or copper), by
It is higher in reaction temperature, cause to remain in hole and go the heated volatilization of the reagents such as glue, releases gas, and be expelled to institute
It states in contact hole, and then has seriously affected the filling effect of conductive material in contact hole.
Based on above-mentioned analysis, occur the problem in cavity in contact plunger to be solved, may be used and eliminate hole, prevent hole
The methods such as the reagent remained in hole are connected to and removed with contact hole, it is however generally that, alternatively it is conceivable to by controlling contact hole
Critical size size when formation, and its overlay alignment is controlled, so that contact hole can also pass through increasing far from described hole
The synthesis speed for adding interlayer dielectric layer reduces described hole size to obtain better coverage effect, however, these methods
Stability is poor, and can not tackle the problem at its root.Based on the above circumstances, the present inventor creatively finds out
A kind of more structurally sound solution.
Formation below in conjunction with the drawings and specific embodiments to a kind of contact plunger proposed by the present invention and semiconductor devices
Method is described in further detail.According to following explanation, advantages and features of the invention will become apparent from.It should be noted that attached drawing
It is all made of very simplified form and uses non-accurate ratio, only to convenient, lucidly the aid illustration present invention is implemented
The purpose of example.
Fig. 3 is the flow diagram of the forming method of contact plunger in the present invention, and Fig. 4~Fig. 6 is one embodiment of the invention
The structural schematic diagram of the forming method of middle contact plunger, shown in Fig. 3~Fig. 6.
In step sl, a substrate 1 is provided, there is a bulge-structure 2 in the substrate 1, and in the bulge-structure 2
It is at least provided with one on side and waits for draw-out area (not shown)；
Specifically, refering to what is shown in Fig. 4, the material of the substrate 1 is, for example, the semi-conducting materials such as silicon or germanium silicon, it is described convex
Structure 2 is played such as can be gate structure, it is described to wait for draw-out area such as be source region or drain region.People in the art
Member is it is understood that the formation of the contact plunger in the present embodiment is not limited only in mos devices, but is had similar
Like the contact plunger of structure, can the respective application present invention contact plunger forming method, and formed contact plunger purpose
It is provided to realize and waits for being formed in the metal interconnecting layer above element in the semiconductor devices in draw-out area and subsequent technique
It is electrically connected.
In step s 2, a barrier material layer 300 is formed on the substrate, and the barrier material layer 300 covers described
The side wall of bulge-structure 2 and the surface for extending over the substrate 1, so as to cover the protrusion in the barrier material layer 300
The part on 1 surface of the substrate is covered in the part of 2 side wall of structure and the barrier material layer 300 in the bulge-structure 2
Bottom is connected with each other；
In the present embodiment, refering to what is shown in Fig. 4, the formation of the barrier material layer 300, in order that in subsequent silicidation metal layer
Forming process in, protection need not form the region of metal silicide, to prevent these regions from metal silication reaction also occurs, together
The metal silicide barrier layer that Shi Suoshu barrier material layers 300 are formed after over etching is in the forming process of subsequent silicidation metal layer
Also it can play the role of alignment.
In step s3, a mask layer (not shown) is formed on the barrier material layer 300, the mask layer covers institute
It states the top of bulge-structure and exposes and described wait for that the side wall of draw-out area and the bulge-structure is being parallel to substrate surface
It is exposed on direction；
Specifically, the mask layer for example can be photoresist layer.The mask layer is as etch stopper in next step
The mask of material layer, to define the region for waiting for that draw-out area is contacted later.
In step s 4, etching technics is executed to the barrier material layer 300, with expose it is described wait for draw-out area, and make
The part being covered in the barrier material layer 300 on the bulge-structure side wall is retained, the barrier material layer structure after etching
At metal silicide barrier layer 301, and when etching the barrier material layer, corresponded in the protrusion in the barrier material layer
There is first gap 4 in the part of 2 bottom of structure；
As a preferred option, include to the method for the execution etching technics of the barrier material layer 300:
First step executes dry etch process to the barrier material layer 300 using the mask layer as mask, and etches
To predetermined thickness with member-retaining portion barrier material layer；
Specifically, to the dry etch process that the barrier material layer 300 executes, such as plasma etching may be used
The method of (Plasma Etching, PE).
Second step removes the mask layer and executes wet-etching technology to the barrier material layer 300, removes and wait drawing
Go out whole barrier material layers in area, draw-out area is waited for expose, forms the metal silicide barrier layer 301.
Specifically, in the wet-etching technology, the chemical etchant of use is, for example, diluted hydrofluoric acid.Due to wet
Method etching is a kind of isotropic etching, therefore etch rate in all directions is consistent, and in order to ensure etching removal
The barrier material layer of bottom, the part generation being easy to cause in barrier material layer 300 close to the bulge-structure bottom are more
Etching, and then form the first gap 4.
As a preferred option, it after forming metal silicide barrier layer 301, and is formed before interlayer dielectric layer,
It is described to wait for forming a metal silicide layer 5 on draw-out area.
Specifically, refering to what is shown in Fig. 5, the metal silicide layer 5 for example can be Titanium silicide, cobalt silicide or nickel suicide
The metal silicides such as object.The metal silicide layer 5 can play the hole resistance for reducing contact hole and contact hole and semiconductor devices
Wait for draw-out area (such as source region or drain region) be electrically connected contact resistance effect.
In step s 5, an interlayer dielectric layer 6, the interlayer dielectric layer 6 are formed on the metal silicide barrier layer 301
Cover the metal silicide barrier layer 301, and the corresponding shape on the position of the first gap 4 of the interlayer dielectric layer 6
At there is Second gap 7, and a contact hole is also formed in the interlayer dielectric layer 6, the contact hole is empty with described second
Gap 7, which is connected to and exposes, described waits for draw-out area；
As a preferred option, the interlayer dielectric layer 6 is the lamination of silicon nitride layer 601 and undoped silicon glass layer 602
Structure.The forming method of the interlayer dielectric layer 6 includes high density plasma CVD (HDPCVD).
Specifically, refering to what is shown in Fig. 6, the interlayer dielectric layer 6, which is one, is used for isolation of semiconductor devices and metal interconnection
The electric insulation layer of layer.In the present embodiment, the interlayer dielectric layer 6 is silicon nitride layer 601 and undoped silicon glass layer (USG) 602
Laminated construction, it will be appreciated by persons skilled in the art that the interlayer dielectric layer 6 in the present embodiment is only one illustrative to lift
Example, the material of interlayer dielectric layer 6 can also select silica, boron-phosphorosilicate glass (BPSG), phosphosilicate glass (PSG), high score
Sub- polymer material and low-k materials etc..And high density plasma CVD (HDPCVD) and other examples
Such as low-pressure chemical vapor deposition (LPCVD) is compared with gas ions enhancing chemical vapor deposition (PECVD) chemical vapour deposition technique,
It is stronger to the filling capacity of the groove of high-aspect-ratio.However, the filling capacity refers to the integral-filled feelings for groove
Condition when filling the first gap 4, can form Second gap 7 with being still difficult to avoid that under this technique.In addition, the contact
Dry etch process may be used in the formation in hole, and in this not go into detail.
It is understood that in the forming process of the contact hole, the formation one second on interlayer dielectric layer 6 is needed to cover
Film layer (is not shown, be, for example, photoresist layer in the present embodiment), goes out the contact hole as mask etching using second mask layer.
And after contact hole formation, further include the removal step of second mask layer, when removing photoresist, needs to use and light
Photoresist removes the reagents such as glue accordingly, and in stripping process, these reagents just very likely enter in the Second gap, and
The reagent remained in Second gap is difficult to directly remove.
In step s 6, baking process is executed to the substrate；
As a preferred option, the etch period for extending the wet-etching technology, to increase the big of the first gap 4
It is small, and accordingly increase the size of the Second gap 7, until so that the Second gap 7 is connected to completely with the contact hole.
In the present embodiment, baking process is performed to the substrate, so that remaining reagent and institute in the contact hole
The remaining reagent stated in Second gap 7 is volatilized, to fundamentally prevent to generate when conductive material is filled in subsequent touch hole
The condition in cavity.
It should be noted that inventor most starts to directly increase the baking process for executing substrate, can actually play
The remaining reagent in contact hole and in Second gap 7 is set to accelerate the effect of volatilization.However, inventor has had been found that there is also one
The more special situation of kind results in possibility due to the deviation of overlay alignment and the fill rate of interlayer dielectric layer 6
Occur not being connected to completely between Second gap 7 and contact hole, i.e., it is complete there are one not to be between Second gap 7 and contact hole
Whole channel, and it is analogous to that there is many desultory passage aisles so that between the Second gap 7 and contact hole
Junction shows state separated but still in each other's thoughts, causes reagent to be easier to enter in the Second gap 7, but executes baking process
When, it is but difficult to that the reagent in Second gap 7 is made to volatilize completely.
In turn, the idea that the proposition of inventor's creativeness further increases the Second gap 7.Just typically, increase
Big Second gap 7 undoubtedly only can make the cavitation in the contact plunger further deteriorate, however, in the present embodiment, hair
A person of good sense proposes the wet etching time for extending the barrier material layer, and the Second gap 7 is increased, to ensure second
Gap 7 is connected to completely with the contact hole, is also easy to realize in technique.And then when executing baking process, it can ensure that
Remaining reagent in Second gap 7 is completely removed, and then has been inherently eliminated the condition for generating cavity in contact plunger.
Specifically, refering to what is shown in Fig. 6, in one embodiment, the etch period of the wet etching used originally is, for example,
300s, after many experiments, discovery increases to the etch period of the wet etching to be greater than equal to after 345s inventor,
It can ensure that Second gap 7 is connected to completely with the contact hole, add baking process again on this basis, can effectively remove
Remaining reagent in Second gap 7.In fact, in order to verify the feasibility of this programme, inventor also after contact hole is formed, and
Before contact plunger is formed, cleaned that (reagent of cleaning can further fill Second gap 7, lead to sky to the substrate
Hole is worse off), and in the semiconductor devices obtained using the above scheme, the quantity of the component failure of appearance compares original technology
Obtained significant reduction, to also demonstrate by Second gap 7 increase to eliminate the validity in contact plunger cavity with it is feasible
Property.
In the step s 7, conductive material is filled into the contact hole to form the contact plunger 8.
As a preferred option, the material of the contact plunger 8 includes tungsten, aluminium or copper；And forming contact plunger 8
Before, after forming the contact hole, it is also formed with a metal diffusion barrier layer (not shown) in the contact hole.
Specifically, the metal diffusion barrier layer is, for example, Ti/TiN film layers, it can prevent the conductive material of filling from occurring
Diffusion and enter interlayer dielectric layer even in substrate, further, it is possible to be formed with the metal silicide layer at contact hole bottom good
Contact, and improve the adhesion effect of filling conductive material；In the present embodiment, the contact plunger 8 is, for example, tungsten, art technology
Personnel can also select the conductive material such as aluminium or copper according to demand, and this is not restricted.After passing through baking process,
Through eliminating remaining reagent in the Second gap 7, therefore fundamentally avoid caused by reagent residual in Second gap 7
The empty problem of contact plunger 8.
In addition, additionally providing a kind of forming method of semiconductor devices in the present embodiment, above-mentioned contact plunger is used
Forming method, the function so as to ensure semiconductor devices is normal, improves the yields for the semiconductor devices prepared.
In conclusion the forming method of a kind of contact plunger provided by the present invention and semiconductor devices, analyzes contact
There is the reason in cavity in the conductive material filled in plug, and when forming metal silicide barrier layer, makes metal silicide barrier layer
Larger-size first gap is formed on the bottom of respective protrusions structure side wall, thus can in subsequently filling interlayer dielectric layer
Make interlayer dielectric layer that can also form larger-size Second gap accordingly on the position of first gap, and complete with contact hole
Full-mesh.Thus, in conjunction with baking process, can effectively remove residual gas or liquid etc. in Second gap (for example,
In graphical interlayer dielectric layer, reagent etc. remaining when the residues such as photoresist is removed), and then Second gap is made to be emptied,
So that no longer there is the condition for forming cavity in the filling process of conductive material, to be conducive to improve filling out for conductive material layer
Effect is filled, avoids forming cavity in finally formed contact plunger, and then realize semiconductor devices and metal interconnecting layer
Good contact, has ensured the normal work of device.
Obviously, those skilled in the art can carry out invention spirit of the various modification and variations without departing from the present invention
And range.In this way, if these modification and variations of the present invention belong to right of the present invention.
Claims (9)
1. a kind of forming method of contact plunger, which is characterized in that including：
One substrate is provided, there is a bulge-structure in the substrate, and one is provided on at least side of the bulge-structure
Wait for draw-out area；
A barrier material layer is formed on the substrate, and the barrier material layer covers the side wall of the bulge-structure and extension is covered
The surface of the substrate is covered, so as to cover the part of the bulge-structure side wall and the barrier material in the barrier material layer
The part that the substrate surface is covered in layer is connected with each other in the bottom of the bulge-structure；
A mask layer is formed on the barrier material layer, the mask layer covers the top of the bulge-structure and exposes institute
It states and waits for that draw-out area and the side wall of the bulge-structure expose on the direction for be parallel to substrate surface；
Etching technics is executed to the barrier material layer, with expose it is described wait for draw-out area, and make to cover in the barrier material layer
The part covered on the bulge-structure side wall is retained, and the barrier material layer after etching constitutes metal silicide barrier layer, and
It is corresponding in the barrier material layer to have the in the part of the bulge-structure bottom when etching the barrier material layer
One gap；
An interlayer dielectric layer is formed on the metal silicide barrier layer, the interlayer dielectric layer covers the metal silicide blocking
Layer, and the interlayer dielectric layer is formed with Second gap accordingly on the position of the first gap, and in the layer
Between be also formed with a contact hole in dielectric layer, the contact hole, which is connected to and is exposed with the Second gap, described waits for draw-out area；
Baking process is executed to the substrate；
Conductive material is filled into the contact hole to form the contact plunger.
2. the forming method of contact plunger as described in claim 1, which is characterized in that execute etching to the barrier material layer
The method of technique includes:
Dry etch process is executed to the barrier material layer using the mask layer as mask, and is etched to predetermined thickness to retain
Part barrier material layer；
It removes the mask layer and wet-etching technology is executed to the barrier material layer, removal waits for whole blockings on draw-out area
Material layer waits for draw-out area to expose, and forms the metal silicide barrier layer.
3. the forming method of contact plunger as claimed in claim 2, which is characterized in that extend the quarter of the wet-etching technology
The time is lost, to increase the size of the first gap, and accordingly increases the size of the Second gap, until so that described second
Gap is connected to completely with the contact hole.
4. the forming method of contact plunger as described in claim 1, which is characterized in that the interlayer dielectric layer utilizes high density
Plasma activated chemical vapour deposition technique is formed.
5. the forming method of contact plunger as described in claim 1, which is characterized in that formed metal silicide barrier layer it
Afterwards, it and is formed before interlayer dielectric layer, waits for forming a metal silicide layer on draw-out area described.
6. the forming method of contact plunger as described in claim 1, which is characterized in that the material on the metal silicide barrier layer
For silica.
7. the forming method of contact plunger as described in claim 1, which is characterized in that the interlayer dielectric layer is silicon nitride layer
With the laminated construction of silica glass layer.
8. the forming method of contact plunger as described in claim 1, which is characterized in that the material of the contact plunger includes
Tungsten, aluminium or copper.
9. a kind of forming method of semiconductor devices, uses the shape of the contact plunger as described in any one of claim 1-8
At method.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810210995.2A CN108428691B (en) | 2018-03-14 | 2018-03-14 | Contact plug and method for forming semiconductor device |
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| CN201810210995.2A CN108428691B (en) | 2018-03-14 | 2018-03-14 | Contact plug and method for forming semiconductor device |
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