CN108416311A - A kind of azimuth acquisition methods based on programmable gate array and coordinate rotation processing - Google Patents
A kind of azimuth acquisition methods based on programmable gate array and coordinate rotation processing Download PDFInfo
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Abstract
The invention discloses a kind of azimuth acquisition methods based on programmable gate array and coordinate rotation processing, utilize twiddle iterative principle, input data is first converted to cartesian coordinate coefficient x and coordinate coefficient y, again the solution of coordinate coefficient x and coordinate coefficient y, handled by additions and multiplications；For iteration coefficient z, utilize interconnection the Fast Carry Logic (Carry Chain) of the multi input look-up table (LUT) inside FPGA device between resource and programming resource, nonlinear operation involved in azimuthal solution procedure optimizes, and finally obtains azimuth information；In this way according to the progress change data bit wide of interative computation, optimization process flow, while execution efficiency is improved using pipelining, realizes rapid solving.
Description
Technical field
The invention belongs to signal processing and signal measurement technique fields, more specifically, are related to a kind of based on programmable
The azimuth acquisition methods of gate array and coordinate rotation processing.
Background technology
In communication, radar, signal testing and fields of measurement, many times need to calculate the azimuth of incoming signal
And measurement.Such as in the modulation of digital communication system and demodulating process, in time, frequency and Phase synchronization stage calculated complex
Angle.In another example in Radar Signal Processing, angle of arrival (AOA) measures, during angle of arrival poor (DAOA) measurement etc.,
Need quick computer azimuth angle.During computer azimuth angle or slope, it will usually be related to SIN function, cosine function with
And the calculating that arctan function etc. surmounts function.Solution for such nonlinear function, generally use look-up table, grade in engineering
Number expansion and iterative approach three classes method are realized.Look-up table refers to that the functional value of fixed point is preset in memory, in operation
When data are obtained by way of address mapping inquiry, but limited memory capacity limits the storage quantity of functional value, because
Quickly, but precision is not high for the speed of this look-up table.Series expansion and iterative approximation are compared to look-up table, and higher may be implemented
Precision, but time cost of this two classes computational methods in terms of multiplication and floating number processing is very big, the realization of hardware circuit
It is relatively cumbersome and inefficient.
The method calculated by Coordinate Rotation Digital, it would be desirable to occupy more calculation resources and the operation of the multiplication of operation time
It is transformed into addition and shifting function.Due to needed for addition and shifting function calculation resources and operation time well below multiplication grasp
Make, resource occupation and the processing time of entire iterative solution process can be significantly reduced.Programmable gate array (FPGA)
It is a kind of present age widely used programmable digital logic device, complicated mathematical operation can be realized in a manner of parallel processing
And digital logical operation, it is to solve for the ideal application platform of nonlinear function.Therefore, how according to FPGA device internal programmable
The characteristics of logical resource, realizes the quick resolving to orientation, has important theory and engineering application value.
Invention content
It is an object of the invention to overcome the deficiencies of the prior art and provide one kind to be rotated based on programmable gate array and coordinate
The azimuth acquisition methods of processing the characteristics of using programmable gate array digital logic device, realize that Coordinate Rotation Digital calculates
In non-linear trigonometric function iterative solution, complete azimuthal to signal source to measure and calculate.
For achieving the above object, the present invention is a kind of azimuth based on programmable gate array and coordinate rotation processing
Acquisition methods, which is characterized in that include the following steps：
(1), data acquisition and transformation；
Sensor input data is amplified and is filtered by modulate circuit, analog-digital converter ADC is recycled to be turned
It changes, obtains the input data of standard；
Cartesian coordinate transformation is carried out to the input data of standard, obtains the coefficient x in cartesian coordinate system and coefficient y；
(2), setting iteration coefficient z so that coefficient y constantly levels off to zero in iteration rotary course；
Z=z'-d × atan (2-i)
Wherein, z' indicates that last iteration coefficient, i are the number of iteration, and d is iteration direction；
(3), under the control of iteration coefficient z, iteration postrotational coefficient x and coefficient y each time is calculated；
Wherein, x' and y' indicates the last iterative value of coefficient x and coefficient y respectively；
(4), iterations i is determined
According to the iterative calculation in step (3), if the precision of output factor x and coefficient y is w when iterative calculation, that
Iterations i=w+1；
(5), setup algorithm unit
According to the iterative calculation in step (3), when coefficient x is after w/2 iteration, after directly removing w/2 iteration
The calculating of coefficient x；
When coefficient y is after w/2 iteration, rear stage is iterated to calculate into the bit wide of unit adder and multiplier by suitable
Sequence reduces 1 than previous stage computing unit；
(6), final azimuth is obtained
After setting according to step (2)-(5), coefficient x and coefficient y export w precision after w+1 interative computation
Rotation angle accumulated value, using obtaining final azimuth information after coordinate modification.
What the goal of the invention of the present invention was realized in：
The present invention is based on the azimuth acquisition methods of programmable gate array and coordinate rotation processing, utilize twiddle iterative original
Input data, is first converted to cartesian coordinate coefficient x and coordinate coefficient y, then asking coordinate coefficient x and coordinate coefficient y by reason
Solution, is handled by additions and multiplications；For iteration coefficient z, the multi input look-up table inside FPGA device is utilized
(LUT) the interconnection the Fast Carry Logic between resource and programming resource (Carry Chain) is non-involved in azimuthal solution procedure
Linear operation optimizes, and finally obtains azimuth information；In this way according to the progress change data bit wide of interative computation, at optimization
Flow is managed, while execution efficiency is improved using pipelining, realizes rapid solving.
Meanwhile the present invention is based on programmable gate array and the azimuth acquisition methods of coordinate rotation processing also to have with following
Beneficial effect：
(1), the present invention has simplified unrelated with azimuthal angle calculation and weak relevant redundant computation unit module, and uses FPGA
The multi input port of internal LUT units and carry chain constitute carry lookahead adder, realize quickly and effectively angle derivation；
(2), in the case where reaching identical operation precision, it is compared to the processing method of other coordinate rotations, speed is more
Soon, resource occupation is less, customizing functions and cuts more flexible, is not only effectively reduced the occupancy of logical resource in FPGA pieces,
And improve calculation process speed.
Description of the drawings
Fig. 1 is the azimuth acquisition methods schematic diagram the present invention is based on programmable gate array and coordinate rotation processing；
Fig. 2 is the schematic diagram of assembly line calculation stages shown in Fig. 1；
Fig. 3 is addition chain structural schematic diagram in postorder processing stage shown in Fig. 1.
Specific implementation mode
The specific implementation mode of the present invention is described below in conjunction with the accompanying drawings, preferably so as to those skilled in the art
Understand the present invention.Requiring particular attention is that in the following description, when known function and the detailed description of design perhaps
When can desalinate the main contents of the present invention, these descriptions will be ignored herein.
Embodiment
Fig. 1 is the azimuth acquisition methods schematic diagram the present invention is based on programmable gate array and coordinate rotation processing.
In the present embodiment, as shown in Figure 1, a kind of orientation based on programmable gate array and coordinate rotation processing of the present invention
Angle acquisition methods, include the following steps：
S1, the acquisition of sensor die analog quantity and input
Acceleration transducer, attitude transducer, phase discriminator or the analogue data of other type sensors input are acquired, and will
These analogue datas are input to modulate circuit as input signal.
S2, modulate circuit pre-process the sensor die analog quantity of input
Modulate circuit is first amplified analogue data so that the dynamic model of input signal size and analog-digital converter ADC
It encloses as far as possible unanimously, then carries out analog filtering again, remove interference signal.
S3, analog-digital converter ADC carry out analog-to-digital conversion to analog signal, obtain digital signal and are input to FPGA module.
S4, the azimuth information that digital signal is calculated using FPGA module
S4.1, preamble processing stage
Preamble processing stage includes mainly at data mapping module processing, the processing of bit wide expansion module and coordinate transformation module
Reason；
According to the difference of sensor type, the sampled data for being sent to FPGA carries out data mapping processing first.If passed
Sensor data are successive value, reduce measurement and transformed error using the method that more data accumulations are averaging；If sensing data
For happen suddenly discrete magnitude type, then data no longer do the operation being averaging.Resolution ratio for sample conversion ADC is 14, is considered
To the bit wide spills-over effects of data when operation, 14 data are extended to 16.Data highest order after extension is sign bit, 0
Indicate positive number, 1 indicates negative.After bit wide extends and increases sign bit, need to be coordinately transformed.With four-way azimuth
For phase detector voltage output, the voltage difference of horizontal direction two-way phase discriminator is coordinate coefficient x, vertical direction two-way phase discriminator electricity
Pressure difference is coordinate coefficient y.Ideal angle rotation section is Descartes's rectangular coordinate system first quartile, i.e. [0, pi/2] angular area
Between, and there is (0,0) in the highest order sign bit of coordinate coefficient x and y, (1,0), (1,1) and (0,1) four kinds of combinations, correspond to respectively
First, second, third and fourth quadrant.Therefore, coordinate coefficient first quartile is adjusted to by coordinate transform to calculate, first as
Angle modification is carried out again after the completion of limit azimuthal angle calculation.This first adjustment calculates the mode for correcting output again, is accounted in logical resource
With and calculating speed on it is all more efficient than the direct operation of panoramic limit.
S4.2, assembly line calculation stages
1) iteration coefficient z, is calculated so that coefficient y constantly levels off to zero in iteration rotary course；
Z=z'-d × atan (2-i)
Wherein, z' indicates that last iteration coefficient, i are the number of iteration, and d is iteration direction；
Wherein, by current coefficient y, residing quadrant determines iteration direction d in a coordinate system；If coefficient y is in four-quadrant
Limit, then d is negative, coefficient y is rotated counterclockwise, otherwise d is just, and coefficient y is rotated clockwise；
2), under the control of iteration coefficient z, iteration postrotational coefficient x and coefficient y each time is calculated；
Wherein, x' and y' indicates the last iterative value of coefficient x and coefficient y respectively；
3) iterations i, is calculated
According to the iterative calculation in step 2), if the precision of output factor x and coefficient y is w when iterative calculation,
Iterations i=w+1；
4), setup algorithm unit
According to the iterative calculation in step 2), when coefficient x is after w/2 iteration, it is after directly removing w/2 iteration
The calculating of number x；
When coefficient y is after w/2 iteration, rear stage is iterated to calculate into the bit wide of unit adder and multiplier by suitable
Sequence reduces 1 than previous stage computing unit；
In the present embodiment, using pipeline iterative, function logic inside FPGA improves operation with " space for time "
Processing speed, assembly line computing unit basic structure are as shown in Figure 2.Per level-one interative computation unit by two carry lookahead adders
Device and two shift registers composition, adder and the bit wide of shift register and the bit wide of coefficient are identical, and by quickly into
Position chain extension interconnection.Since coordinate coefficient is extended to 16 by preamble processing unit, output data precision w is 16, total
Pipeline series are 17 grades.Preceding 8 level production line is to coordinate coefficient x processing, and after the 9th grade, and coordinate coefficient x is with the 8th
The value that grade obtains participates in subsequent twiddle operation.Required 17 decomposition rotation angle characteristic value in iteration coefficient z calculating process
It is read in preset ROM by look-up table.Further, since the step value of coordinate y rotations is the preceding half once rotated, that is, manage
Primary by the rotation of upper coordinate, the value of coordinate coefficient y reduces half, it is contemplated that the leading effect of single rotation, the present embodiment is from the
Three class pipeline starts, and the bit wide of coordinate coefficient y computing units is successively decreased 1 in order, and the bit wide of level-one is 4 to the end.It is logical
Cutting redundant computation unit bit wide is crossed, twiddle iterative arithmetic speed is improved under the premise of ensureing computational accuracy.Repeatedly by 17 times
After generation rotation, the value of coordinate coefficient y is less than 0.001, and corresponding azimuth is less than 0.01 degree, has reached the requirement of computational accuracy.
S4.3, postorder processing stage
Final azimuth be the cumulative of each twiddle iterative value and.In order to improve cumulative speed, the present embodiment utilizes
Carry Chains structure between the middle-and-high-ranking look-up table unit ALUT of Stratix Series FPGA devices and unit is constituted super
Advanced potential adder link, addition link structure are as shown in Figure 3.Arithmetic speed is improved by assembly line and carry chain cascaded,
First order carry chain initial value is set as 0, and the value of rear class carry chain is then added by the input and current pipeline of previous stage carry chain
The result of musical instruments used in a Buddhist or Taoist mass output determines.Due to being extended to data in preamble processing step, the sign bit of z when rotating clockwise
It is 0, highest sign bit is 1 when rotation counterclockwise, therefore can utilize two's complement arithmetic rule in a unit simultaneously
Realize addition and subtraction.After azimuthal angle calculation, the twiddle iterative accumulated value of addition link output is sent to postorder processing
Unit carries out azimuth amendment.According to the quadrant where original coordinates coefficient x and y, by the first quartile being calculated [0, pi/2]
Rotation angle value be remapped to the section [0,2 π] or the section [- π, π], obtain final azimuthal angle calculation value.It repaiies at azimuth
After just terminating, data are stored in FIFO so that other function logic function modules use, and proceed by and transport next time
It calculates.Azimuthal of the present invention solves interative computation unit and is simplified and optimized, therefore under assembly line executive mode, according to
The series of assembly line, the register number needed in calculating process is also corresponding therewith to be reduced.It is real in 16 precision azimuthal angle calculations
It applies in example, compared with traditional coordinate rotation derivation algorithm, it is possible to reduce the about logical resource consumption of one third.
Although the illustrative specific implementation mode of the present invention is described above, in order to the technology of the art
Personnel understand the present invention, it should be apparent that the present invention is not limited to the range of specific implementation mode, to the common skill of the art
For art personnel, if various change the attached claims limit and determine the spirit and scope of the present invention in, these
Variation is it will be apparent that all utilize the innovation and creation of present inventive concept in the row of protection.
Claims (3)
1. a kind of azimuth acquisition methods based on programmable gate array and coordinate rotation processing, which is characterized in that including following
Step：
(1), data acquisition and transformation；
Sensor input data is amplified and is filtered by modulate circuit, recycles analog-digital converter ADC to be converted, obtains
To the input data of standard；
Cartesian coordinate transformation transformation is carried out to the input data of standard, obtains the coefficient x in cartesian coordinate system and coefficient y；
(2), setting iteration coefficient z so that coefficient y constantly levels off to zero in iteration rotary course；
Z=z'-d × atan (2-i)
Wherein, z' indicates that last iteration coefficient, i are the number of iteration, and d is iteration direction；
(3), under the control of iteration coefficient z, iteration postrotational coefficient x and coefficient y each time is calculated；
Wherein, x' and y' indicates the last iterative value of coefficient x and coefficient y respectively；
(4), iterations i is determined
According to the iterative calculation in step (3), if the precision of output factor x and coefficient y is w when iterative calculation, change
Generation number i=w+1；
(5), setup algorithm unit
According to the iterative calculation in step (3), when coefficient x after after w/2 iteration, directly removing w/2 iteration coefficient x
Calculating；
When coefficient y is after w/2 iteration, the bit wide that rear stage is iterated to calculate to unit adder and multiplier compares in order
Previous stage computing unit reduces 1；
(6), final azimuth is obtained
After setting according to step (2)-(5), coefficient x and coefficient y export the rotation of w precision after w+1 interative computation
Angle accumulated value, using obtaining final azimuth information after coordinate modification.
2. a kind of azimuth acquisition methods based on programmable gate array and coordinate rotation processing according to claim,
It is characterized in that, by current coefficient y, residing quadrant determines the iteration direction d in a coordinate system；If coefficient y is in four-quadrant
Limit, then d is negative, coefficient y is rotated counterclockwise, otherwise d is just, and coefficient y is rotated clockwise.
3. a kind of azimuth acquisition methods based on programmable gate array and coordinate rotation processing according to claim 1,
It is characterized in that, in the step (6), the computational methods of rotation angle accumulated value are after each iteration：Utilize Stratix series
Carry Chains structure between the middle-and-high-ranking look-up table unit ALUT of FPGA device and unit constitutes carry lookahead adder
Link, to realize cumulative summation by assembly line and carry chain cascaded mode.
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