CN108390675B - Phase discriminator of exclusive-or gate - Google Patents
Phase discriminator of exclusive-or gate Download PDFInfo
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- CN108390675B CN108390675B CN201810461029.8A CN201810461029A CN108390675B CN 108390675 B CN108390675 B CN 108390675B CN 201810461029 A CN201810461029 A CN 201810461029A CN 108390675 B CN108390675 B CN 108390675B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
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Abstract
The invention discloses an exclusive-or gate phase discriminator which is commonly used with a digital module to form a loop. The four-input current-mode logic exclusive-or gate phase discriminator uses the rising and falling of two output voltages to represent the phase difference between input signals, so that the phase discrimination speed is high, and the phase discrimination resolution is twice that of the traditional exclusive-or gate phase discriminator; the output voltage of the phase discriminator is directly input into the resistor voltage dividing network, and compared with the existing capacitor switch voltage dividing network, the structure is simple, the load is lower, and the power consumption is lower; the pipeline comparator sends the phase detected output status word to the digital circuit.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a phase detector with a pipeline comparator, which is used for detecting phase differences between input signals.
Background
The digital-to-analog converter (Digital to Analog Converter, abbreviated as DAC) converts a digital signal into an analog signal, and in the research of the circuit, the most important is the correct transmission of each stage of data, and in order to ensure the correct transmission of data, the design emphasis and difficulty lie in the time sequence problem between the digital domain clock and the analog domain clock, and if the sampling position is not ideal or an error occurs, the performance of the DAC will be directly affected. Therefore, the phase detector with high speed, low power consumption and high resolution is designed to greatly improve the accuracy and reliability of data sampling.
Disclosure of Invention
The invention aims to: in order to solve the problems existing in the prior art and improve the phase discrimination speed and the phase discrimination resolution, the invention provides an exclusive-OR gate phase discriminator.
The technical scheme is as follows: the input end of the four-input exclusive-or gate phase detector is connected with two pairs of differential signals, and the output end outputs a pair of phase detector output voltages; the pipeline comparator comprises a first resistor voltage-dividing network, a second resistor voltage-dividing network and a plurality of comparators, wherein the first resistor voltage-dividing network and the second resistor voltage-dividing network are symmetrical and both comprise two NMOS (N-channel metal oxide semiconductor) tubes and a plurality of resistors, the resistors are connected in series between the two NMOS tubes, and the number of the resistors in the resistor voltage-dividing network is equal to that of the comparators; the output voltages of the phase discriminator are respectively connected with the input ends of the first resistor voltage dividing network and the second resistor voltage dividing network, and the first resistor voltage dividing network and the second resistor voltage dividing network obtain a plurality of output voltages after being divided by the resistors; the method comprises the steps of connecting a plurality of output voltages of a first resistor voltage dividing network with inverting input ends of a plurality of comparators, connecting a plurality of output voltages of a second resistor voltage dividing network with non-inverting input ends of the plurality of comparators, and outputting state words by output ends of the plurality of comparators.
Preferably, the four-input exclusive-OR gate phase discriminator comprises six NMOS input tubes and two resistors, wherein the six NMOS input tubes comprise an input tube M0, an input tube M1, an input tube M2, an input tube M3, an input tube M4 and an input tube M5, and the two resistors are a resistor R1 and a resistor R2; the grid electrode of the input tube M0 and the grid electrode of the input tube M3 are connected with an input signal clkp, the grid electrode of the input tube M1 and the grid electrode of the input tube M2 are connected with an input signal clkn, the grid electrode of the input tube M4 is connected with an input signal d, the grid electrode of the input tube M5 is connected with an input signal db, one end of the resistor R1 is connected with a power supply voltage, the other end of the resistor R2 is connected with the drain electrode of the input tube M1 and the drain electrode of the input tube M3, the node voltage connected with the three ends is connected with the drain electrode of the input tube M1 and the drain electrode of the input tube M4 as a phase detector output voltage voutp, the source electrodes of the input tube M2 and the input tube M3 are connected with the drain electrode of the input tube M5, and the source electrodes of the input tube M4 and the input tube M5 are grounded; the input signals clkp and clkn are a pair of differential signals, and the input signals d and db are a pair of differential signals; the phase detector output voltage voutn and the phase detector output voltage voutp are a pair of phase detector output voltages.
Preferably, the first resistor divider network includes an NMOS tube M6, an NMOS tube M8, a resistor Rn1, a resistor Rn2 … …, and a resistor Rnt; the second resistor divider network comprises an NMOS tube M7, an NMOS tube M9, a resistor Rp1, a resistor Rp2 and a resistor Rpt … …; wherein t is the number of comparators; the drains of the NMOS tube M6 and the NMOS tube M7 are connected with power supply voltage, the grid of the NMOS tube M6 is connected with the output voltage voutn of the phase discriminator, the grid of the NMOS tube M7 is connected with the output voltage voutp of the phase discriminator, the grids of the NMOS tube M8 and the NMOS tube M9 are connected with a bias circuit, a resistor Rn1, a resistor Rn2 … … resistor Rnt and a drain of the NMOS tube M8 are sequentially connected from the source of the NMOS tube M6, t is the number of resistors in each group of resistor voltage division network, and t resistors divide the voltage into Vn0 and Vn1 … … Vnt; the resistor Rp1, the resistor Rp2 and the resistor Rpt … … are sequentially connected from the source of the NMOS tube M7 to the drain of the NMOS tube M9, and the t resistors divide the voltage into Vp0 and Vp1 … … Vpt; the inverting input end of the comparator is connected with the voltage Vn, and the non-inverting input end of the comparator is connected with the corresponding voltage Vp.
Preferably, the output ends of the comparators output state words and are connected with a subsequent digital circuit.
Preferably, the width-to-length ratio of the NMOS tube M6 and the NMOS tube M7 is equal; the pipe width-length ratio of the NMOS pipe M8 is equal to that of the NMOS pipe M9.
Preferably, each group of resistor divider network comprises 16 resistors, and the number of comparators is 16.
The beneficial effects are that: the four-input exclusive-or gate phase discriminator formed by adopting the current-mode logic structure has the advantages that the phase discrimination speed is high, the phase discrimination resolution is twice that of the traditional exclusive-or gate phase discriminator, the output voltage of the phase discriminator is directly input into the resistor voltage-dividing network, and compared with the traditional capacitor switch type resistor voltage-dividing network, the design circuit has the advantages of simple structure, lower load and lower power consumption, and has good application prospect.
Drawings
FIG. 1 is a schematic diagram of an exclusive OR gate phase detector constructed of a four-input current-mode logic structure of the present invention;
FIG. 2 is a schematic diagram of a pipeline comparator composed of a resistor divider network and a comparator according to the present invention.
Detailed Description
The invention will be further described with reference to the drawings and the specific examples.
The input end of the four-input exclusive-or gate phase detector is connected with two pairs of differential signals, and the output end outputs a pair of phase detector output voltages. As shown in fig. 1, the four-input exclusive-or gate phase discriminator comprises six NMOS input tubes and two resistors, wherein the six NMOS input tubes comprise an input tube M0, an input tube M1, an input tube M2, an input tube M3, an input tube M4 and an input tube M5, and the two resistors are a resistor R1 and a resistor R2; the grid electrode of the input tube M0 and the grid electrode of the input tube M3 are connected with an input signal clkp, the grid electrode of the input tube M1 and the grid electrode of the input tube M2 are connected with an input signal clkn, the grid electrode of the input tube M4 is connected with an input signal d, the grid electrode of the input tube M5 is connected with an input signal db, one end of the resistor R1 is connected with a power supply voltage, the other end of the resistor R2 is connected with the drain electrode of the input tube M1 and the drain electrode of the input tube M3, the node voltage connected with the three ends is connected with the drain electrode of the input tube M1 and the drain electrode of the input tube M4 as a phase detector output voltage voutp, the source electrodes of the input tube M2 and the input tube M3 are connected with the drain electrode of the input tube M5, and the source electrodes of the input tube M4 and the input tube M5 are grounded; the input signals clkp and clkn are a pair of differential signals, and the input signals d and db are a pair of differential signals; the phase detector output voltage voutn and the phase detector output voltage voutp are a pair of phase detector output voltages.
If the input signal d is at the high level in the first half period, the left half circuit starts to operate, if clkp is at the high level and clkn is at the low level at this time, the output voltage voutn starts to drop, voutp starts to rise, the stable value after voltage drop and rising is related to the magnitude of the phase difference between the input signals, db jumps to the high level when the input signal d jumps to the low level, the right half circuit starts to operate, if clkp is at the high level and clkn is at the low level at this time, the output voltage voutn starts to drop, voutn starts to rise, and the stable value after voltage drop and rising is related to the magnitude of the phase difference between the input signals.
The pipeline comparator comprises a first resistor voltage division network, a second resistor voltage division network and 16 comparators. As shown in fig. 2, the first resistor voltage-dividing network and the second resistor voltage-dividing network are symmetrical, each of the first resistor voltage-dividing network and the second resistor voltage-dividing network comprises two NMOS tubes and 16 resistors, the 16 resistors are connected in series between the two NMOS tubes, and the number of the resistors in the resistor voltage-dividing network is equal to that of the comparators; the output voltages of the phase discriminator are respectively connected with the input ends of the first resistor voltage dividing network and the second resistor voltage dividing network, and 16 output voltages are obtained after the first resistor voltage dividing network and the second resistor voltage dividing network divide voltages through the resistors; the 16 output voltages of the first resistor divider network are connected with the inverting input ends of the 16 comparators, the 16 output voltages of the second resistor divider network are connected with the non-inverting input ends of the 16 comparators, the output ends of the 16 comparators output state words, and the output state words are connected with subsequent digital circuits.
As shown in fig. 2, the first resistor divider network includes an NMOS transistor M6, an NMOS transistor M8, a resistor Rn1, a resistor Rn2 … …, and a resistor Rn16; the second resistor divider network comprises an NMOS tube M7, an NMOS tube M9, a resistor Rp1, a resistor Rp2 and a … … resistor Rp16; the drains of the NMOS tube M6 and the NMOS tube M7 are connected with the power supply voltage, the grid electrode of the NMOS tube M6 is connected with the output voltage voutn of the phase discriminator, the grid electrode of the NMOS tube M7 is connected with the output voltage voutp of the phase discriminator, and the grid electrodes of the NMOS tube M8 and the NMOS tube M9 are connected with the bias circuit vbias to form a constant current source. The resistor Rn1, the resistor Rn2 … …, the resistor Rn16 and the drain electrode of the NMOS tube M8 are sequentially connected from the source stage of the NMOS tube M6, and the 16 resistors divide the voltage into Vn0 and Vn1 … … Vn15; the resistor Rp1, the resistor Rp2 … … and the resistor Rp16 are sequentially connected from the source of the NMOS tube M7 to the drain of the NMOS tube M9, and the 16 resistors divide the voltage into Vp0 and Vp1 … … Vp16; the inverting input end of the comparator is connected with the voltage Vn, and the non-inverting input end of the comparator is connected with the corresponding voltage Vp. Wherein, the corresponding relation means that the inverting input end of the first comparator is connected with the voltage Vn0, and the non-inverting input end is connected with the corresponding voltage Vp0; the inverting input terminal of the first comparator is connected with the voltage Vn1, and the non-inverting input terminal is connected with the corresponding voltage Vp1 … …
The pipe width-length ratio of the NMOS pipe M6 is equal to that of the NMOS pipe M7; the pipe width-length ratio of the NMOS pipe M8 is equal to that of the NMOS pipe M9. Since the current flowing through these 16 resistors is equal because of the series connection of 16 voltage dividing resistors between the M7 source and the M9 drain, the current supplied by these two constant current sources is equal because of the equal width to length ratio of the M8 and M9 tubes, and since the width to length ratio of the M6 and M7 tubes is equal, when the input voltage voutn is equal to the voutp voltage, the output voltages Vn0 to Vn15 and Vp15 are respectively equal to the output voltages Vp15 to Vp0, and since Vp8 is equal to Vn7 and Vn7 is greater than Vn8, vp7 to Vp0 is absolutely greater than Vn15 to Vn8, and Vp7 to Vp0 is absolutely less than Vn7 to Vn0, then after 16 comparators, the output state words q15 to q8 are 8 high levels, q7 to q0 are 8 low levels. When the input voltages voutn and voutp change, the number of high and low levels in the output state words q 15-q 0 changes, the input voltages voutn and voutp of the pipeline comparator are provided by the output voltage of the phase discriminator, the output voltages voutn and voutp of the phase discriminator change along with the magnitude of the phase difference between the input signals, the magnitude of the phase difference between the input signals is finally converted into the output state word of the pipeline comparator, and the digital circuit judges the phase difference between the input signals by detecting the number of the high and low levels of the 16-bit output state word, so that the phase discrimination function is completed.
In this embodiment, the number of comparators and the number of resistors in each resistor divider network are 16, the phase is divided into 16 equal parts within 180 degrees, the phase difference between the input signals is defined as 0-16 equal parts, when the phase difference is 16 equal parts, the rising edges of the input signals are defined to be aligned with each other, and other numbers can be selected according to the needs in the actual use process, but the numbers of the comparators and the resistors in each resistor divider network are required to be kept consistent. Table 1 shows the number of high and low levels in the output state words q 15-q 0 of the pipeline comparator when the input signals have different phase differences, and Pd represents the equal number of the phase differences.
TABLE 1
Claims (1)
1. The phase detector comprises a four-input phase detector and a pipeline comparator, wherein the input end of the four-input phase detector is connected with two pairs of differential signals, and the output end of the four-input phase detector outputs a pair of phase detector output voltages; the pipeline comparator comprises a first resistor voltage-dividing network, a second resistor voltage-dividing network and a plurality of comparators, wherein the first resistor voltage-dividing network and the second resistor voltage-dividing network are symmetrical and both comprise two NMOS (N-channel metal oxide semiconductor) tubes and a plurality of resistors, the resistors are connected in series between the two NMOS tubes, and the number of the resistors in the resistor voltage-dividing network is equal to that of the comparators; the output voltages of the phase discriminator are respectively connected with the input ends of the first resistor voltage dividing network and the second resistor voltage dividing network, and the first resistor voltage dividing network and the second resistor voltage dividing network obtain a plurality of output voltages after being divided by the resistors; connecting a plurality of output voltages of the first resistor voltage dividing network with inverting input ends of a plurality of comparators, connecting a plurality of output voltages of the second resistor voltage dividing network with non-inverting input ends of a plurality of comparators, and outputting status words by output ends of the plurality of comparators;
the four-input exclusive-OR gate phase discriminator comprises six NMOS input tubes and two resistors, wherein the six NMOS input tubes comprise an input tube M0, an input tube M1, an input tube M2, an input tube M3, an input tube M4 and an input tube M5, and the two resistors are a resistor R1 and a resistor R2; the grid electrode of the input tube M0 and the grid electrode of the input tube M3 are connected with an input signal clkp, the grid electrode of the input tube M1 and the grid electrode of the input tube M2 are connected with an input signal clkn, the grid electrode of the input tube M4 is connected with an input signal d, the grid electrode of the input tube M5 is connected with an input signal db, one end of the resistor R1 is connected with a power supply voltage, the other end of the resistor R2 is connected with the drain electrode of the input tube M1 and the drain electrode of the input tube M3, the node voltage connected with the three ends is connected with the drain electrode of the input tube M1 and the drain electrode of the input tube M4 as a phase detector output voltage voutp, the source electrodes of the input tube M2 and the input tube M3 are connected with the drain electrode of the input tube M5, and the source electrodes of the input tube M4 and the input tube M5 are grounded; the input signals clkp and clkn are a pair of differential signals, and the input signals d and db are a pair of differential signals; the phase detector output voltage voutn and the phase detector output voltage voutp are a pair of phase detector output voltages;
the first resistor divider network comprises an NMOS tube M6, an NMOS tube M8, a resistor Rn1 and a resistor Rn2 … … resistor Rnt; the second resistor divider network comprises an NMOS tube M7, an NMOS tube M9, a resistor Rp1, a resistor Rp2 and a resistor Rpt … …; wherein t is the number of comparators; the drains of the NMOS tube M6 and the NMOS tube M7 are connected with power supply voltage, the grid of the NMOS tube M6 is connected with the output voltage voutn of the phase discriminator, the grid of the NMOS tube M7 is connected with the output voltage voutp of the phase discriminator, the grids of the NMOS tube M8 and the NMOS tube M9 are connected with a bias circuit, a resistor Rn1, a resistor Rn2 … … resistor Rnt and a drain of the NMOS tube M8 are sequentially connected from the source of the NMOS tube M6, t is the number of resistors in each group of resistor voltage division network, and t resistors divide the voltage into Vn0 and Vn1 … … Vnt; the resistor Rp1, the resistor Rp2 and the resistor Rpt … … are sequentially connected from the source of the NMOS tube M7 to the drain of the NMOS tube M9, and the t resistors divide the voltage into Vp0 and Vp1 … … Vpt; the inverting input end of the comparator is connected with the voltage Vn, and the non-inverting input end of the comparator is connected with the corresponding voltage Vp;
the output ends of the comparators output state words and are connected with a subsequent digital circuit;
the pipe width-length ratio of the NMOS pipe M6 is equal to that of the NMOS pipe M7; the pipe width-length ratio of the NMOS pipe M8 is equal to that of the NMOS pipe M9;
each group of resistor divider network comprises 16 resistors, and the number of comparators is 16.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810461029.8A CN108390675B (en) | 2018-05-15 | 2018-05-15 | Phase discriminator of exclusive-or gate |
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| CN201810461029.8A CN108390675B (en) | 2018-05-15 | 2018-05-15 | Phase discriminator of exclusive-or gate |
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| CN108390675B true CN108390675B (en) | 2024-02-02 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102281060A (en) * | 2011-04-02 | 2011-12-14 | 长沙景嘉微电子有限公司 | Phase discriminator circuit applied to clock data recovery |
| CN102347765A (en) * | 2010-07-26 | 2012-02-08 | 中兴通讯股份有限公司 | Clock and data recovery system, phase adjustment method and phase discriminator |
| CN102931981A (en) * | 2012-11-13 | 2013-02-13 | 苏州磐启微电子有限公司 | Ultra-low power consumption phase locked loop circuit |
| CN106849939A (en) * | 2017-01-24 | 2017-06-13 | 四川和芯微电子股份有限公司 | CMOS phase discriminators |
| CN208272955U (en) * | 2018-05-15 | 2018-12-21 | 南京德睿智芯电子科技有限公司 | A kind of XOR gate phase discriminator |
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- 2018-05-15 CN CN201810461029.8A patent/CN108390675B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347765A (en) * | 2010-07-26 | 2012-02-08 | 中兴通讯股份有限公司 | Clock and data recovery system, phase adjustment method and phase discriminator |
| CN102281060A (en) * | 2011-04-02 | 2011-12-14 | 长沙景嘉微电子有限公司 | Phase discriminator circuit applied to clock data recovery |
| CN102931981A (en) * | 2012-11-13 | 2013-02-13 | 苏州磐启微电子有限公司 | Ultra-low power consumption phase locked loop circuit |
| CN106849939A (en) * | 2017-01-24 | 2017-06-13 | 四川和芯微电子股份有限公司 | CMOS phase discriminators |
| CN208272955U (en) * | 2018-05-15 | 2018-12-21 | 南京德睿智芯电子科技有限公司 | A kind of XOR gate phase discriminator |
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