CN108389598B - Sensitive amplifier circuit clamped by phase inverter - Google Patents
Sensitive amplifier circuit clamped by phase inverter Download PDFInfo
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- CN108389598B CN108389598B CN201810251693.XA CN201810251693A CN108389598B CN 108389598 B CN108389598 B CN 108389598B CN 201810251693 A CN201810251693 A CN 201810251693A CN 108389598 B CN108389598 B CN 108389598B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
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Abstract
The invention discloses a sensitive amplifier circuit clamped by a phase inverter.A source electrode of a first PMOS transistor and a source electrode of a second PMOS transistor are connected with a power supply voltage end, and a grid electrode and a drain electrode of the first PMOS transistor are connected with a grid electrode of the second PMOS transistor and a drain electrode of a first NMOS transistor; the source electrode of the first NMOS transistor is connected with the positive end of the first voltage-controlled current source and one end of the first capacitor; the drain electrode of the second PMOS transistor is connected with the reverse input end of the first comparator and the drain electrode of the second NMOS transistor; the source electrode of the second NMOS transistor is connected with the positive end of the second voltage-controlled current source and one end of the second capacitor; the negative ends of the first voltage-controlled current source and the second voltage-controlled current source are grounded with the other ends of the first capacitor and the second capacitor; feedback voltage is input to the grids of the first NMOS transistor and the second NMOS transistor; the positive input end of the first comparator inputs a reference voltage VREF, and the output end of the first comparator is used as the output end of the circuit. The invention can increase the reading margin.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuits, in particular to a Sensitive Amplifier (SA) circuit clamped by an inverter.
Background
The sense amplifier is applied to an NVM Memory read circuit. A typical SA circuit uses an inverter as a clamp feedback circuit for the BL (drain) in read mode.
Referring to fig. 1, the conventional inverter-clamped sense amplifier circuit is composed of four PMOS transistors MP 0-MP 3, two NMOS transistors MN0, MN1, two inverters FB1, FB2, two capacitors C1, C2, two voltage-controlled current sources VD0, VD1, and a comparator CMP 1.
The sources of the PMOS transistors MP0 to MP3 are connected to the power supply voltage terminal VDD, the drain of the PMOS transistor MP0 is connected to the drain and gate of the PMOS transistor MP1, the gate of the PMOS transistor MP2, and the drain of the NMOS transistor MN0, and the node of the connection is denoted as VE. The source of the NMOS transistor MN0 is connected to the input terminal of the inverter FB1, the positive terminal of the voltage-controlled current source VD0, and one terminal of the capacitor C1; the negative terminal of the voltage-controlled current source VD0 and the other terminal of the capacitor C1 are grounded to GND. The output terminal of the inverter FB1 is connected to the gate of the NMOS transistor MN 0.
The drain of the PMOS transistor MP2 is connected to the drain of the PMOS transistor MP3, the drain of the NMOS transistor MN1, and the inverting input terminal of the comparator CMP1, and the node at which these are connected is denoted as VF.
The source of the NMOS transistor MN1 is connected to the input terminal of the inverter FB2, the positive terminal of the voltage-controlled current source VD1, and one terminal of the capacitor C2; the negative terminal of the voltage-controlled current source VD1 and the other terminal of the capacitor C2 are grounded to GND. The output terminal of the inverter FB2 is connected to the gate of the NMOS transistor MN 1.
The positive input terminal of the comparator CMP1 inputs the reference voltage VREF, and the output terminal thereof serves as the output terminal SOUT of the circuit.
The gate of the PMOS transistors MP0 and MP3 receives the ready signal PREB.
The working principle of the sensitive amplifier clamping circuit is as follows:
the circuit works in a range of 1.7V-5.5V with a larger power supply voltage VDD range; at the stabilized voltage at node VE, the reference memory cell CKDY provides a large current (equivalent to a 0 "cell) for comparison with the current of memory cell CCDY. The reference memory cell CKDY is formed by a capacitor C1 and a voltage-controlled current source VD0 in fig. 1, and the memory cell CCDY is formed by a capacitor C2 and a voltage-controlled current source VD 1.
When reading the "0" cell, the node VF voltage is high; when reading the "1" cell, the node VF voltage is low.
As shown in fig. 1, in the conventional sense amplifier circuit clamped by an inverter, in order to stabilize the voltage-controlled current sources VD0 and VD1 at about 1.2V, an inverter is generally used as a feedback circuit, such as the inverters FB1 and FB2 in fig. 1.
The sensitive amplifier circuit clamped by the inverter has the following defects: with the variation of temperature voltage and process, the range of feedback voltage can become larger, resulting in smaller margin of reading
The waveform diagram of the sense amplifier circuit clamped by the inverter is shown in fig. 2.
Disclosure of Invention
The invention aims to provide a sensitive amplifier circuit clamped by an inverter, which can increase the reading margin.
In order to solve the technical problem, the sensitive amplifier circuit clamped by the phase inverter comprises two PMOS transistors, two NMOS transistors, two voltage-controlled current sources, two capacitors and a comparator;
the source electrode of the first PMOS transistor and the source electrode of the second PMOS transistor are connected with a power supply voltage end VDD, the grid electrode and the drain electrode of the first PMOS transistor are connected with the grid electrode of the second PMOS transistor and the drain electrode of the first NMOS transistor, and the connected node is marked as VE; the source electrode of the first NMOS transistor is connected with the positive end of the first voltage-controlled current source and one end of the first capacitor; the negative end of the first voltage-controlled current source and the other end of the first capacitor are grounded;
the drain electrode of the second PMOS transistor is connected with the inverted input end of the first comparator and the drain electrode of the second NMOS transistor, and the connected node is marked as VF; the source electrode of the second NMOS transistor is connected with the positive end of the second voltage-controlled current source and one end of the second capacitor; the negative end of the second voltage-controlled current source and the other end of the second capacitor are grounded;
the gate of the first NMOS transistor and the gate of the second NMOS transistor are input with a feedback voltage FK;
the positive input end of the first comparator inputs a reference voltage VREF, and the output end of the first comparator is used as the output end SOUT of the circuit;
the feedback circuit is composed of fourth to seventh PMOS transistors, a third NMOS transistor and a fourth NMOS transistor;
the source electrode of the fourth PMOS transistor is connected with the source electrode of the fifth PMOS transistor, the drain electrode of the fourth PMOS transistor is connected with the source electrode of the sixth PMOS transistor, the drain electrode of the sixth PMOS transistor is connected with the drain electrode and the grid electrode of the third NMOS transistor, the connected node is used as a feedback voltage output end FK, and the source electrode of the third NMOS transistor is grounded GND;
the grid electrode of the fourth PMOS transistor is connected with the node VE, the grid electrode of the sixth PMOS transistor inputs a reading signal READB, and the grid electrode of the fifth PMOS transistor inputs a preparation signal PREB;
the drain electrode of the fifth PMOS transistor is connected with the source electrode of the seventh PMOS transistor, the drain electrode of the seventh PMOS transistor and the drain electrode of the fourth NMOS transistor are connected with the feedback voltage output end FK, and the source electrode of the fourth NMOS transistor is grounded GND;
the gate of the seventh PMOS transistor and the gate of the fourth NMOS transistor are connected to the positive terminal of the first voltage controlled current source.
Through simulation, the feedback voltage full PVT (voltage temperature process corner) range of the traditional sensitive amplifier circuit clamped by the inverter is 0.5V-1.4V; the feedback voltage of the improved sensitive amplifier circuit clamped by the inverter is 0.56V-1.34V, which is 120mV better than that of the sensitive amplifier circuit clamped by the traditional inverter. Therefore, the reading margin of the sensitive amplifier circuit clamped by the inverter can be increased by 120mV, and the reliability parameters of the circuit are greatly improved.
Drawings
The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
FIG. 1 is a schematic diagram of a prior art inverter clamped sense amplifier circuit;
FIG. 2 is a waveform diagram of FIG. 1;
FIG. 3 is a schematic diagram of one embodiment of an improved inverter clamped sense amplifier circuit;
FIG. 4 is a schematic diagram of an embodiment of a feedback circuit for an improved inverter clamped sense amplifier circuit;
fig. 5 is a waveform diagram of fig. 3 and 4.
Detailed Description
Referring to fig. 3, the improved inverter-clamped sense amplifier circuit in the following embodiment is composed of PMOS transistors MP1 and MP2, NMOS transistors MN0 and MN1, voltage-controlled current sources VD0 and VD1, capacitors C1 and C2, and a comparator CMP 1.
The source of the PMOS transistor MP1 and the source of the PMOS transistor MP2 are connected to the power supply voltage terminal VDD, the gate and the drain of the PMOS transistor MP1 are connected to the gate of the PMOS transistor MP2, and the node of the connection is denoted as VE.
The drain of the NMOS transistor MN0 is connected to the node VE, the source thereof is connected to the positive terminal of the voltage-controlled current source VD0 and one end of the capacitor C1, and the negative terminal of the voltage-controlled current source VD0 and the other end of the capacitor C1 are grounded.
The drain of the PMOS transistor MP2 is connected to the inverting input terminal of the comparator CMP1, and the node at which it is connected is denoted as VF.
The drain MN1 of the NMOS transistor is connected with the node VF, and the source of the NMOS transistor is connected with the positive terminal of a voltage-controlled current source VD1 and one end of a capacitor C2; the negative terminal of the voltage-controlled current source VD1 and the other terminal of the capacitor C2 are grounded.
The gate of the NMOS transistor MN0 and the gate of the NMOS transistor MN1 input the feedback voltage FK.
The positive input terminal of the comparator CMP1 inputs the reference voltage VREF, and the output terminal thereof serves as the output terminal SOUT of the circuit.
Referring to fig. 4, the feedback circuit of the inverter-clamped sense amplifier circuit is composed of PMOS transistors MP 4-MP 7, NMOS transistors MN3, MN 4.
The sources of the PMOS transistors MP4 and MP5 are connected, the drain of the PMOS transistor MP4 is connected to the source of the PMOS transistor MP6, the drain of the PMOS transistor MP6 is connected to the drain and gate of the NMOS transistor MN3, and the node of the connection serves as the feedback voltage output end FK. The source of the NMOS transistor MN3 is grounded GND.
The gate of the PMOS transistor MP4 is connected to the node VE, and the gate of the PMOS transistor MP6 receives the read signal READB. The gate of the PMOS transistor MP5 inputs the ready signal PREB.
The drain of the PMOS transistor MP5 is connected to the source of the PMOS transistor MP7, the drain of the PMOS transistor MP7 and the drain of the NMOS transistor MN4 are connected to the feedback voltage output terminal FK, and the source of the NMOS transistor MN4 is connected to the ground GND.
The gate of the PMOS transistor MP7 and the gate of the NMOS transistor MN4 are connected to the positive terminal of the voltage controlled current source VD 0.
As shown in FIGS. 3 and 4, the new feedback circuit is applied to a sensitive amplifier circuit clamped by an inverter, and the voltage-controlled current sources VD0 and VD1 have smaller variation range than that of a single inverter along with the variation of temperature voltage and process angle, so that the read margin is increased. The present invention eliminates the conventional transistors (PM0, PM3) used for precharging because it takes a lot of time for the voltage at the precharge node VF to reach 5.5V and then to drop to about 2V when the power supply voltage VDD is 5.5V. Eliminating transistors (PM0, PM3) saves time when compared to the reference voltage VREF.
As shown in fig. 4, when PREB is low, the feedback voltage FK is high, and the voltage at the node VE is stable; after PREB is finished, the sense amplifier circuit clamped by the inverter enters a comparison working state, the PMOS transistor MP5 is turned off, and the current flowing through the PMOS transistors MP4 and MP6 is stabilized as the current of the reference memory cell CKDY.
The NMOS transistor MN3 functions to ensure that the feedback voltage does not pull down to zero, resulting in the NMOS transistors MN0, MN1 turning off completely.
The stable current provided by the reference memory cell CKDY charges and discharges MN4, so that the voltage variation range of the BL (drain) in the read mode can be reduced, and the read margin can be increased.
In the embodiment shown in fig. 3, the reference memory cell CKDY is formed by a capacitor C1 and a voltage controlled current source VD0, and the memory cell CCDY is formed by a capacitor C2 and a voltage controlled current source VD 1.
Fig. 5 is a waveform diagram of fig. 3 and 4, particularly illustrating the timing sequence to be followed for the function of a sense amplifier circuit implementing the improved inverter clamping of the present invention.
The present invention has been described in detail with reference to the specific embodiments, but these are not to be construed as limiting the invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (4)
1. A phase inverter clamped sense amplifier circuit, comprising: the circuit consists of two PMOS transistors, two NMOS transistors, two voltage-controlled current sources, two capacitors and a comparator;
the source electrode of the first PMOS transistor and the source electrode of the second PMOS transistor are connected with a power supply voltage end VDD, the grid electrode and the drain electrode of the first PMOS transistor are connected with the grid electrode of the second PMOS transistor and the drain electrode of the first NMOS transistor, and the connected node is marked as VE; the source electrode of the first NMOS transistor is connected with the positive end of the first voltage-controlled current source and one end of the first capacitor; the negative end of the first voltage-controlled current source and the other end of the first capacitor are grounded;
the drain electrode of the second PMOS transistor is connected with the inverted input end of the first comparator and the drain electrode of the second NMOS transistor, and the connected node is marked as VF; the source electrode of the second NMOS transistor is connected with the positive end of the second voltage-controlled current source and one end of the second capacitor; the negative end of the second voltage-controlled current source and the other end of the second capacitor are grounded;
the grid electrode of the first NMOS transistor and the grid electrode of the second NMOS transistor are used for inputting feedback voltage;
the positive input end of the first comparator inputs a reference voltage VREF, and the output end of the first comparator is used as the output end SOUT of the circuit;
the feedback circuit is composed of fourth to seventh PMOS transistors, a third NMOS transistor and a fourth NMOS transistor;
the source electrode of the fourth PMOS transistor is connected with the source electrode of the fifth PMOS transistor, the drain electrode of the fourth PMOS transistor is connected with the source electrode of the sixth PMOS transistor, the drain electrode of the sixth PMOS transistor is connected with the drain electrode and the grid electrode of the third NMOS transistor, the connected node is used as a feedback voltage output end FK, and the source electrode of the third NMOS transistor is grounded GND;
the grid electrode of the fourth PMOS transistor is connected with the node VE, the grid electrode of the sixth PMOS transistor inputs a reading signal READB, and the grid electrode of the fifth PMOS transistor inputs a preparation signal PREB;
the drain electrode of the fifth PMOS transistor is connected with the source electrode of the seventh PMOS transistor, the drain electrode of the seventh PMOS transistor and the drain electrode of the fourth NMOS transistor are connected with the feedback voltage output end FK, and the source electrode of the fourth NMOS transistor is grounded GND;
the gate of the seventh PMOS transistor and the gate of the fourth NMOS transistor are connected to the positive terminal of the first voltage controlled current source.
2. The sense amplifier circuit of claim 1, wherein; when the ready signal PREB is low, the feedback voltage FK is high, and the voltage at the node VE is stable; after the preparation signal PREB is ended, the sense amplifier circuit enters a comparison working state, the fifth PMOS transistor is turned off, and the current flowing through the fourth PMOS transistor and the sixth PMOS transistor is stabilized as the reference memory cell current.
3. The sense amplifier circuit of claim 2, wherein; the fourth NMOS transistor is charged and discharged by the stable current provided by the reference storage unit, so that the voltage variation range of the drain electrode in a reading mode can be reduced, and the reading allowance can be increased.
4. The sense amplifier circuit of claim 1, wherein; the third NMOS transistor ensures that the feedback voltage FK is not pulled down to zero, which results in the first and second NMOS transistors being completely turned off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810251693.XA CN108389598B (en) | 2018-03-26 | 2018-03-26 | Sensitive amplifier circuit clamped by phase inverter |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810251693.XA CN108389598B (en) | 2018-03-26 | 2018-03-26 | Sensitive amplifier circuit clamped by phase inverter |
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| CN108389598A CN108389598A (en) | 2018-08-10 |
| CN108389598B true CN108389598B (en) | 2020-09-29 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113327636B (en) * | 2020-02-28 | 2024-01-26 | 中芯国际集成电路制造(上海)有限公司 | Sense amplifier |
| CN111383674B (en) * | 2020-03-05 | 2023-08-22 | 上海华虹宏力半导体制造有限公司 | Sense amplifier for compensating SONOS memory |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1637951A (en) * | 2003-12-26 | 2005-07-13 | 夏普株式会社 | Semiconductor readout circuit |
| CN101777374A (en) * | 2010-01-12 | 2010-07-14 | 上海宏力半导体制造有限公司 | Readout amplifier with process and current compensation |
| CN103208304A (en) * | 2012-01-13 | 2013-07-17 | 北京兆易创新科技股份有限公司 | Current comparator circuit of reading circuit |
| WO2015042752A1 (en) * | 2013-09-30 | 2015-04-02 | Atmel Corporation | Sense amplifier |
| CN105741871A (en) * | 2016-03-11 | 2016-07-06 | 上海华虹宏力半导体制造有限公司 | Sensitive amplifying circuit and memory |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1637951A (en) * | 2003-12-26 | 2005-07-13 | 夏普株式会社 | Semiconductor readout circuit |
| CN101777374A (en) * | 2010-01-12 | 2010-07-14 | 上海宏力半导体制造有限公司 | Readout amplifier with process and current compensation |
| CN103208304A (en) * | 2012-01-13 | 2013-07-17 | 北京兆易创新科技股份有限公司 | Current comparator circuit of reading circuit |
| WO2015042752A1 (en) * | 2013-09-30 | 2015-04-02 | Atmel Corporation | Sense amplifier |
| CN105741871A (en) * | 2016-03-11 | 2016-07-06 | 上海华虹宏力半导体制造有限公司 | Sensitive amplifying circuit and memory |
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