CN108388721B - SOI NMOS total dose radiation multi-bias point current model modeling method - Google Patents

SOI NMOS total dose radiation multi-bias point current model modeling method Download PDF

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CN108388721B
CN108388721B CN201810130075.XA CN201810130075A CN108388721B CN 108388721 B CN108388721 B CN 108388721B CN 201810130075 A CN201810130075 A CN 201810130075A CN 108388721 B CN108388721 B CN 108388721B
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陈静
许灵达
柴展
王硕
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Shanghai Institute of Microsystem and Information Technology of CAS
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Abstract

The invention provides a modeling method of an SOI NMOS total dose radiation multi-bias point current model, which comprises the following steps: obtaining transfer characteristic data of the SOI NMOS side wall transistor under different drain terminal biases and transfer characteristic data under different dose irradiation and different drain terminal biases through testing; screening data and extracting parameters; introducing a threshold voltage model of a leakage induced barrier reduction effect, a threshold voltage offset model of a radiation effect and an equivalent grid voltage model of a total dose radiation effect of the sidewall transistor into a sidewall transistor current model, and correcting an equivalent zero offset threshold voltage of the total dose radiation effect; and forming an SOI NMOS total dose radiation current model. The invention is suitable for total dose radiation simulation under different drain terminal bias voltages; the transfer characteristic curves of the SOI NMOS under different drain terminal biases under the influence of the total dose radiation effect can be more accurately fitted, and the method is more suitable for the total dose radiation effect simulation of an integrated circuit.

Description

SOI NMOS total dose radiation multi-bias point current model modeling method
Technical Field
The invention relates to the field of total dose radiation research, in particular to a modeling method of an SOI NMOS total dose radiation multi-bias point current model.
Background
With the development of aerospace technology, a large number of aerospace electronic devices are being deployed in a space environment. Without atmospheric protection, electronic devices are susceptible to cosmic rays in space, producing radiation-related effects such as single-event effects, transient radiation effects, total dose effects, and the like. Studies have shown that the total dose radiation effect degrades the electrical performance of MOS and two-terminal devices, thereby affecting the operating state of the overall circuit. Therefore, the radiation-resistant reinforced design becomes a big hotspot of circuit design in the aerospace field.
The Silicon-on-Insulator (SOI) technology has the advantages of small parasitic capacitance, low power consumption and single event effect resistance due to the introduction of the dielectric isolation formed by the buried oxide layer, and is widely applied to the radiation-resistant reinforcement design. In the SOI MOSFET, a parasitic structure similar to that of the bulk silicon MOSFET exists, and Shallow Trench Isolation (STI) is widely used as a device isolation technology in the SOI MOSFET because of its high integration and high gain. However, in actual processes, the sidewall gate terminal will have a partial extension, and the partial extension gate will generate a parasitic current from the drain terminal to the source terminal in the MOS device due to the edge effect.
Research shows that the leakage of the edge parasitic transistor caused by the total dose radiation effect is the main mechanism of the failure of the EEPROM circuit and the decline of the operational amplifier performance in the deep submicron process. For many high-performance analog circuits and radiation-resistant circuits, the cost of repeatedly carrying out radiation experiments on the circuits in the radiation-resistant circuit design can be greatly reduced and the development period of the radiation-resistant circuit can be shortened by establishing the STI sidewall transistor current model with the total dose radiation effect.
Therefore, modeling the STI sidewall transistor current with total dose radiation effect has become one of the problems to be solved by those skilled in the art.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a modeling method for a SOI NMOS total dose radiation multi-bias point current model, which is used to solve the problems of high total dose radiation effect research cost, long period, etc. in the prior art.
In order to achieve the above and other related objects, the present invention provides a SOI NMOS total dose radiation multi-bias point current model modeling method, which at least includes:
obtaining transfer characteristic data of the SOI NMOS side wall transistor under different drain terminal biases through testing;
obtaining transfer characteristic data of the SOI NMOS transistor under different dose irradiation and different drain terminal bias through testing;
screening transfer characteristic data of the SOI NMOS side wall transistor under different drain terminal biases and data obtained from the transfer characteristic data of the SOI NMOS side wall transistor under different dosage irradiation and different drain terminal biases, eliminating the data obtained under the condition that the transistor is damaged, and extracting parameters based on the screened data;
obtaining a sidewall transistor current model according to the transistor current model, and introducing a threshold voltage model of a leakage induced barrier reduction effect and a threshold voltage offset model of a radiation effect into the sidewall transistor current model to obtain a sidewall transistor total dose radiation current model;
introducing an equivalent grid voltage model of the total dose radiation effect of the side wall transistor based on a commercial SOI NMOS model and the total dose radiation current model of the side wall transistor, correcting the equivalent zero-bias threshold voltage of the total dose radiation effect, and extracting radiation parameters of the side wall equivalent transistor;
and combining the commercial SOI NMOS model and the sidewall transistor total dose radiation current model to form an SOI NMOS total dose radiation current model.
Preferably, the step of obtaining transfer characteristic data of the SOI NMOS sidewall transistor under different drain terminal biases comprises:
providing an SOI NMOS side wall transistor, respectively providing different drain terminal bias voltages for the SOI NMOS side wall transistor, changing a gate test voltage applied to a side wall gate terminal of the SOI NMOS side wall transistor under each drain terminal bias voltage to obtain corresponding drain terminal current, and further obtaining the corresponding relation between the gate voltage and drain current under different drain terminal biases.
Preferably, the step of acquiring transfer characteristic data of the SOI NMOS transistor under different dose irradiation and different drain bias includes:
the method comprises the steps of irradiating SOI NMOS transistors with different doses, respectively providing different drain terminal bias voltages for the SOI NMOS transistors after irradiation, changing a gate test voltage applied to a gate terminal of the SOI NMOS transistor under each drain terminal bias voltage to obtain corresponding drain terminal currents, and further obtaining transfer characteristic data under different dose irradiation and different drain terminal biases.
More preferably, the radiation source is X-rays; the irradiation bias condition is that the grid end voltage of a main transistor of the SOI NMOS side wall transistor is 3.3V; the drain terminal voltage, the source terminal voltage, the body terminal voltage and the substrate voltage are grounded.
Preferably, the sidewall transistor current model satisfies the following relation:
Figure BDA0001574661980000021
wherein, Ids,sIs the leakage current of the sidewall transistor, musIs the carrier mobility, ε, of a sidewall transistoroxIs the dielectric coefficient of silicon dioxide, theta is the angle between the side wall gate terminal and the surface of the side wall transistor, L is the channel length of the main transistor, and V isgsteff,sIs the effective overdrive voltage, V, of the sidewall transistordseff,sIs the effective drain voltage of the sidewall transistor, AbulkIs a bulk charge factor, vtIs a thermal voltage. More preferably, the threshold voltage after introducing the threshold voltage model of the drain induced barrier lowering effect satisfies the following relationship:
Vth,s1＝Vth0,s-DIBL,sVds，
wherein, V th,s1 is the threshold voltage after the threshold voltage model of the drain induced barrier lowering effect is introduced, Vth0,sDIBL, which is the equivalent zero bias threshold voltage of the total dose radiation effect,sFor the leakage induced barrier lowering effect parameter, VdsIs the drain voltage of the main transistor.
More preferably, the threshold voltage after introducing the threshold voltage shift model of the radiation effect satisfies the following relation:
Vth,s2＝Vth0,s-ΔVth,s，
Figure BDA0001574661980000031
wherein, V th,s2 is the threshold voltage after the threshold voltage shift model introducing the radiation effect, Vth0,sEquivalent zero offset threshold for total dose radiation effectVoltage, Δ Vth,sIs a threshold voltage shift model of the radiation effect, k1For radiation-dependent overall coefficients, q is the charge constant, g0Number of electron-hole pairs, t, generated by the absorption of 1rad (SiO2) energy per unit mass of SiO2oxIs the thickness of the gate oxide layer, epsilonoxIs the dielectric coefficient of silicon dioxide, D is the total dose of radiation, and τ is the charge distribution coefficient.
More preferably, the equivalent gate voltage model of the total dose radiation effect of the sidewall transistor satisfies the following relationship:
Vgs,s＝αVgs，
wherein, Vgs,sIs the equivalent gate voltage of the total dose radiation effect of the sidewall transistor, alpha is a correction factor, VgsIs the gate voltage of the main transistor.
Preferably, a sidewall transistor current model of a threshold voltage model introducing a drain induced barrier reduction effect is introduced into parameter extraction software to extract SOI sidewall transistor parameters, wherein the parameters comprise one or more of carrier mobility, gate oxide thickness, drain induced barrier reduction effect parameters and sub-threshold slope of the sidewall transistor.
Preferably, the radiation parameter includes one or both of a total radiation dose or a charge distribution coefficient.
As described above, the SOI NMOS total dose radiation multi-bias point current model modeling method of the present invention has the following beneficial effects:
the SOI NMOS total dose radiation multi-bias point current model modeling method establishes the side wall transistor total dose radiation effect current model suitable for different biases by researching the current characteristics of an STI side wall transistor under the commercial process condition of 0.13 mu m PD SOICMOS and combining the principle of MOS electric leakage caused by the total dose radiation effect.
Drawings
Fig. 1 is a schematic top view of a prior art SOI transistor.
Fig. 2 shows a schematic AA' cross-sectional view of a prior art SOI transistor.
FIG. 3 is a flow chart of the SOI NMOS total dose radiation multi-bias point current model modeling method of the present invention.
Fig. 4 is a graph showing transfer characteristic data versus sidewall transistor simulation curves for different drain bias.
Fig. 5 is a schematic diagram showing comparison between transfer characteristic data under different irradiation doses and simulation curves of a sidewall transistor and an SOI NMOS transistor when drain bias voltage is 0.1V.
Fig. 6 is a schematic diagram showing the comparison between the transfer characteristic data under different irradiation doses and the simulation curves of the sidewall transistor and the SOI NMOS transistor when the drain bias voltage is 3.3V.
FIG. 7 is a schematic diagram showing input ports and parameter settings for tuning parameters up in IC-CAP modeling software.
Description of the element reference numerals
1 SOI transistor
11 source end
12 drain terminal
13 Main grid
14 side wall gate terminal
15 main transistor
16 sidewall transistor
17 corner transistor
18 body region
191 gate oxide layer
192 shallow trench isolation
S1-S6
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 6. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
A complete sidewall transistor total dose radiation effect current model is established, and the current characteristics of the sidewall transistor are firstly researched. Fig. 1 is a schematic top view of an SOI transistor, wherein a source terminal 11 and a drain terminal 12 are respectively disposed at two sides of a main gate 13, a sidewall gate terminal 14 extends from the source terminal 11 and the drain terminal 12 along the main gate 13, a sidewall transistor 15 is formed on sidewalls of the source terminal 11 and the drain terminal 12, and a current characteristic curve test of the sidewall transistor is possible by adding a polysilicon gate terminal on the sidewall. The main transistor 15 is formed by the upper surfaces of the main gate 13, the gate oxide layer 191 and the body region 18, the sidewall gate terminal 14, the shallow trench isolation 192 and the sidewall of the body region 18 form the sidewall transistor 16 on both sides of the main transistor 15, the included angle between the sidewall gate terminal 14 and the sidewall is theta, the corner of the main transistor 15 and the sidewall transistor 16 is also formed with the corner transistor 17, and the cross section is as shown in fig. 2.
Under 0.13 μm SOI CMOS process conditions, the gate oxide layer thickness of the IO device main transistor is only 6.5 nanometers, while the STI layer typically has an equivalent gate oxide thickness of about tens to hundreds of nanometers. Therefore, the threshold voltage of the sidewall transistor is much greater than the threshold voltage of the main transistor. The current model formula of a normal transistor is obtained according to a model manual of BSIM SOI4.2 as follows:
Figure BDA0001574661980000051
Figure BDA0001574661980000052
wherein, IdsFor leakage current, μ is the carrier mobility,
Figure BDA0001574661980000053
is the width-to-length ratio of the device, VgsteffFor effective overdrive voltage, VdseffFor effective drain voltage, AbulkIs a bulk charge factor, vtIs a thermal voltage.
Example one
As shown in fig. 3, the present invention provides a SOI NMOS total dose radiation multi-bias point current model modeling method, which includes:
step S1: and obtaining transfer characteristic data of the SOI NMOS side wall transistor under different drain terminal biases through testing.
Specifically, providing an SOI NMOS sidewall transistor, providing different drain terminal bias voltages to the SOI NMOS sidewall transistor, and changing a gate test voltage applied to a sidewall gate terminal of the SOI NMOS sidewall transistor under each drain terminal bias voltage to obtain a corresponding drain terminal current, thereby obtaining a corresponding relationship between a gate voltage and a drain current under different drain terminal biases.
More specifically, as shown in fig. 4, in this embodiment, the width-to-length ratio W/L of the SOI NMOS sidewall transistor is 0.15 μm/0.35 μm, a first drain bias voltage (0.1V), a second drain bias voltage (1.7V), and a third drain bias voltage (3.3V) are respectively applied to the drain of the SOI NMOS sidewall transistor, and a test value (each data point in fig. 4) of the correspondence relationship between the gate voltage and the drain current is obtained at each bias voltage, corresponding to three sets of data in fig. 4, where the left three sets of data correspond to the left logarithmic ordinate; the right three groups of data correspond to a right linear ordinate; the data on both sides are identical, only the coordinates are transformed.
It should be noted that, in practical applications, the size of the SOI NMOS sidewall transistor, the value and the number of the drain bias voltage may be set according to needs, and are not limited to this embodiment.
Step S2: and obtaining transfer characteristic data of the SOI NMOS transistor under different dose irradiation and different drain terminal bias through testing.
Specifically, in order to establish an SOI NMOS total dose radiation current model, a total dose irradiation test experiment is designed in this embodiment, different doses are irradiated on SOI NMOS transistors (main transistor + sidewall transistor), different drain bias voltages are respectively provided for the SOI NMOS transistors after irradiation, and a gate test voltage applied to a gate terminal of the SOI NMOS transistor is changed under each drain bias voltage to obtain a corresponding drain current, so as to obtain transfer characteristic data under different doses of irradiation and different drain biases.
More specifically, as shown in fig. 5 and 6, in the present embodiment, the total dose test employs a 0.13 μm SOI CMOS process and a T-gate body-contacted NMOS IO device, and the width-to-length ratio W/L of the NMOS IO device is 0.13 μm/0.35 μm. The radiation source adopts an X-ray source of the american van der bauer university, the irradiation device adopts the worst ON bias (i.e., gate terminal voltage Vg is 3.3V, drain terminal voltage Vd is source terminal voltage Vs is body terminal voltage Vb is substrate voltage Vsub is GND), a first dose point 50krad (si), a second dose point 100krad (si), a third dose point 150krad (si) and a fourth dose point 200krad (si) are respectively selected, after irradiation, a fourth drain terminal bias voltage (0.1V) and a fifth drain terminal bias voltage (3.3V) are respectively applied to the drain terminal of the SOI NMOS transistor, and a test value of the corresponding relationship between the gate voltage and the drain current (each data point in fig. 5 and fig. 6) is obtained under each bias voltage to be compared with data before irradiation.
Step S3: and screening the data obtained in the steps S1 and S2, removing the data obtained under the condition that the SOI NMOS side wall transistor is damaged, and extracting parameters based on the screened data.
Specifically, the whole set of data of the smooth curve obtained after the data of each set of data in fig. 4, 5 and 6 are connected is reserved, and the whole set of data with the trip point is deleted, so as to ensure that the SOI NMOS transistor for testing is complete (no damage or breakdown occurs) and the data is accurate; and importing the screened data into parameter extraction software.
Step S4: obtaining a sidewall transistor current model according to the transistor current model, introducing a threshold voltage model of a leakage induced barrier reduction effect and a threshold voltage offset model of a radiation effect into the sidewall transistor current model, introducing an equivalent gate voltage model of a sidewall transistor total dose radiation effect, correcting an equivalent zero offset threshold voltage of the total dose radiation effect, and fitting to obtain the sidewall transistor total dose radiation current model.
Specifically, step S41: obtaining a sidewall transistor current model according to the formula (1), and satisfying the following relational expression:
Figure BDA0001574661980000071
Figure BDA0001574661980000072
wherein, Ids,sIs the leakage current of the sidewall transistor, musIs the carrier mobility, ε, of a sidewall transistoroxIs the dielectric coefficient of silicon dioxide, theta is the angle between the side wall gate terminal and the surface of the side wall transistor, L is the channel length of the main transistor, and V isgsteff,sIs the effective overdrive voltage, V, of the sidewall transistordseff,sIs the effective drain voltage of the sidewall transistor, AbulkIs a bulk charge factor, vtIs a thermal voltage. Equivalent gate oxide thickness t of sidewall transistorox,sSatisfy tox,s(x) θ W. To simplify the relationship, in the present embodiment, Vgsteff≈Vgs,s-Vth,s。
Specifically, step S42: the sidewall transistor has a larger gate oxide voltage (about 21V) and a more gradual subthreshold slope due to the thicker equivalent gate oxide thickness. The Drain Induced Barrier Lowering (DIBL) effect present in the sidewall transistors is superimposed into the main transistor under the total dose radiation. Therefore, the DIBL effect is introduced by modifying the threshold voltage, satisfying the following relationship:
V th,s1＝Vth0,s-DIBL,sVds (5)
wherein, V th,s1 is the threshold voltage after the threshold voltage model of the drain induced barrier lowering effect is introduced, Vth0,sDIBL, which is the equivalent zero bias threshold voltage of the total dose radiation effect,sFor the leakage induced barrier lowering effect parameter, VdsIs the drain voltage of the main transistor. As shown in fig. 4, the simulated value of the corresponding relationship curve between the gate voltage and the drain current of the sidewall transistor current model after the drain induced barrier lowering effect is introduced and the transfer characteristic data under different drain terminal biases obtained by the test are well fitted. Then introducing the Verilog-A sidewall transistor model after the drain induced barrier lowering effect into parameter extraction software to extract sidewall transistor parameters including but not limited to the carrier mobility mu of the sidewall transistorsGate oxide layer thickness tox,sLeakage induced barrier lowering effect parameter DIBL,sAnd one or more of sub-threshold slope, which is not limited in this embodiment.
Specifically, step S43: with the reduction of the process size, the thickness of the gate oxide is continuously thinned, and for a 0.13-micron PD SOI CMOS commercial process, the total dose radiation leakage of the STI side wall transistor is a main factor generated by the off-state leakage current of the SOI transistor total dose radiation effect, and the leakage influence of corners and front and rear gates is small. Radiation causes a large amount of fixed positive charge to be introduced into the STI, resulting in a reduction in the threshold voltage of the sidewall transistor; after a certain dose, the threshold voltage will saturate and will not continue to shift negatively due to the positive charge traps in the oxide layer. Therefore, a threshold voltage shift model of the radiation effect is introduced to obtain a sidewall transistor total dose current model, and the following relation is satisfied:
V th,s2＝Vth0,s-ΔVth,s (6)
Figure BDA0001574661980000081
wherein, V th,s2 is the threshold voltage after the threshold voltage shift model introducing the radiation effect, Vth0,sEquivalent zero bias threshold voltage, Δ V, for total dose radiation effectth,sIs a threshold voltage shift model of the radiation effect, k1For radiation-dependent overall coefficients, q is the charge constant, g0Number of electron-hole pairs, t, generated by the absorption of 1rad (SiO2) energy per unit mass of SiO2oxIs the thickness of the gate oxide layer, epsilonoxIs the dielectric coefficient of silicon dioxide, D is the total dose of radiation, and τ is the charge distribution coefficient. Combining equation (5) and equation (6) yields the full sidewall transistor threshold voltage:
Vth,s＝Vth0,s-DIBL,sVds-ΔVth,s (8)
and introducing the threshold voltage of the complete sidewall transistor to obtain a sidewall transistor total dose radiation current model.
Step S5: and introducing an equivalent grid voltage model of the total dose radiation effect of the side wall transistor based on a commercial SOI NMOS model and the total dose radiation current model of the side wall transistor, correcting the equivalent zero-bias threshold voltage of the total dose radiation effect, and extracting the radiation parameters of the side wall equivalent transistor.
Specifically, a commercial SOI model and a sidewall transistor total dose radiation current model are introduced into parameter extraction software, the whole modeling parameter adjustment process is performed on IC-CAP modeling software, corresponding input ports and parameter settings are shown in fig. 7, and different dose points can be set in input parameters for simulation fitting. Based on the transfer characteristic data of the SOI NMOS transistor under different drain terminal biases in fig. 5 and fig. 6, it is found that the equivalent threshold voltage before the radiation of the total dose radiation effect of the sidewall transistor is about 2V, which is much smaller than the threshold voltage of the sidewall transistor test data, in the parameter adjusting process, mainly because the STI sidewall oxide layer is thick, the sidewall gate voltage is not vertically applied to the sidewall channel, and the positive charge generated by the radiation effect is in the STI oxide layer, so that the parameter α needs to be introduced to obtain the equivalent gate voltage of the total dose radiation effect of the sidewall transistor, and the following relationship is satisfied:
Vgs,s＝αVgs (9)
wherein, Vgs,sIs the equivalent gate voltage of the total dose radiation effect of the sidewall transistor, alpha is a correction factor, VgsIs the gate voltage of the main transistor. Equivalent zero-bias threshold voltage V for simultaneous correction of total dose radiation effectth0,s. Adjusting the carrier mobility μsAdjusting the current maximum to be of the same order as the saturation leakage current by adjusting the threshold voltage shift k with respect to the total dose1(integrated coefficients related to radiation) and τ (charge distribution coefficient) are fitted to the leakage current intervals for the different dose points. As shown in fig. 5 and 6, the simulated values of the corresponding relationship curves of gate voltage and drain current of the commercial SOI model and the reference-adjusted back-side-wall transistor total dose radiation current model and the transfer characteristic data under different drain terminal biases obtained by the test are well fitted. Radiation parameters of the sidewall equivalent transistor, including but not limited to total radiation dose D, charge distribution coefficient tau, and radiation dependent integral coefficient k, are then extracted1One or two of them, not limited to this embodiment. The Hspice simulation results of the total dose radiation effect current model of the finally obtained sidewall transistor are shown by dotted lines in fig. 5 and 6.
Step S6: and combining the commercial SOI NMOS model and the sidewall transistor total dose radiation current model to form an SOI NMOS total dose radiation current model.
It should be noted that the specific operation steps listed in this embodiment are only an example, and the order may be changed as needed without affecting the implementation of the method, and the present embodiment is not limited thereto.
Example two
The present embodiment provides a modeling method for SOI NMOS total dose radiation multi-bias point current model, which is different from the first embodiment in that step S1, step S3, step S4, step S2, step S3, step S5, and step S6 are sequentially performed. The detailed description of the embodiments is not repeated herein.
The SOI NMOS total dose radiation multi-bias point current model established by combining the current characteristic of the side wall transistor and the total dose radiation effect mechanism can more accurately fit the transfer characteristic curve of the SOI NMOS under different drain terminal biases when the SOI NMOS is influenced by the total dose radiation effect, and is more suitable for the total dose radiation effect simulation of an integrated circuit.
In summary, the present invention provides a SOI NMOS total dose radiation multi-bias point current model modeling method, including: obtaining transfer characteristic data of the SOI NMOS side wall transistor under different drain terminal biases through testing; obtaining transfer characteristic data of the SOI NMOS transistor under different dose irradiation and different drain terminal bias through testing; screening transfer characteristic data of the SOI NMOS side wall transistor under different drain terminal biases and data obtained from the transfer characteristic data of the SOI NMOS side wall transistor under different dosage irradiation and different drain terminal biases, eliminating the data obtained under the condition that the transistor is damaged, and extracting parameters based on the screened data; obtaining a sidewall transistor current model according to the transistor current model, and introducing a threshold voltage model of a leakage induced barrier reduction effect and a threshold voltage offset model of a radiation effect into the sidewall transistor current model to obtain a sidewall transistor total dose radiation current model; introducing an equivalent grid voltage model of the total dose radiation effect of the side wall transistor based on a commercial SOI NMOS model and the total dose radiation current model of the side wall transistor, correcting the equivalent zero-bias threshold voltage of the total dose radiation effect, and extracting radiation parameters of the side wall equivalent transistor; and combining the commercial SOI NMOS model and the sidewall transistor total dose radiation current model to form an SOI NMOS total dose radiation current model. The invention is suitable for total dose radiation simulation under different drain terminal bias voltages; the method adopts a sidewall transistor separation modeling mode, fully considers the DIBL effect of the sidewall transistor, and realizes the difference of different total dose radiation influences under different drain end biases; the transfer characteristic curves of the SOI NMOS under different drain terminal biases under the influence of the total dose radiation effect can be more accurately fitted, and the method is more suitable for the total dose radiation effect simulation of an integrated circuit. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. An SOI NMOS total dose radiation multi-bias point current model modeling method is characterized by at least comprising the following steps:
obtaining transfer characteristic data of the SOINMOS side wall transistor under different drain terminal biases through testing;
obtaining transfer characteristic data of the SOINMOS transistor under different dose irradiation and different drain terminal bias through testing;
screening transfer characteristic data of the SOI NMOS side wall transistor under different drain terminal biases and data obtained from the transfer characteristic data of the SOINMOS transistor under different dosage irradiation and different drain terminal biases, eliminating the data obtained under the condition that the transistor is damaged, and extracting parameters based on the screened data;
obtaining a sidewall transistor current model according to the transistor current model, and introducing a threshold voltage model of a leakage induced barrier reduction effect and a threshold voltage offset model of a radiation effect into the sidewall transistor current model to obtain a sidewall transistor total dose radiation current model;
introducing an equivalent grid voltage model of the total dose radiation effect of the side wall transistor based on a commercial SOI NMOS model and the total dose radiation current model of the side wall transistor, correcting the equivalent zero-bias threshold voltage of the total dose radiation effect, and extracting radiation parameters of the side wall equivalent transistor;
and combining the commercial SOI NMOS model and the sidewall transistor total dose radiation current model to form an SOINMOS total dose radiation current model.
2. The SOINMOS total dose radiation multi-bias point current model modeling method of claim 1, wherein: the step of acquiring the transfer characteristic data of the SOINMOS side wall transistor under different drain terminal biases comprises the following steps:
providing an SOI NMOS side wall transistor, respectively providing different drain terminal bias voltages for the SOI NMOS side wall transistor, changing a gate test voltage applied to a side wall gate terminal of the SOI NMOS side wall transistor under each drain terminal bias voltage to obtain corresponding drain terminal current, and further obtaining the corresponding relation between the gate voltage and drain current under different drain terminal biases.
3. The SOINMOS total dose radiation multi-bias point current model modeling method of claim 1, wherein: the method for acquiring the transfer characteristic data of the SOINMOS transistor under different dose irradiation and different drain terminal bias comprises the following steps:
the method comprises the steps of irradiating SOI NMOS transistors with different doses, respectively providing different drain terminal bias voltages for the SOI NMOS transistors after irradiation, changing a gate test voltage applied to a gate terminal of the SOI NMOS transistor under each drain terminal bias voltage to obtain corresponding drain terminal currents, and further obtaining transfer characteristic data under different dose irradiation and different drain terminal biases.
4. The SOINMOS total dose radiation multi-bias point current model modeling method of claim 3, wherein: the radiation source is X-ray; the irradiation bias condition is that the grid end voltage of a main transistor of the SOI NMOS transistor is 3.3V; the drain terminal voltage, the source terminal voltage, the body terminal voltage and the substrate voltage are grounded.
5. The SOI NMOS total dose radiation multi-bias point current model modeling method of claim 1, wherein: the sidewall transistor current model satisfies the following relation:
Figure FDA0003127043210000021
wherein，Ids,sIs the leakage current of the sidewall transistor, musIs the carrier mobility, ε, of a sidewall transistoroxIs the dielectric coefficient of silicon dioxide, theta is the angle between the side wall gate terminal and the surface of the side wall transistor, L is the channel length of the main transistor, and V isgsteff,sIs the effective overdrive voltage, V, of the sidewall transistordseff,sIs the effective drain voltage of the sidewall transistor, AbulkIs a bulk charge factor, vtIs a thermal voltage.
6. The SOI NMOS total dose radiation multi-bias point current model modeling method of claim 1 or 5, wherein: the threshold voltage after the threshold voltage model of the drain induced barrier lowering effect is introduced meets the following relation:
Vth,s1＝Vth0,s-DIBL,sVds，
wherein, Vth,s1 is the threshold voltage after the threshold voltage model of the drain induced barrier lowering effect is introduced, Vth0,sDIBL, which is the equivalent zero bias threshold voltage of the total dose radiation effect,sFor the leakage induced barrier lowering effect parameter, VdsIs the drain voltage of the main transistor.
7. The SOI NMOS total dose radiation multi-bias point current model modeling method of claim 1 or 5, wherein: the threshold voltage after introducing the threshold voltage shift model of the radiation effect satisfies the following relation:
Vth,s2＝Vth0,s-ΔVth,s，
Figure FDA0003127043210000022
wherein, Vth,s2 is the threshold voltage after the threshold voltage shift model introducing the radiation effect, Vth0,sEquivalent zero bias threshold voltage, Δ V, for total dose radiation effectth,sIs a threshold voltage shift model of the radiation effect, k1For radiation-dependent overall coefficients, q is the charge constant, g0Is SiO2 absorption per unit massNumber of electron-hole pairs generated by 1rad (SiO2) energy, toxIs the thickness of the gate oxide layer, epsilonoxIs the dielectric coefficient of silicon dioxide, D is the total dose of radiation, and τ is the charge distribution coefficient.
8. The SOI NMOS total dose radiation multi-bias point current model modeling method of claim 1 or 5, wherein: the equivalent grid voltage model of the total dose radiation effect of the sidewall transistor meets the following relation:
Vgs,s＝αVgs，
wherein, Vgs,sIs the equivalent gate voltage of the total dose radiation effect of the sidewall transistor, alpha is a correction factor, VgsIs the gate voltage of the main transistor.
9. The SOINMOS total dose radiation multi-bias point current model modeling method of claim 1, wherein: and importing a sidewall transistor current model of a threshold voltage model introducing the leakage induced barrier reduction effect into parameter extraction software to extract parameters of the SOI sidewall transistor, wherein the parameters comprise one or more of carrier mobility of the sidewall transistor, thickness of a gate oxide layer, leakage induced barrier reduction effect parameters and sub-threshold slope.
10. The SOINMOS total dose radiation multi-bias point current model modeling method of claim 1, wherein: the radiation parameters include one or both of a total radiation dose or a charge distribution coefficient.
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