CN108364910B - Nanowire array surrounding gate MOSFET structure and manufacturing method thereof - Google Patents

Nanowire array surrounding gate MOSFET structure and manufacturing method thereof Download PDF

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CN108364910B
CN108364910B CN201810143686.8A CN201810143686A CN108364910B CN 108364910 B CN108364910 B CN 108364910B CN 201810143686 A CN201810143686 A CN 201810143686A CN 108364910 B CN108364910 B CN 108364910B
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nanowire
gate
layer
type mosfet
nanowire array
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CN108364910A (en
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徐秋霞
周娜
李俊峰
洪培真
许高博
孟令款
贺晓彬
陈大鹏
叶甜春
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Abstract

The invention discloses a nanowire array surrounding gate MOSFET structure and a manufacturing method thereof. The manufacturing method comprises the following steps: forming N-type MOSFET regions and/or P-type MOSFET regions separated by shallow trench isolation regions on a substrate; photoetching a nanowire pattern on a substrate, and alternately etching by adopting anisotropic plasma and isotropic plasma to form a silicon nanowire array structure with a plurality of layers of nanowire stacks; forming a sacrificial oxide layer on each nanowire of the silicon nanowire array structure to regulate the shape of the nanowire, and then removing the sacrificial oxide layer; for a P-type MOSFET region, SiGe selective epitaxial growth is carried out on a silicon nanowire, a Si film can be selectively covered on the SiGe to serve as a protective film, and then concentration oxidation is carried out to obtain a SiGe nanowire array structure; and manufacturing a high-K gate dielectric layer and a metal gate layer around the nanowire array structure. The nanowire array surrounding gate MOSFET structure not only keeps good mobility of Si nanowire surrounding gate NMOSFET electrons, but also improves hole mobility of SiGe nanowire surrounding gate PMOSFET.

Description

Nanowire array surrounding gate MOSFET structure and manufacturing method thereof
Technical Field
The disclosure belongs to the technical field of semiconductors, and relates to a nanowire array surrounding gate MOSFET structure and a manufacturing method thereof.
Background
With the feature size of integrated circuits becoming smaller and smaller, planar CMOS devices have met with serious challenges, and various new device structures have come into play, the device gate structures have been developed from the conventional planar single gate to the double-gate and triple-gate to the surrounding gate structure which completely wraps the channel, the gate control capability and the capability of controlling the short channel effect are continuously enhanced, the MOSFET with the nanowire surrounding gate structure having the quasi-ballistic transmission characteristic has been widely and highly emphasized due to the extremely strong gate control capability and the capability of reducing the size, and becomes a powerful competitor for the technical generations of 5nm and below.
At present, the successful nanowire fence device has been developed at home and abroad, and most of the nanowire fence devices are mainly made of Silicon On Insulator (SOI) substrates, and the fence structure is easier to manufacture due to the fact that a natural Silicon dioxide buried oxide layer is used as an isolation layer. However, the corresponding fence structure manufactured on the SOI substrate has the following defects: the SOI substrate has a self-heating effect and a floating body effect; the corresponding source-drain engineering is more complicated; the compatibility with the traditional bulk silicon CMOS process is limited; and the cost is still relatively high.
Silicon and SiGe nanowires are favored because of their more compatible fabrication processes, and SiGe nanowires are preferred for PMOSFETs because of their higher hole mobility. The process for fabricating SiGe nanowires reported so far is complex, the cost of the large marmesan dummy gate process using Si/SiGe alternating epitaxy is expensive, and the size reduction of nanowires has certain limitations.
Therefore, there is a need for a nanowire wrap gate MOSFET device structure and a method for fabricating the same that is easy to integrate, simple in fabrication process, and compatible with CMOS process.
Disclosure of Invention
Technical problem to be solved
The present disclosure provides a nanowire array wrap gate MOSFET structure and a method for fabricating the same to better solve the above-mentioned technical problems.
(II) technical scheme
According to an aspect of the present disclosure, there is provided a method for fabricating a nanowire array wrap gate MOSFET structure, including: forming N-type MOSFET region and/or P-type MOSFET region separated by shallow trench isolation region on substrate, and depositing SiO on the substrate2A/α -Si hard mask; photoetching a nanowire pattern on a substrate, and repeatedly and alternately etching by adopting anisotropic and isotropic plasmas to form a silicon nanowire array structure with a multilayer nanowire stack; forming a sacrificial oxide layer on each silicon nanowire of a silicon nanowire array structure to control the thickness of the nanowireSize and shape, then removing the sacrificial oxide layer; for a P-type MOSFET region, SiGe selective epitaxial growth is carried out on a silicon nanowire, a Si film can be selectively covered on the SiGe to serve as a protective film, and then concentration oxidation is carried out at a set temperature to obtain a SiGe nanowire array structure with high Ge content; manufacturing a high-K gate dielectric layer and a metal gate layer in the nanowire array structure; the metal gate layer comprises a first metal gate layer and a second metal gate layer, the first metal gate layer is doped with N-type (NMOSFET) and/or P-type (PMOSFET) dopants by isotropic plasmas, and the second metal gate layer covers the first metal gate layer and is annealed to form an interface dipole and adjust the effective work function.
In some embodiments of the present disclosure, fabricating a high-K gate dielectric layer and a metal gate layer in a nanowire array structure comprises: forming a dummy gate stack, a gate side wall surrounding the dummy gate stack and a source/drain region above the substrate of the N-type MOSFET region and/or the P-type MOSFET region; removing the dummy gate stack in the N-type MOSFET region and/or the P-type MOSFET region to form respective gate openings on the inner side of the gate side wall, so that the surface of the nanowire array structure is exposed; forming an interface oxide layer, a high-K gate dielectric layer and a first metal gate layer in sequence at respective gate openings of an N-type MOSFET region and/or a P-type MOSFET region; and respectively masking one of the N-type MOSFET region and the P-type MOSFET region, doping N-type or P-type dopant in the first metal gate layer by utilizing isotropic plasma doping on the other, controlling the energy of the plasma, enabling the doped ions to be distributed in the first metal gate layer only, controlling the doping dose according to the expected threshold voltage, covering the first metal gate layer by the second metal gate layer, carrying out annealing treatment, forming an interface dipole, and adjusting the effective work function.
In some embodiments of the present disclosure, the step of alternately forming the nanowire array structure of the multilayer nanowire stack by anisotropic and isotropic plasma etching further comprises: a passivation step, which comprises the following steps: oxidizing the exposed surface of the nanowire structure by using plasma after each step of etching to form a passivation film; and using CF4The anisotropic plasma removes the passivation film on the surface of the substrate,so as to facilitate the smooth proceeding of the subsequent etching; and/or after the high-K gate dielectric layer is formed, before the first metal gate layer is formed, the method further comprises the following steps: and after the high-K gate dielectric layer is manufactured, annealing treatment is carried out to improve the quality of the high-K gate dielectric layer.
In some embodiments of the present disclosure, after the step of forming the dummy gate stack, the gate sidewall surrounding the dummy gate stack, and the source/drain region over the substrate of the N-type MOSFET region and/or the P-type MOSFET region, the method further includes: forming silicified regions on the surface of the respective source/drain regions; forming an interlayer dielectric layer which covers the upper part of each source/drain region, the periphery of the outer surface of the grid side wall and the upper part of the dummy grid laminated layer; the dummy gate stack includes: and planarizing the surface of the interlayer dielectric layer and exposing the top surface of the dummy gate conductor by using chemical mechanical polishing.
In some embodiments of the present disclosure, the annealing treatment is performed under the following conditions: the annealing temperature is 350-450 ℃, and the annealing time is 20-90 min.
In some embodiments of the present disclosure, the temperature of the SiGe concentration oxidation is between 750 ℃ and 950 ℃ for 8 hours to 20 hours; and/or the thickness of SiGe selective epitaxial growth is between 5nm and 20nm, and the thickness of the covering Si film is between 0 and 3 nm.
In some embodiments of the present disclosure, the anisotropic plasma etch employs HBr/Cl2/O2a/He plasma; and/or isotropic etching with SF6a/He plasma; and/or the energy of the anisotropic plasma etching is between 150W and 350W; when HBr and Cl are used2When anisotropic plasma etching is performed by plasma, Cl2: HBr is between 1:1 and 1:3, and the additive is O2(ii) a And/or the energy of isotropic plasma etching is between 300W and 700W; when using SF6And He in isotropic plasma etching, SF6: he is between 1:5 and 1: 20.
In some embodiments of the present disclosure, the N-type dopant includes: hydrides and fluorides of phosphorus and arsenic, which are one or the combination of the following materials: phosphorus (P)Alkane, arsine, phosphorus pentafluoride, phosphorus trifluoride, arsenic pentafluoride or arsenic trifluoride; and/or the P-type dopant comprises: boron hydride, fluoride or chloride, which is one or the combination of the following materials: b is2H6、B4H10、B6H10、B10H14、B18H22、BF3Or BCl3。
In some embodiments of the present disclosure, the material of the high-K gate dielectric layer is one or a combination of the following materials: ZrO (ZrO)2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2HfAlO, HfAlON, HfSiO, HfSiON, HfLaO or HfLaON; and/or the material of the first metal gate layer is one or the combination of the following materials: TiN, TaN, MoN, WN, TaC, or TaCN; and/or the second metal grid layer comprises a plurality of layers of metal materials, wherein the metal material close to the first metal grid layer selects metal with good oxygen absorption performance, and the method comprises the following steps: at least one of Ti, TiAl and Ta; then a barrier metal comprising: one or two of TiN, TaN, Ta, MoN, AlN or WN; finally, a filler metal comprising: one or two of W, Al, TiAl and Mo; and/or the thickness of the high-K gate dielectric layer is between 1.5nm and 5 nm; and/or the thickness of the first metal gate layer is between 1nm and 10 nm.
According to another aspect of the present disclosure, a nanowire array wrap gate MOSFET structure is provided, which is manufactured by using any one of the methods for manufacturing the nanowire array wrap gate MOSFET structure mentioned in the present disclosure.
(III) advantageous effects
According to the technical scheme, the nanowire array wrap gate MOSFET structure and the manufacturing method thereof have the following beneficial effects:
the method comprises the steps that a silicon nanowire array structure and a SiGe nanowire array structure are correspondingly manufactured in an N-type MOSFET region and a P-type MOSFET region respectively, wherein the silicon nanowire array structure can be obtained by etching a silicon substrate in an isotropic plasma etching and anisotropic plasma etching alternating mode, the SiGe nanowire array structure is obtained by carrying out SiGe selective epitaxial growth on a silicon nanowire, a Si film can be selectively covered on the SiGe to serve as a protective film, and then concentration oxidation is carried out at a preset temperature to obtain the SiGe nanowire array structure; the method not only keeps the good mobility of Si nanowire surrounding gate NMOSFET electrons, but also improves the hole mobility of SiGe nanowire surrounding gate PMOSFET, is completely compatible with a CMOS (complementary metal oxide semiconductor transistor) process, has simple process and lower cost, is easier to reduce the size of the nanowire by controlling etching parameters, obtains the expected circular cross section morphology of the nanowire, and obtains the optimal gate control characteristic and the optimal device on-off ratio.
Drawings
Fig. 1 is a flow chart of a method for fabricating a nanowire array wrap gate MOSFET structure according to an embodiment of the present disclosure.
Fig. 2-6 are schematic structural diagrams illustrating a process for fabricating a nanowire array wrap gate MOSFET structure according to an embodiment of the present disclosure.
FIG. 2 is a schematic diagram of deposition of PE SiO on a substrate2The cross section structure of the/alpha Si hard mask is shown by the sectional view.
Fig. 3 is a schematic cross-sectional structure view taken along a cross-section of a nanowire array structure stacked by multiple layers of nanowires after being alternately etched by an isotropic plasma etching method and an anisotropic plasma etching method.
Fig. 4 is a schematic cross-sectional view taken along a cross-section after a sacrificial oxide layer is formed on each nanowire of the nanowire array structure.
Fig. 5 is a schematic view of a cross-sectional structure of a longitudinal section taken along the axial direction of the nanowire after forming a dummy gate stack, a gate sidewall surrounding the dummy gate stack, and a source/drain region over the substrate in the N-type MOSFET region and/or the P-type MOSFET region.
Fig. 6 is a schematic cross-sectional structure view taken along a plane a-a in fig. 4 after an interfacial oxide layer, a high-K gate dielectric layer and a metal gate layer are sequentially formed at respective gate openings of an N-type MOSFET region and/or a P-type MOSFET region.
[ description of the drawings ]
10-a substrate; 20-shallow trench isolation regions;
30-masking;
31-PE SiO2； 32-α Si；
40-nanowire array structures; 50-sacrificial oxide layer;
60-a dummy gate stack;
61-a dummy gate dielectric; 62-a dummy gate conductor;
70-a gate spacer; 80-interlayer dielectric layer;
81-source region; 82-a drain region;
91-interfacial oxide layer; 92-high-K gate dielectric layer;
93-first metal gate layer 94-second metal gate layer.
Detailed Description
The invention provides a nanowire array surrounding gate MOSFET structure and a manufacturing method thereof, the nanowire array surrounding gate MOSFET structure can be an easily integrated Si nanowire surrounding gate N-type MOSFET device structure or a SiGe nanowire surrounding gate P-type MOSFET device structure compatible with a CMOS (complementary metal oxide semiconductor transistor) process, or can also be provided with an N-type MOSFET region and a P-type MOSFET region in a CMOSFET device, so that the good mobility of Si nanowire surrounding gate NMOSFET electrons is reserved, the hole mobility of SiGe nanowire surrounding gate PMOSFET is improved, the nanowire array surrounding gate MOSFET structure is completely compatible with the CMOS process, the process is simple, the cost is low, the reduction of the nanowire size is easier to realize by controlling etching parameters, the expected nanowire circular cross section morphology is obtained, and the optimal gate control characteristic and the device on-off ratio are obtained.
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
In the present disclosure, the term "semiconductor structure" refers to a substrate formed after undergoing various steps of fabricating a semiconductor device and all layers or regions that have been formed on the substrate. The term "P-type dopant" refers to a dopant that can increase the effective work function for a P-type MOSFET. The term "N-type dopant" refers to a dopant that can reduce the effective work function for a P-type MOSFET. The term "source/drain region" refers to both the source and drain regions of a MOSFET. The term "between" includes both endpoints. In the following description, similar components are denoted by the same or similar reference numerals, whether or not shown in different embodiments. In the various drawings, the various features of the drawings are not drawn to scale for the sake of clarity. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure. And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. The same reference numerals are used for the same filling in the gate openings in fig. 5 and 6 of the drawings to indicate the same structures.
It should be noted that, in the drawings, the semiconductor structures are all illustrated by cross-sectional views, and the cross-section refers to a cross-section of the nanowire.
In a first exemplary embodiment of the present disclosure, a method of fabricating a nanowire array wrap gate MOSFET is provided.
Fig. 1 is a flow chart of a method for fabricating a nanowire array wrap gate MOSFET structure according to an embodiment of the present disclosure.
Referring to fig. 1, a method for manufacturing a nanowire array wrap gate MOSFET structure of the present disclosure includes:
step S102: forming N-type MOSFET region and/or P-type MOSFET region separated by shallow trench isolation region on substrate, and depositing SiO on the substrate2A/α -Si hard mask;
the substrate 10 of the present disclosure is a common semiconductor substrate, and may be a silicon substrate, an SOI substrate, and other semiconductor substrates. Since the silicon nanowire array structure and the SiGe nanowire array structure are respectively and correspondingly fabricated in the N-type MOSFET region and the P-type MOSFET region in the subsequent steps, fabricating nanowires on a bulk silicon substrate has very obvious advantages over fabricating nanowires on an SOI substrate, such as: the self-heating effect and the floating body effect of the SOI substrate are eliminated; complex source-drain engineering is avoided; the cost of the bulk silicon substrate is much lower; more compatible with conventional bulk silicon CMOS processes, etc., the semiconductor substrate is preferably a silicon substrate in this embodiment.
Since the nanowire array wrap gate MOSFET structure of the present disclosure may be a single N-type MOSFET device structure, a single P-type MOSFET device structure, or a CMOSFET device structure having an N-type MOSFET region and a P-type MOSFET region, the meaning of "N-type MOSFET region and/or P-type MOSFET region" herein denotes any of the three device structures described above.
Step S104: photoetching a nanowire pattern on a substrate, and alternately etching by adopting anisotropic plasma and isotropic plasma to form a layer of silicon nanowire structure;
FIG. 2 is a schematic diagram of deposition of PE SiO on a substrate2The cross-sectional structure of the/alpha Si hard mask is shown in the figure along the cross-sectional direction. Fig. 3 is a schematic cross-sectional structure view taken along a cross-section of a nanowire array structure stacked by multiple layers of nanowires after being alternately etched by an isotropic plasma etching method and an anisotropic plasma etching method.
The nanowire material is selected from Si, SiGe, Ge, III-V, II-VI, metals and their silicides, etc. In the present embodiment, the example that the N-type MOSFET region includes a Si nanowire and the P-type MOSFET region includes a SiGe nanowire is described as an example.
In this embodiment, referring to FIG. 2, the mask used for photolithography is a hard mask 30 comprising sequentially deposited SiO 231 and α Si 32, in step S104, after forming the hard mask 30, performing photolithography steps such as photoresist throwing, exposure, and development on the hard mask to form a layer of nanowire pattern, then etching the hard mask 30 by a dry etching method, then removing the photoresist, and performing dry etching to form a bulk silicon nanowire structure: the anisotropic etching and the isotropic etching are alternately carried out, during which the silicon surface of the exposed nanowire structure needs to be oxidized by plasma after each etching step to form a passivation film, and the formed nanowire structure is not damaged in the subsequent etching, so that the protection of the silicon nanowire structure is realized. The anisotropic etching is carried out by adopting HBr/Cl2/O2/He plasma; the isotropic etching is carried out by using SF6/He plasma; in the passivation step, oxidation is performed using oxygen plasma, followed by CF4Anisotropic plasma etching is carried out to remove only the silicon oxide passivation layer on the surface of the semiconductor substrate, so as to facilitate the smooth proceeding of the subsequent etching, and the etching power, the gas components, the etching time and the like are adjusted according to the required size and shape of the nanowire structureAnd (4) parameters.
Wherein, HBr and Cl are adopted for anisotropic plasma etching2、O2He plasma; the isotropic etching adopts SF6He plasma.
In the embodiment, the energy of the anisotropic plasma etching is between 150W and 350W; cl2: HBr is between 1:1 and 1:3, and an additive O can be added2。
In the embodiment, the energy of isotropic plasma etching is between 300W and 700W; SF6: he is between 1:5 and 1: 20.
Step S106: repeating the step of plasma etching to obtain a silicon nanowire array structure with stacked multilayer nanowires;
in this embodiment, the silicon nanowire array structure 40 with multiple layers of nanowire stacks obtained in step S106 is shown in fig. 3, and this embodiment is only illustrated by a structure with 3 layers of nanowire stacks, but the disclosure does not limit the number of layers of nanowires.
Step S108: forming a sacrificial oxide layer on each nanowire of the silicon nanowire array structure to regulate and control the size and the shape of the nanowire, and then removing the sacrificial oxide layer;
fig. 4 is a schematic cross-sectional view taken along a cross-section after a sacrificial oxide layer is formed on each nanowire of the nanowire array structure, where the cross-section of the nanowire is reduced in size and approaches a circular shape.
Referring to fig. 4, a sacrificial oxide layer 50 is formed on each nanowire of the nanowire array structure to remove etching damage and further control the size and shape of the nanowire structure, in this embodiment, after the sacrificial oxide layer 50 is formed on each nanowire of the silicon nanowire array structure 40, the size and shape of the nanowire array structure 40 are controlled due to stress, so as to obtain a circular shape as shown in fig. 4; the sacrificial oxide layer is then removed.
Step S110: carrying out SiGe selective epitaxial growth on a silicon nanowire in a P-type MOSFET region, selectively covering a Si protective film on SiGe, and then carrying out concentration oxidation at a set temperature to obtain a SiGe nanowire array structure with high Ge content;
in this embodiment, for the P-type MOSFET region, SiGe is selectively epitaxially grown on the silicon nanowire, and optionally covered with a Si protective film, followed by concentration oxidation at a predetermined temperature, and internal Si is diffused outward to form SiO2And when the Ge is consumed, the Ge is concentrated to form the SiGe nanowire array structure with high Ge content.
In the embodiment, the thickness of SiGe selective epitaxial growth is between 5nm and 20nm, the thickness of the Si film covering is between 0nm and 3nm, wherein 0 represents that the Si film is not covered as a protective layer; the temperature of SiGe concentration oxidation is between 750 ℃ and 950 ℃, and the time is between 8 hours and 20 hours.
Step S112: forming a dummy gate stack, a gate side wall surrounding the dummy gate stack and a source/drain region above the substrate of the N-type MOSFET region and/or the P-type MOSFET region;
fig. 5 is a schematic structural view of a longitudinal cross section of the substrate after forming a dummy gate stack, a gate sidewall surrounding the dummy gate stack, and a source/drain region over the substrate in the N-type MOSFET region and/or the P-type MOSFET region, and splitting the substrate along the axial direction of the nanowire.
In this embodiment, a dummy gate stack 60, a gate spacer 70 surrounding the dummy gate stack, and a source region 81 and a drain region 82 are formed over the substrate 10 in the MOSFET region, as shown in fig. 5. For the N-type MOSFET region, the nanowire array structure 40 is a silicon nanowire array structure, and the forming process is as shown in steps S102 to S108; for the P-type MOSFET region, the nanowire array structure 40 is a SiGe nanowire array structure, and the formation process is as shown in steps S102-S110.
In this embodiment, the dummy gate stack 60 is formed to include: a dummy gate dielectric 61 and a dummy gate conductor 62, wherein the material of the dummy gate dielectric 61 is silicon oxide, and the material of the dummy gate conductor 62 can be polysilicon, α Si, etc.
Step S114: removing the dummy gate stack in the N-type MOSFET region and/or the P-type MOSFET region to form respective gate openings on the inner side of the gate side wall, so that the surface of the nanowire array structure is exposed;
in this step, the dummy gate stack layer positioned at the inner side of the gate sidewall in the N-type MOSFET region and/or the P-type MOSFET region is removed, and respective gate openings of the N-type MOSFET region and/or the P-type MOSFET region are formed at the inner side of the gate sidewall, so that the surface of the nanowire array structure is exposed.
Step S116: forming an interface oxide layer, a high-K gate dielectric layer and a first metal gate layer in sequence at respective gate openings of an N-type MOSFET region and/or a P-type MOSFET region;
for the N-type MOSFET area, an interface oxide layer, a high-K gate dielectric layer and a metal gate layer are sequentially deposited around the silicon nanowire array structure; and for the P-type MOSFET region, an interface oxide layer, a high-K gate dielectric layer and a metal gate layer are sequentially deposited around the SiGe nanowire array structure.
Fig. 6 is a schematic view of a longitudinal cross-sectional structure cut along the axis of a nanowire after an interfacial oxide layer, a high-K gate dielectric layer and a metal gate layer are sequentially formed at respective gate openings of an N-type MOSFET region and/or a P-type MOSFET region. Referring to fig. 6, an interface oxide layer, a high-K gate dielectric layer, and a metal gate layer are sequentially deposited around each nanowire, and the interface oxide layer is thin and exists between the nanowire and the interface of the high-K gate dielectric layer, and for simplification of expression, the interface oxide layer between the nanowire and the high-K gate dielectric layer is not illustrated in fig. 6.
In other embodiments, after the step of forming the dummy gate stack, the gate sidewall surrounding the dummy gate stack, and the source/drain region over the substrate in the N-type MOSFET region and/or the P-type MOSFET region, the method further includes: forming silicified regions on the surface of the respective source/drain regions; forming an interlayer dielectric layer which covers the upper part of each source/drain region, the periphery of the outer surface of the grid side wall and the upper part of the dummy grid laminated layer; the dummy gate stack includes: and planarizing the surface of the interlayer dielectric layer and exposing the top surface of the dummy gate conductor by using chemical mechanical polishing. Since the silicide regions and the interlayer dielectric layer are disposed in a conventional manner, for simplicity, only the interlayer dielectric layer 80 after planarization is shown in fig. 6, the gate sidewall spacers 70 are also planarized, and the gate sidewall spacers 70 are shown filled with the same material.
In this embodiment, the material of the high-K gate dielectric layer is one or a combination of the following materials: ZrO (ZrO)2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2HfAlO, HfAlON, HfSiO, HfSiON, HfLaO or HfLaON. Preferably, the thickness of the high-K gate dielectric layer is between 1.5nm and 5 nm.
Preferably, after the high-K gate dielectric layer is formed, before the first metal gate layer is formed, the method further includes the following steps: and after the high-K gate dielectric layer is manufactured, annealing treatment is carried out to improve the quality of the high-K gate dielectric layer.
In this embodiment, the material of the first metal gate layer is one or a combination of the following materials: TiN, TaN, MoN, WN, TaC, or TaCN. Preferably, the thickness of the first metal gate layer is between 1nm and 10 nm.
Step S118: respectively masking one of the N-type MOSFET region and the P-type MOSFET region, doping N-type (NMOSFET) or P-type (PMOSFET) dopant ions in the first metal gate layer by utilizing isotropic plasma doping on the other, controlling the energy of the plasma, enabling the dopant ions to be only distributed in the first metal gate layer, and controlling the doping dose according to the expected threshold voltage;
in this embodiment, the doping ions of the first metal gate layer in the N-type MOSFET region are N-type dopants capable of reducing the effective work function; the doping ions of the first metal gate in the P-type MOSFET region are P-type dopants that increase the effective work function. Wherein the N-type dopant includes: hydrides, fluorides of phosphorus and arsenic, can be but are not limited to one or a combination of the following materials: phosphane, arsane, phosphorus pentafluoride, phosphorus trifluoride, arsenic pentafluoride or arsenic trifluoride; the P-type dopant includes: boron hydride, fluoride or chloride, which may be, but not limited to, one or a combination of the following materials: b is2H6、B4H10、B6H10、B10H14、B18H22、BF3Or BCl3。
Step S120: forming a second metal gate layer on the doped first metal gate layer to fill the gate opening, annealing to form an interface dipole, adjusting the effective work function, and finishing the manufacture of the nanowire array surrounding gate MOSFET structure;
in this embodiment, the metal gate layer includes a first metal gate layer and a second metal gate layer, the second metal gate layer covers the first metal gate layer to fill the gate opening, and then annealing is performed to form an interface dipole and adjust an effective work function.
In this embodiment, the second metal gate layer includes a plurality of metal materials, where the metal material adjacent to the first metal gate layer is a metal with good oxygen absorption performance, and includes: at least one of Ti, TiAl and Ta; then a barrier metal comprising: one or two of TiN, TaN, Ta, MoN, AlN or WN; finally, a filler metal comprising: one or two of W, Al, TiAl and Mo.
In this embodiment, the conditions for performing the annealing treatment to diffuse the dopant ions are as follows: the annealing temperature is 350-450 ℃, and the annealing time is 20-90 min.
In a second exemplary embodiment of the present disclosure, there is provided a nanowire array wrap gate MOSFET structure, which is manufactured by the manufacturing method of the present disclosure, and as shown in fig. 6, the nanowire array wrap gate MOSFET structure of the present disclosure includes:
a substrate 10 having N-type MOSFET regions and/or P-type MOSFET regions separated by shallow trench isolation regions 20; the source/drain regions are positioned at two sides of the edge of the N-type MOSFET region and/or the P-type MOSFET region; the nanowire array structure 40 is a stacked structure of multiple layers of nanowires and is located between the source region 81 and the drain region 82; forming an interface oxide layer 91, a high-K gate dielectric layer 92, a first metal gate layer 93 and a second metal gate layer 94 around each nanowire of the nanowire array structure 40 in sequence; and a gate sidewall 70 surrounding the high-K gate dielectric layer 91, the first metal gate layer 93, and the second metal gate layer 94; the nanowire array structure of the N-type MOSFET region is a silicon nanowire array structure and comprises a plurality of layers of stacked silicon nanowires; the nanowire array structure of the P-type MOSFET region is a SiGe nanowire array structure and comprises a plurality of layers of stacked SiGe nanowires; the metal gate layer comprises a first metal gate layer 93 and a second metal gate layer 94, the first metal gate layer adopts isotropic plasma to dope N-type (NMOSFET) or P-type (PMOSFET) dopant, the second metal gate layer 94 covers the first metal gate layer 93 to fill the gate opening, and then interface dipoles are formed through annealing treatment to adjust the effective work function.
In other embodiments, after the step of forming the dummy gate stack, the gate sidewall surrounding the dummy gate stack, and the source/drain region over the substrate in the N-type MOSFET region and/or the P-type MOSFET region, the method further includes: forming silicified regions on the surface of the respective source/drain regions; forming an interlayer dielectric layer 80 covering the upper part of the source/drain region, the periphery of the outer surface of the grid side wall and the upper part of the dummy grid lamination; the dummy gate stack includes: the dummy gate dielectric and the dummy gate conductor, and the surface of the interlevel dielectric layer 80 is planarized and the top surface of the dummy gate conductor is exposed using chemical mechanical polishing. Since the S/D silicide regions are conventional processes, they are not labeled here. It should be noted that the nanowire array wrap gate MOSFET structure may be an NMOSFET structure, the corresponding preparation method does not include the step of preparing the SiGe nanowire, and the ions doped in the first metal gate layer are an N-type dopant; the nanowire array surrounding gate MOSFET structure can also be a PMOSFET structure, the corresponding preparation method comprises the step of preparing SiGe nanowires, and ions doped in the first metal gate layer are P-type dopants; the nanowire array surrounding gate MOSFET structure can also be a CMOSFET structure, the corresponding preparation method simultaneously comprises the manufacturing steps of an N-type MOSFET region and a P-type MOSFET region, and isotropic plasma doping of an N-type dopant and a P-type dopant is correspondingly carried out in the first metal gate layers of the N-type MOSFET region and the P-type MOSFET region.
In summary, the present disclosure provides a nanowire array wrap gate MOSFET and a method for fabricating the same, in which a silicon nanowire array structure and a SiGe nanowire array structure are correspondingly fabricated in an N-type MOSFET region and a P-type MOSFET region, respectively, where the silicon nanowire array structure is obtained by etching a silicon substrate in an alternating manner of isotropic plasma etching and anisotropic plasma etching, the SiGe nanowire array structure is obtained by performing SiGe selective epitaxial growth on a silicon nanowire, selectively covering a Si film on SiGe as a protective film, and then performing concentration oxidation at a predetermined temperature; the method not only keeps the good mobility of Si nanowire surrounding gate NMOSFET electrons, but also improves the hole mobility of SiGe nanowire surrounding gate PMOSFET, is completely compatible with a CMOS (complementary metal oxide semiconductor transistor) process, has simple process and lower cost, is easier to reduce the size of the nanowire by controlling etching parameters, obtains the expected circular cross section morphology of the nanowire, and obtains the optimal gate control characteristic and the optimal device on-off ratio.
It is to be noted that the word "comprising" or "comprises" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify a corresponding element does not by itself connote any ordinal number of the element or any ordering of one element from another or the order of manufacture, and the use of the ordinal numbers is only used to distinguish one element having a certain name from another element having a same name.
In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims (10)

1. A method for manufacturing a nanowire array wrap gate MOSFET structure comprises the following steps:
forming N-type MOSFET and/or P-type MOSFET regions separated by shallow trench isolation regions on a substrate on which SiO is deposited2A/α -Si hard mask;
photoetching a nanowire pattern on a substrate, and repeatedly and alternately etching by adopting anisotropic and isotropic plasmas to form a silicon nanowire array structure with a multilayer nanowire stack;
forming a sacrificial oxide layer on each silicon nanowire of the silicon nanowire array structure to regulate and control the size and the shape of the nanowire, and then removing the sacrificial oxide layer;
for a P-type MOSFET region, SiGe selective epitaxial growth is carried out on a silicon nanowire, a Si film can be selectively covered on the SiGe to serve as a protective film, and then concentration oxidation is carried out at a set temperature to obtain a SiGe nanowire array structure with high Ge content; and
manufacturing a high-K gate dielectric layer and a metal gate layer in the nanowire array structure; the metal gate layer comprises a first metal gate layer and a second metal gate layer, wherein the first metal gate layer is doped with N-type and/or P-type dopant by isotropic plasma, and the second metal gate layer covers the first metal gate layer and is annealed to form an interface dipole and adjust the effective work function.
2. The method of claim 1, wherein the fabricating the high-K gate dielectric layer and the metal gate layer in the nanowire array structure comprises:
forming a dummy gate stack, a gate side wall surrounding the dummy gate stack and a source/drain region above the substrate of the N-type MOSFET region and/or the P-type MOSFET region;
removing the dummy gate stack in the N-type MOSFET region and/or the P-type MOSFET region to form respective gate openings on the inner side of the gate side wall, so that the surface of the nanowire array structure is exposed;
forming an interface oxide layer, a high-K gate dielectric layer and a first metal gate layer in sequence at respective gate openings of an N-type MOSFET region and/or a P-type MOSFET region; and
respectively masking one of the N-type MOSFET region and the P-type MOSFET region, doping N-type or P-type dopant in the first metal gate layer by utilizing isotropic plasma doping on the other, controlling the energy of the plasma, enabling the doped ions to be only distributed in the first metal gate layer, controlling the doping dose according to the expected threshold voltage, covering the first metal gate layer by the second metal gate layer, carrying out annealing treatment, forming an interface dipole, and adjusting the effective work function.
3. The method of manufacturing of claim 2, wherein:
the step of alternately forming the nanowire array structure of the multilayer nanowire stack by adopting anisotropic and isotropic plasma etching further comprises:
a passivation step, which comprises the following steps: oxidizing the exposed surface of the nanowire structure by using plasma after each step of etching to form a passivation film; and
using CF4Removing the passive film on the surface of the substrate by the anisotropic plasma so as to facilitate the smooth proceeding of subsequent etching; and/or
After the high-K gate dielectric layer is formed, the method also comprises the following steps before the first metal gate layer is formed: and after the high-K gate dielectric layer is manufactured, annealing treatment is carried out to improve the quality of the high-K gate dielectric layer.
4. The method of claim 2, wherein after the step of forming the dummy gate stack, the gate sidewall surrounding the dummy gate stack, and the source/drain region over the substrate in the N-type MOSFET region and/or the P-type MOSFET region, further comprising: forming silicified regions on the surface of the respective source/drain regions; forming an interlayer dielectric layer which covers the upper part of each source/drain region, the periphery of the outer surface of the grid side wall and the upper part of the dummy grid laminated layer; the dummy gate stack includes: and planarizing the surface of the interlayer dielectric layer and exposing the top surface of the dummy gate conductor by using chemical mechanical polishing.
5. The manufacturing method according to claim 2, wherein the conditions for performing the annealing treatment are as follows: the annealing temperature is 350-450 ℃, and the annealing time is 20-90 min.
6. The method of manufacturing of claim 1, wherein:
the temperature of the SiGe concentration oxidation is 750-950 ℃, and the time is 8-20 hours; and/or
The thickness of the SiGe selective epitaxial growth is between 5nm and 20nm, and the thickness of the covering Si film is between 0nm and 3 nm.
7. The method of manufacturing of claim 1, wherein:
HBr/Cl is adopted in the anisotropic plasma etching2/O2a/He plasma; and/or
The isotropic etching adopts SF6a/He plasma; and/or
The energy of anisotropic plasma etching is between 150W and 350W; when HBr and Cl are used2When anisotropic plasma etching is performed by plasma, Cl2HBr is between 1:1 and 1:3, and the additive is O2(ii) a And/or
The energy of isotropic plasma etching is between 300 and 700W; when using SF6And He in isotropic plasma etching, SF6He is between 1:5 and 1: 20.
8. The method of manufacturing of claim 1, wherein:
the N-type dopant includes: hydrides and fluorides of phosphorus and arsenic, which are one or the combination of the following materials: phosphane, arsane, phosphorus pentafluoride, phosphorus trifluoride, arsenic pentafluoride or arsenic trifluoride; and/or
The P-type dopant includes: boron hydride, fluoride or chloride, which is one or the combination of the following materials: b is2H6、B4H10、B6H10、B10H14、B18H22、BF3Or BCl3。
9. The method of manufacturing of claim 1, wherein:
the high-K gate dielectric layer is made of one or a combination of the following materials: ZrO (ZrO)2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2HfAlO, HfAlON, HfSiO, HfSiON, HfLaO or HfLaON; and/or
The material of the first metal gate layer is one or a combination of the following materials: TiN, TaN, MoN, WN, TaC, or TaCN; and/or
The second metal gate layer comprises a plurality of layers of metal materials, wherein the metal material close to the first metal gate layer selects metal with good oxygen absorption performance, and the second metal gate layer comprises the following components: at least one of Ti, TiAl and Ta; then a barrier metal comprising: one or two of TiN, TaN, Ta, MoN, AlN or WN; finally, a filler metal comprising: one or two of W, Al, TiAl and Mo; and/or
The thickness of the high-K gate dielectric layer is between 1.5nm and 5 nm; and/or
The thickness of the first metal gate layer is between 1nm and 10 nm.
10. A nanowire array wrap gate MOSFET structure made by the method of any of claims 1 to 9.
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