CN108351341B

CN108351341B - Digital patch clamp amplifier

Info

Publication number: CN108351341B
Application number: CN201680062644.0A
Authority: CN
Inventors: R·洛布迪尔
Original assignee: Sutter Instrument Co
Current assignee: Sutter Instrument Co
Priority date: 2015-09-18
Filing date: 2016-09-12
Publication date: 2020-07-14
Anticipated expiration: 2036-09-12
Also published as: WO2017048635A4; CN108351341A; US10393727B2; WO2017048635A1; US20170082600A1; EP3350594A1

Abstract

A patch-clamp amplifier that can be easily manufactured, can be easily reconfigured for product renewal, and can be quickly reconfigured to a different mode during operation. One example may provide a patch-clamp amplifier that can be easily manufactured by implementing some or all of the compensation and other circuitry using digital circuitry. These digital circuits may be implemented using discrete or integrated logic circuits, programmable logic such as field programmable gate arrays or programmable logic arrays, or other fixed or configurable logic circuits, or a combination thereof. These programmable logic circuits may be reconfigured by a user or by a manufacturer through firmware or software updates when a product update is required. These circuits may also be quickly reconfigured to allow for quick switching of modes during use.

Description

Digital patch clamp amplifier

Cross Reference to Related Applications

This application claims priority to U.S. patent application No. 14/859, 227, filed on 9/18/2015, which is incorporated herein by reference.

Background

Patch-clamp amplifiers can be used in cell and molecular biology to measure and record electrical signals generated by biological tissues. Biological tissue may allow a small current to flow through the cell wall or membrane when the cell is stimulated by a voltage signal. In short, a patch clamp amplifier can be used to measure and record the resulting current flowing through the cell as a result of the voltage input. Typically, the voltage input is a step or other function, referred to as a command signal, which may be applied via a pipette in contact with the cell. The resulting current can then be measured and recorded.

Measuring and recording such resulting cell currents can be very difficult. For example, pipettes may have stray or parasitic capacitances that may generate large currents when a command signal is applied. This large signal may overwhelm or overwhelm the desired output signal current generated by the cell, making determination of the actual cell current problematic. Similarly, pipettors and cells may have other stray or parasitic capacitances and resistances, and the current signals they produce may similarly hide or mask the currents of interest, particularly the currents generated by the cells themselves.

The solution is to include various circuits in these patch-clamp amplifiers that compensate for these unwanted signals, leaving behind the desired signal. But this leads to a tremendous complexity of patch-clamp amplifiers. These complex patch-clamp amplifiers have proven difficult to manufacture. Moreover, they are so specialized that once manufactured, they can be difficult to reconfigure. For example, it may be desirable to reconfigure one or more circuits in a product upgrade or improvement. The complexity of current patch-clamp amplifiers may limit such reconfiguration.

Moreover, during use of the device, it may be desirable to quickly reconfigure the patch-clamp amplifier in order to make a relevant set of measurements. Also, the complexity of existing patch-clamp amplifiers may slow the reconfiguration process and limit the ability to take such related measurements.

Accordingly, there is a need for a patch-clamp amplifier that can be easily manufactured, can be easily reconfigured for product renewal, and can be quickly reconfigured to a different mode during operation.

Disclosure of Invention

Thus, embodiments of the present invention may provide a patch-clamp amplifier that may be easily manufactured, may be easily reconfigured for product renewal, and may be quickly reconfigured to a different mode during operation.

Illustrative embodiments of the invention can provide patch-clamp amplifiers that can be easily manufactured by implementing some or all of the compensation and other circuitry in the patch-clamp amplifier using digital circuitry. These digital circuits may be implemented using discrete or integrated logic circuits, programmable logic such as field programmable gate arrays or programmable logic arrays, microprocessors or other fixed or configurable logic circuits, or a combination thereof. These digital circuits can replace complex analog circuits that may have several limiting and undesirable characteristics. For example, these analog circuits may require manual tuning or adjustment of several potentiometers and other variable components. These adjustments may be inadvertently altered or lost, for example, during shipping when the patch clamp amplifier is under stress. Moreover, the potentiometers themselves may be relatively expensive or difficult to procure due to lack of current demand for these components. Replacing such complex analog circuitry with digital circuitry may provide a patch-clamp amplifier that is easier to manufacture.

More specifically, embodiments of the invention may provide a patch-clamp amplifier having a probe circuit to receive an input signal, which may be referred to as a command signal, to receive a current signal derived from the command signal and to convert the received current signal to a voltage. The patch-clamp amplifier may also include one or more compensation circuits to compensate for various non-ideal aspects of a measurement system that includes the patch-clamp amplifier. The patch-clamp amplifier may have other circuitry to boost the gain of the probe, filter the output, or perform other functions. In various embodiments of the present invention, the probe circuitry may be implemented using analog circuitry, while the one or more compensation circuits and at least one of the other circuits may be implemented using digital circuitry. Analog-to-digital converters and digital-to-analog converters may be used to convert signals between the probe circuitry and one or more compensation circuits and other circuitry. These transducers may be located close to the probe to reduce noise coupling on the analog signal lines.

Illustrative embodiments of the present invention may further provide a patch-clamp amplifier that may be easily reconfigured for product upgrades. In various embodiments of the present invention, at least one of the one or more compensation circuits and other circuits may be implemented using programmable logic circuitry. These programmable logic circuits may be reconfigured by a user or by a manufacturer through firmware or software updates. This may provide for a simple reconfiguration, especially when compared to what would be required to reconfigure a complex analog circuit involving many separate gain circuits, switches, capacitors, etc.

This configurability may also be advantageous during operation of the patch-clamp amplifier. For example, illustrative embodiments of the invention may provide a patch-clamp amplifier that may be operated in various modes, which may include a voltage-clamp mode and a current-clamp mode. This may be useful if the patch-clamp amplifier can alternate or switch from one of these modes to the other or between them in rapid succession. Also, while this may be difficult to achieve in conventional patch-clamp amplifiers, the patch-clamp amplifier provided by the illustrative embodiments may use programmable logic to implement the critical path involved in this mode switching. Such programmable logic can be quickly reconfigured to allow for quick changes between modes.

The use of programmable logic or other digital circuitry for one or more compensation or other circuits may also provide performance improvements. For example, operational amplifiers may produce non-linear or asymmetric responses, time delays, excessive noise, and they may have bandwidth limitations and suffer from temperature drift. Capacitors may exhibit undesirable properties such as leakage and dielectric absorption. Analog switches can have significant on-resistance, non-linearity, and suffer from crosstalk. Replacing these components with programmable logic or other digital circuitry can provide compensation and other circuitry with improved performance.

Another illustrative embodiment of the present invention may provide a patch-clamp amplifier having a probe. The probe can receive the command signal, provide the command signal to the cell, receive the resulting current, convert the resulting current to an output voltage, and provide the output voltage. The probe may include a transimpedance or other type of amplifier. In particular, a command signal may be received at a first input terminal of a transimpedance amplifier. The transimpedance amplifier may have a feedback configured such that a voltage on the second input terminal of the transimpedance amplifier follows a command signal applied to the first input terminal. The voltage may then be provided to the cells. The resulting current may be received at the second input terminal. A current may flow through a feedback impedance around the transimpedance amplifier to generate a voltage, which may be provided as an output.

There may be several parasitic components in the measurement system that contains the patch-clamp amplifier. These parasitic components may generate signals that may mask the desired current signal generated by the cell. Several of these parasitic components may produce signal components that can be compensated by the compensation circuit in the patch-clamp amplifier. One or more of these compensation circuits may be implemented with programmable logic or other digital circuitry. Particular embodiments of the present invention may provide a patch-clamp amplifier in which each of these compensation circuits is implemented on a programmable logic circuit. Each of these compensation circuits may at least reduce or mitigate unwanted signal components. Each compensation may be performed by providing a cancellation signal. At least some of these cancellation signals may be provided by a digital-to-analog converter that converts the cancellation signals from the programmable logic circuit and provides analog signals to the probe circuitry.

In this and other embodiments of the invention, one or more of these compensation circuits may include circuitry for adjusting the magnitude and frequency response of the cancellation signal so that the cancellation signal more accurately reduces or mitigates the unwanted signal components. In these embodiments, each compensation circuit may include a fixed or variable gain circuit for resizing and a filter for adjusting the frequency response of the cancellation signal. It should be noted that these gain circuits may provide a gain that is less than a unity element and therefore may operate as attenuators. These cancellation signals may be added to the command signals, they may be injected as currents added to the cell currents, or they may be added to the output signals or amplified or filtered versions of the output signals.

These parasitic components in a measurement system that may include patch clamp circuitry according to embodiments of the present invention may include pipette capacitance, pipette resistance, cell capacitance, and cell resistance. The resistance of the cell, the series resistance of the pipette, and the capacitance of the cell may create a time constant that may act as a filter and may slow the edge of a step or other voltage applied to the cell. From the cell perspective, the pipette's series resistance and cell resistance may be in parallel. Since the cell resistance may typically be much larger than the series resistance, the time constant can be reduced to depend on the cell capacitance and the series resistance. To reduce or mitigate this filtering, embodiments of the invention may employ a series resistance prediction circuit. The circuit may receive a step or other function, add the overshoot portion, and provide the sum as a command signal. The overshoot portion may help reduce the delayed response that may be seen in the cell due to the time constant of the cell capacitance and series resistance. The series resistance prediction circuit may include a filter and a gain stage, as with other compensation circuits. In particular, the series resistance prediction circuit may include a high pass filter for providing the overshoot. The frequency response of the high pass filter can be set by estimating the cell capacitance and the series resistance. The series resistance prediction circuit may further include a gain stage. The series resistance prediction circuit may be an open loop path. That is, estimates of cell capacitance and series resistance may be used to generate a prediction signal that is added to the command signal.

The series resistance prediction circuit may also be used in a calibration routine to determine estimates of the series resistance and the cell capacitance. For example, the initial estimate may be used to set the frequency response of a filter in a series resistance prediction circuit that provides an overshoot signal to compensate for the time constant seen by the cell due to the finite bandwidth. The amount of compensation needed to compensate for the filtering effect of the series resistance and cell capacitance can be found. In particular, the desired peak amplitude and time constant of the overshoot waveform can be found. Thus, estimates of series resistance and cell capacitance can be determined and used in series resistance prediction circuits and elsewhere.

Series resistance may also result in a voltage drop that reduces the input voltage provided to the cells. Specifically, when a cell receives an input voltage and begins to conduct, current may flow through the series resistance, thereby reducing the voltage seen by the cell. To reduce or mitigate this, embodiments of the invention may employ a series resistance correction circuit. The circuit may receive an output from the probe and provide a correction voltage to the command signal. In particular, since the estimate of the series resistance is known, as the probe output increases, it can be determined how much voltage drop is seen in the cell due to the cell current flowing through the series resistance. The command signal, and thus the input voltage, may be increased to compensate for and help maintain the voltage seen by the cell. Since the output of the probe is used to generate the input to the probe, the series resistance correction circuit is a closed loop circuit. To prevent this loop oscillation, a hysteresis filter may be used to limit the bandwidth of the feedback loop. The correction circuit may also include a gain circuit.

A pipette may have a capacitance associated with it. This capacitance may draw a charging current when an input voltage is applied to the pipette. Thus, illustrative embodiments may inject current at the input to compensate for the charging current. The pipette compensation path may be used to provide a voltage coupled through a capacitor to generate a voltage at the input node. The pipette compensation path may include a low pass filter in series with the gain circuit. In particular, the command signal may be received by a pipette compensation path. The signal may be low pass filtered, which essentially integrates the command signal. The resulting voltage may be gain adjusted or, more specifically, attenuated. The output voltage may then be applied through a capacitor that essentially takes the derivative of the output voltage and supplies current to the input. This current may at least approximately cancel the current drawn by the pipette capacitance.

In various embodiments of the present invention, it may be desirable to model pipette capacitance as a series of parallel capacitors coupled to each other by small resistors. In these embodiments of the present invention, the pipette compensation path may comprise parallel paths, each parallel path comprising a series combination of low pass filters in series with one or more gain circuits to implement a higher order filter to more accurately compensate for pipette capacitance.

In a similar manner, a cell may have a capacitance associated with it. This capacitance may draw a charging current when an input voltage is applied to the pipette. Thus, illustrative embodiments may inject current at the input to compensate for the cell capacitance charging current. The whole-cell compensation path may be used to provide a voltage coupled through a capacitor to generate a current at the input node. The whole-cell compensation path may include a low-pass filter in series with the gain circuit. In particular, a step or other function for providing a command signal may be received by the whole-cell compensation path. The signal may be low pass filtered, which essentially integrates the step or other function. The resulting voltage may be amplified by an amount at least approximately equal to a ratio of the whole-cell capacitance to a coupling capacitor used to couple the output voltage of the whole-cell compensation path. The command signal itself may then be added to the signal to generate the output voltage of the whole-cell compensation path. The output voltage may then be applied through a capacitor that essentially takes the derivative of the output voltage and supplies current to the input. This current can then at least approximately cancel the current drawn by the cell capacitance.

The series resistance and the cell resistance may form a path from the pipette input to ground. The resistive path may thus create a leakage path that generates leakage current. Accordingly, embodiments of the present invention may employ a leakage mitigation circuit. The leakage current may increase the magnitude of the output voltage. Thus, the leakage reduction circuit may receive a step or other function for generating the command signal. The step or other function may be attenuated and subtracted from the output voltage to compensate for the increase in output amplitude caused by leakage current.

These and other embodiments of the invention may provide other circuits that may also be implemented using programmable logic or other digital circuitry. For example, it may be desirable to boost or adjust the gain for the output signal from the probe. It may also be desirable to filter the output of the probe. Thus, a frequency boost, which may include a filter and an optional gain stage, may be inserted at the output of the probe circuit. In these and other embodiments of the present invention, it may be desirable to further filter the output signal. Thus, the output signal may be filtered using a signal conditioning filter, which may be implemented as a higher order Bessel or other type of filter. The filter may have an adjustable bandwidth in various embodiments of the invention.

Various embodiments of the present invention may utilize various control circuits. These control circuits may include a microcontroller or other processing circuit, a host computer or other processing, control, or computing circuit. In an illustrative embodiment of the present invention, a microcontroller may be used to control programmable logic such as a field programmable gate array. The microcontroller or programmable logic or control circuitry elsewhere may load configuration data for the programmable logic at startup, reset, or other appropriate time. The microcontroller may be used to communicate gain settings, filter constants, or other values to the programmable logic. In a specific example, a user may input the bandwidth of the filter into a host computer using a Graphical User Interface (GUI). The microcontroller can take the bandwidth values from the host and calculate the required filter constants. The filter constants can then be sent to programmable logic, which can then configure the filter. In these and other embodiments of the invention, filter constant calculations may be accomplished using double-precision floating-point mathematics.

In the above example, a voltage is forced on the cell and the resulting current is measured. This may be referred to as a voltage clamp configuration. In other test configurations consistent with embodiments of the present invention, a current is forced into the cell and the resulting voltage is measured. This may be referred to as a current clamp configuration. In these embodiments of the invention, the circuitry may be reconfigured from the voltage clamp configuration described above to a current clamp circuit. That is, the current clamp circuit may use the same circuit as used in the above example, but reconnect to this new configuration.

Specifically, a command waveform may be received and converted to a current. A current may be forced into the cell and the gain of the resulting voltage may be adjusted and provided as an output. Pipette capacitance may be compensated with a loop that adjusts the gain of a portion of the output voltage and applies it to the summing node through a capacitor. This technique may be referred to as capacitive neutralization. The series resistance may be compensated by subtracting a portion of the command signal from the resulting output signal.

In other embodiments of the invention, a varying current may be forcibly applied to the cells, wherein the current varies over time, such that the desired conductance may be provided to the sample as a function of time. This may be referred to as a dynamic clamp or a conductive clamp configuration. The circuitry described above for the voltage clamp circuit (which may be reconfigured for the current clamp circuit) may also be reconfigured as a conductance clamp, which may be more generally referred to as a dynamic clamp. These embodiments of the invention can vary the current and voltage conditions applied to the sample. This can be used to mimic current and voltage conditions that one cell may supply to an adjacent cell or for other reasons.

In a conductance clamp configuration, a desired or target conductance waveform may be received and stored in memory. A command signal having a first amplitude may be generated. The command signal may be used to generate a current into the sample. The resulting voltage can be measured. From which the measured conductance can be calculated. A target conductance value may be read from the memory, where the target conductance value is a target value for conductance at a next point in time. The measured conductance may be compared to a target conductance. The difference between the measured conductance and the target conductance may be used to determine a change in the magnitude of the command signal amplitude.

Various embodiments of the present invention may incorporate one or more of these and other features described herein. The nature and advantages of the invention may be better understood with reference to the following detailed description and the accompanying drawings.

Drawings

FIG. 1 illustrates a measurement system that may be improved by incorporating embodiments of the present invention;

FIG. 2 illustrates a spurious component in a measurement system according to an embodiment of the present invention;

FIG. 3 illustrates a system diagram of a measurement system according to an embodiment of the invention;

FIG. 4 illustrates another system diagram of a measurement system according to an embodiment of the invention;

FIG. 5 illustrates another system diagram of a measurement system according to an embodiment of the invention;

FIG. 6 illustrates a probe (headstage) according to an embodiment of the invention;

FIG. 7 illustrates another probe according to an embodiment of the invention;

FIG. 8 illustrates a portion of a probe and associated transducer according to an embodiment of the invention;

FIG. 9 illustrates a portion of a probe and associated transducer according to an embodiment of the invention;

FIG. 10 illustrates another probe according to an embodiment of the invention;

FIG. 11 illustrates another probe according to an embodiment of the invention;

FIG. 12 illustrates a waveform generator according to an embodiment of the invention;

FIG. 13 illustrates another waveform generator according to an embodiment of the present invention;

FIG. 14 illustrates a series resistance correction and prediction circuit according to an embodiment of the present invention;

FIG. 15 illustrates a whole-cell compensation circuit (whole-cell compensation circuit) according to an embodiment of the present invention;

fig. 16 illustrates a pipette compensation circuit according to an embodiment of the present invention;

FIG. 17 illustrates an output regulation and leakage reduction circuit according to an embodiment of the present invention;

FIG. 18 illustrates a current clamp circuit according to an embodiment of the present invention;

FIG. 19 illustrates a dynamic clamp circuit according to an embodiment of the invention; and

FIG. 20 is a flow chart illustrating operation of a dynamic clamping circuit according to an embodiment of the present invention.

Detailed Description

FIG. 1 illustrates a measurement system that may be improved by incorporating embodiments of the present invention. This figure is shown together with other included figures for illustrative purposes and does not limit the possible embodiments of the invention and the claims.

The figure illustrates an amplifier circuit 110 that can be used to characterize the electrical response of a cell membrane, sample or tissue 140. Specifically, one or more cells of the sample 140 may be placed in the bath 132 in the sample dish 130. The sample dish 130 may be a Petri dish (Petri dish) or other type of sample dish. Amplifier 110 may provide voltage V1 to cell sample 140 via conductor 112 and pipette 120. A voltage V1 may be applied on conductor 112 relative to conductor 114, and conductor 114 may be in electrical contact with bath 132. Bath 132 and conductor 114 may be electrically connected to ground.

When the signal voltage V1 is applied, the resulting current I1 may be provided to the cell sample 140 by the amplifier 110. The provided current I1 may be converted to a voltage and provided as the output VOUT on line 116. The resulting voltage VOUT for a given input voltage V1 can be used to characterize the electrical properties of the cells in sample 140.

Unfortunately, some complexity may arise in implementing such a measurement system. For example, the resistance of the cells in the sample 140 may be very high, and thus any resulting current I1 may be very small and difficult to measure accurately. This may be further complicated by the presence of parasitic components in the pipettor 120 and sample 140, as well as other parts in the measurement system. For example, the pipette 120 may have a resistance and a capacitance associated therewith. The cells in the sample 140 may also have a resistance and capacitance associated with them. These parasitic components may distort voltage V1 before voltage V1 is applied to sample 140, thereby degrading the quality of any resulting measurements. These parasitic components may also generate currents that may add to I1 or even overwhelm I1, further degrading the quality of any resulting measurements. The lower graph shows examples of these parasitic components.

FIG. 2 illustrates parasitic components that may be present in a measurement system according to an embodiment of the invention. In this figure, pipette 120 may have a series resistance RS. Pipette 120 may also have a parasitic capacitance CP that is grounded. The sample 140 may have a series resistance RM and a capacitance CM to ground or bath 132.

Again, these parasitic components may distort voltage V1 when voltage V1 is applied to sample 140. Moreover, these parasitic components may generate currents that make it difficult to determine I1. Accordingly, embodiments of the present invention may use compensation circuitry to compensate for these effects. For example, embodiments of the present invention may provide a compensation circuit to adjust the voltage V1 such that a desired voltage is applied to the sample 140. These and other embodiments of the present invention may also provide compensation circuitry to create a current to cancel the current generated by the parasitic component.

Typically, such compensation circuitry may be implemented with analog circuitry. These analog circuits may have several limiting and undesirable characteristics. For example, operational amplifiers may produce non-linear or asymmetric responses, time delays, excessive noise, and they may have bandwidth limitations and be affected by temperature drift. Capacitors may exhibit undesirable properties such as leakage and dielectric absorption. Analog switches can have significant on-resistance, non-linearity, and suffer from crosstalk.

Moreover, these analog circuits may be difficult to manufacture. For example, these analog circuits may require manual tuning or adjustment of several potentiometers and other variable components. These adjustments may be inadvertently altered or lost, for example, during shipping when the patch clamp amplifier is under stress. Moreover, the potentiometers themselves may be relatively expensive or difficult to procure due to lack of current demand for these components.

Thus, embodiments of the present invention may provide patch-clamp amplifiers that may be easily manufactured by implementing some or all of the compensation and other circuitry using digital circuitry. These digital circuits may be implemented using discrete or integrated logic circuits, programmable logic such as field programmable gate arrays or programmable logic arrays, or other fixed or configurable logic circuits, or a combination thereof. These digital circuits can replace those complex analog circuits that may have several limiting and undesirable characteristics. Replacing such complex analog circuitry with digital circuitry may provide a patch-clamp amplifier that is easier to manufacture. Further, these programmable logic circuits may be reconfigured by a user or manufacturer through firmware or software updates. This may provide for a simple reconfiguration, especially when compared to what would be required to reconfigure a complex analog circuit involving many separate gain circuits, switches, capacitors, etc. The following figure shows an example of a measurement system incorporating these compensation circuits.

FIG. 3 illustrates a system diagram of a measurement system according to an embodiment of the invention. The measurement system may include a probe (headstage)310, an FPGA 330, a microcontroller 340, and a host computer 342. In this example, an amplifier such as amplifier 110 may be implemented by the probe 310 and the FPGA 330.

In this system, the FPGA 330 can provide digital functions to the digital to analog converter 326. Digital-to-analog converter 326 may convert the digital signal to an analog COMMAND signal. In this and other embodiments of the invention, the digital function and the resulting COMMAND signal may be a step, pulse, sine wave, ramp, sawtooth, triangular wave, or other function of different or arbitrary shape. The analog COMMAND signal may be received at the non-inverting input of amplifier 312. Amplifier 312 may be configured as a transimpedance amplifier. Amplifier 312 may drive voltage V1 so that it is equal to the analog command signal. Voltage V1 may be applied to membrane 140 via pipettor 120. The resulting current I1 may pass through a feedback impedance ZF, thereby generating a voltage VHS. The voltage VHS may be converted to a digital signal by the analog-to-digital converter 324 and provided to the FPGA 330.

Also, the parasitic component may degrade the quality of the signal V1 seen by the cell. Accordingly, FPGA 330 can provide precompensated V1 so that the actual V1 seen by the cell is the desired waveform. Moreover, parasitic components in this measurement system may create currents. These currents may be compensated by embodiments of the present invention. In this example, FPGA 330 may provide pipette compensation signal VPC to capacitor CPC via digital-to-analog converter 320. The voltage applied at capacitor CPC relative to V1 may generate a current to compensate for the current generated by pipette capacitance CP. Similarly, FPGA 330 can provide a full-cell compensation signal VWC to capacitor CWCC via digital-to-analog converter 322. The voltage applied at capacitor CWCC relative to V1 may generate a current to compensate for the current generated by the membrane capacitance of sample 140.

In this example, the FPGA 330 may be controlled by a microcontroller 340. The microcontroller 340 may be used to load configuration data into the FPGA 330 at startup, reset, or other appropriate times. The microcontroller 340 may also be used to communicate gain settings, constants, or other variables or values to the FPGA 330.

The host computer 342 may provide a user interface to the measurement system. In a specific example, a user can input the bandwidth of the filter into the host computer 342 using a graphical user interface. The microcontroller 340 can take the bandwidth values from the host and calculate the required filter constants. The filter constants can then be sent from the microcontroller 340 to the FPGA 330, and the FPGA 330 can then configure the filter.

In these examples, analog-to-digital converters and digital-to-analog converters may be used to convert signals between the probe circuitry and one or more compensation and other circuits. These transducers may be located close to the probe to reduce noise coupling on the analog signal lines. In a particular example, the probe 310 and the

transducer

320 and 326 are in or on a first housing near the pipettor 120 and the sample 140, and the FPGA 330 is in or on a second remote housing, with one or more cables passing digital information between the two.

In this example, various compensation paths may be included in the FPGA 330. In other block diagrams, they may be shown as different circuits. The following figures show examples.

FIG. 4 illustrates another system diagram of a measurement system according to an embodiment of the invention. In this example, an amplifier such as amplifier 110 may be implemented using probe 410, waveform generator 420, series resistance correction and prediction 430, and pipette compensation and whole cell compensation 440. In various embodiments of the present invention, the waveform generator 420, series resistance correction and prediction 430, and pipette compensation and whole cell compensation 440 may be implemented using an FPGA or other programmable circuitry (e.g., FPGA 330).

The waveform generator 420 may generate a step or other function VWF to be applied to the cell membrane. Also, parasitic components may degrade the quality of the generated steps or other functions before they reach the cell. Thus, series resistance correction and prediction circuit 430 may adjust the step or other function VWF and generate a COMMAND signal, which may be provided to probe 410.

More specifically, the cell can see a capacitance CM in parallel with resistors RS and RM. Since the resistance RM of the film may be large, this parallel combination can be simplified to a capacitance CM and a resistance RS. These components may effectively create a time constant at the cell membrane, which may have the effect of rolling off the leading edge of a step or other function applied to the cell. To compensate for this roll off, a boost or overshoot may be added to waveform VWF generated by waveform generator 420 by series resistance correction and prediction circuitry 430 to generate the COMMAND signal.

The COMMAND signal may be received by probe 410, and probe 410 may then generate input voltage V1 to the cell. The step waveform V1 may generate a current through the pipette capacitance CP. To compensate for the current through capacitor CP, pipette compensation and whole cell compensation 440 may receive COMMAND signal and step function VWF from waveform generator 420 and generate voltage VPC at capacitor CPC. Similarly, the voltage applied at the cell may generate a current through the capacitor CM. Pipette compensation and whole cell compensation 440 may also provide voltage VWC to capacitor CWCC in order to compensate for the current in capacitor CM. The resulting current may help to reduce or eliminate current in the membrane capacitance CM.

In this particular example, since the COMMAND signal is otherwise added to the output signal VHS, a second amplifier 412 in probe 410 may be used to subtract the COMMAND signal from the output of amplifier 312. In other embodiments of the invention, the mitigation function may be implemented digitally, for example, in the FPGA 330.

FIG. 5 illustrates another system diagram of a measurement system according to an embodiment of the invention. In this example, pipette compensation 540 and whole cell compensation 550 are shown as separate circuits. Frequency boosting 560 and output signal conditioning and leakage reduction 570 are also included. In this example, an amplifier such as amplifier 110 may be implemented using probe 510, waveform generator 520, series resistance correction and prediction 530, pipette compensation 540, whole cell compensation 550, frequency boost 560, and output signal conditioning and leakage reduction 570. In one embodiment of the invention, these circuits, other than the probe 510, may be implemented using digital circuitry such as the FPGA 330.

As previously described, waveform generator 520 may generate a step or other function VWF. Waveform VWF may be received through series resistance correction and prediction 530. Series resistance correction and prediction 530 may generate a COMMAND signal that may be received by probe 510. Probe 510 may receive the COMMAND signal and generate voltage V1. A voltage V1 may be applied to the cells resulting in a resulting current I1. The current I1 may flow through the feedback impedance ZF, thereby generating the output voltage VHS. The output signal VHS may be amplified by a frequency boost 560 to generate a signal VBOOST. The VBOOST signal may be received by the series resistance correction and prediction circuit 530.

The pipette compensation 540 may use the COMMAND signal to provide the voltage VPC. Voltage VPC may generate a current through capacitor CPC that may at least reduce or eliminate current in pipette capacitance CP. COMMAND signal may also be provided to whole-cell compensation 550, and whole-cell compensation 550 may also receive output VWF from waveform generator 520. Whole-cell compensation 550 may generate voltage VWC, which may be applied to capacitor CWCC. Voltage VWC may generate a current in capacitor CWCC that may at least reduce or compensate for the current generated by capacitance CM at the membrane.

Output signal conditioning and leakage subtraction 570 may receive output signal VBOOST from frequency boost 560 and may filter and provide VBOOST as output VOUT. Output signal conditioning and leakage reduction 570 may also receive the output of waveform generator 520 and may compensate for the leakage path formed by the combination of series resistance RS and cell membrane resistance RM.

As indicated above, various configurations for the probe may be used consistent with embodiments of the present invention. The following figures show examples.

FIG. 6 illustrates a probe according to an embodiment of the invention. As previously described, probe 410 may receive a COMMAND signal. This COMMAND signal may be a step or other function with an overshoot that has been adjusted to compensate for the RC time constant at the cell sample. The COMMAND signal may be received at the non-inverting input of amplifier 312. Amplifier 312 may drive voltage V1 to track the COMMAND signal. V1 may be received by a cell and may generate a current 11. The current I1 may flow through the feedback impedance ZF to create a signal at the non-inverting input of the amplifier 412. Amplifier 412 may be configured to subtract the COMMAND signal from the resulting voltage and provide output signal VHS.

The pipette compensation path may provide a voltage VPC to a capacitor CPC, which may create a current to compensate for the current flowing in the pipette capacitance CP. The whole-cell compensation path may provide a voltage VWC to a capacitor CWCC, which may create a current to compensate for the current flowing in the cell capacitance CM.

FIG. 7 illustrates another probe according to an embodiment of the invention. In this example, the second amplifier 412 may be omitted, and the command signal may be digitally subtracted from the output signal VHS. The following figure shows an example of doing so.

FIG. 8 illustrates a portion of a probe and associated transducer according to an embodiment of the present invention. In this example, the digital COMMAND signal may be received by a digital-to-analog converter 326. Digital-to-analog converter 326 may provide a step or other function to the non-inverting input of amplifier 312. Amplifier 312 may drive V1 to sample 140, generating current I1. The current I1 may generate a voltage across the impedance ZF, which in this case may be a resistance. An analog frequency boost or high pass filter 805 may be used to boost the output of the amplifier 805. The analog-to-digital converter 324 may convert the output signal of the analog frequency boost or high pass filter 805 to a digital signal. The summing node 730 may subtract the command signal from the output of the analog-to-digital converter 324, thereby generating the probe output voltage VHS.

Again, in this example, the feedback impedance ZF may be resistive. In other embodiments of the invention, the feedback impedance ZF may be capacitive. When ZF is capacitive, the feedback capacitor ZF will integrate the current I1. To provide the output voltage, digital frequency boosting may be used. The following figures show examples.

FIG. 9 illustrates a portion of a probe and associated transducer according to an embodiment of the present invention. Likewise, the COMMAND signal may be received by digital to analog converter 326. Digital-to-analog converter 326 may provide a step or other function to the non-inverting input of amplifier 312. Amplifier 312 may drive voltage V1 to follow this step or other function, thereby generating current I1. The current I1 may charge a capacitor as a feedback impedance ZF, thereby generating a voltage that may be converted by the analog-to-digital converter 324. The command signal may be subtracted from the output of analog-to-digital converter 324 at summing node 730. The outputs of summing nodes 730 may be differentiated by digital frequency boosting or high pass filter 810 to provide an output signal VHS.

FIG. 10 illustrates another probe according to an embodiment of the invention. In this example, the feedback component ZF may be resistive. As previously described, digital to analog converter 326 may receive the COMMAND1 signal. Digital-to-analog converter 326 may provide an output attenuated by a factor "k," which provides an analog COMMAND signal to the non-inverting input of amplifier 312. As previously described, amplifier 312 may drive V1 to follow the command signal. This may in turn generate a current I1 that may flow through an impedance ZF, which may be resistive, generating a voltage at the input of the analog frequency boost or high pass filter 805. The output of an analog frequency boost or high pass filter 805 may be received at the input of an analog-to-digital converter 324. The command signal may be divided by a factor "k" and subtracted from the output of the analog-to-digital converter 324 to generate the upper voltage VHS.

In this example, the attenuation block may provide an attenuation factor of 0.1. This may allow a larger dynamic signal to be used as the COMMAND1 signal. This may provide the following benefits: more dynamic range of the digital-to-analog converter 326 may be utilized and the quantization error of the digital-to-analog converter 326 may be reduced by a factor of 10.

As previously described, capacitors CPC and CWCC may receive a voltage to compensate for the current in capacitors CP and CM, respectively.

FIG. 11 illustrates another probe according to an embodiment of the invention. In this example, the feedback component ZF may be capacitive. Instead of passing the output of amplifier 312 through an analog frequency boost or high pass filter 805, the output of amplifier 312 may be converted to a digital signal by an analog to digital converter 324. The output of analog-to-digital converter 324 may be summed with the gain portion of the COMMAND1 signal, where the gain may be approximately one-tenth the attenuation. This attenuation may be matched to the attenuation in the analog COMMAND path so that the amplitude of the attenuated COMMAND1 signal is equal to the amplitude of the analog COMMAND signal applied to the inverting input of amplifier 312, but in digital form. The summed value may then be boosted by a digital frequency boost or high pass filter 810 and then provided as an output of the probe.

Circuit blocks such as the waveform generator shown above may be implemented in various ways. An example of a waveform generator is shown in the following figure.

In various embodiments of the invention, the waveform generator may be used as a waveform generator, such as waveform generator 520, the waveform generator may include a barrel shifter 1110 and a lookup table 1120, the barrel shifter 1110 may be enabled by an enable signal EN and may be clocked by a clock signal C L OCK, the barrel shifter may act as a counter providing an input to lookup table 1120, desired step or other waveform function values may be stored in lookup table 1120.

FIG. 13 illustrates another waveform generator according to an embodiment of the present invention. In this example, at least two sources may be used to generate the waveform. The first is an external input 1210, which may receive a waveform from an external pulse or function generator. The waveform may be converted by analog-to-digital converter 1220 and provided to low pass filter 1230. The low pass filter may filter the high frequency edges of the waveform voltage and provide the output VWF.

A second source that may be used to generate waveforms is waveform generator 1240. Generator 1240 may provide an output to low pass filter 1230, which may again provide waveform output VWF.

Again, these waveform generators may provide a step or other function to the cell. However, at the cell, the signal may be filtered by an RC time constant comprising the capacitance CM of the cell and the series resistance RS of the pipette. To compensate for this, an overshoot may be added to the step or other function. This compensation overshoot may be performed by a prediction circuit. Also, when a cell conducts current, a voltage may be generated across the series resistance RS. To compensate for this voltage drop, the magnitude of the step or other function may be increased. The second compensation may be performed by a correction circuit. The lower diagram shows a series resistance correction and prediction circuit that can provide two functions.

FIG. 14 illustrates a series resistance correction and prediction circuit according to an embodiment of the present invention. A series resistance correction and prediction circuit may be used as the series resistance correction and prediction 530 and as other series resistance correction and prediction circuits in other embodiments of the present invention.

A step or other function VWF may be received from the waveform generator at summing node 1310. The waveform may also be filtered by a high pass filter 1320, and the high pass filter 1320 may generate an overshoot version of the waveform generator. The output of filter 1320 may pass through gain stage 1330 and be selectively added at summing node 1310. This path may be disabled by switch 1340. The overshoot version of VWF generated by filter 1320 may compensate for the RC time constant at the cell.

Again, when a current starts to flow in the cell, a voltage may appear across the series resistance RS. This voltage may reduce the voltage seen at the cell. Thus, embodiments of the invention may use measurements of cell current to increase the voltage applied at the cell so that the voltage applied at the cell may remain at least approximately constant. In this example, the gain of the output signal VBOOST, which should be proportional to the cell current, may be adjusted by block 1350 and filtered by filter 1360. This voltage may be added through summing node 1310 to create a command output signal. This path may be disabled by switch 1370.

It should be noted that each compensation path included herein is used to provide a voltage having a particular waveform and amplitude. Accordingly, each compensation path may include a filter and a gain stage. Thus, the prediction path may include filter 1320 and gain stage 1330, while the correction path may include filter 1360 and gain stage 1350.

The series resistance prediction circuit may also be used in a calibration routine to determine estimates of the series resistance and the cell capacitance. For example, the initial estimate may be used to set the frequency response of filter 1320. These settings may provide the magnitude and duration of the overshoot signal to compensate for the time constant seen by the cell due to the limited bandwidth. The amount of compensation needed to compensate for the filtering effect of the series resistance RS and the cell capacitance CM can be found by varying these estimates until the filtering effect is ineffective. In particular, the peak amplitude and time constant of the overshoot waveform needed to compensate for the cell time constant can be found. Thus, estimates of series resistance and cell capacitance can be determined and used in series resistance prediction circuits and elsewhere.

It should be noted that the series resistance correction path is closed loop in nature. That is, the measurement of the cell current is used in real time to adjust the applied COMMAND signal and the resulting V1. In contrast, the prediction circuit is open-loop in that it receives or determines the settings and uses the settings for subsequent measurements of feedback adjustments.

Again, when an input voltage is applied to the cell, a current may flow in the cell capacitance. Such capacitive currents may be undesirable and may mask the true cell currents. Accordingly, embodiments of the present invention may include a whole cell compensation circuit to compensate for or at least reduce the cell capacitance current. The following figures show examples.

FIG. 15 illustrates a whole-cell compensation circuit according to an embodiment of the invention. A step or other function for providing a command signal may be received by the whole-cell compensation path. The signal may be low pass filtered, which essentially integrates the step or other function. The resulting voltage may adjust the gain of the ratio of the whole-cell capacitance to the coupling capacitor used to couple the output voltage of the whole-cell compensation path. The command signal itself may then be added to the signal to generate the output voltage of the whole-cell compensation path. The output voltage may then be applied through a capacitor that essentially takes the derivative of the output voltage and supplies current to the input. This current at least approximately eliminates the current drawn by the cell capacitance.

Specifically, waveform generator output signal VWF may be received at low pass filter 1410. The output of low pass filter 1410 may be received by gain stage 1420. This output may be added to the COMMAND signal at summing node 1430 and provided to digital to analog converter 322. As indicated above, digital-to-analog converter 322 can generate waveform VWC, which can be provided to capacitor CWCC.

Likewise, when an input voltage is applied to a cell, a current may also flow in the pipette capacitance. This current may also be undesirable and may mask the true cellular current. Accordingly, embodiments of the present invention may include pipette compensation circuitry to compensate for or at least reduce the pipette capacitance current. The following figures show examples.

Fig. 16 illustrates a pipette compensation circuit according to an embodiment of the present invention. The COMMAND signal may be received by the pipette compensation path. The signal may be low pass filtered, which essentially integrates the COMMAND signal. The resulting voltage may be gain adjusted or, more specifically, attenuated. The output voltage may then be applied through a capacitor that essentially takes the derivative of the output voltage and supplies current to the input. This current may at least approximately cancel the current drawn by the pipette capacitance.

In particular, the COMMAND signal may be received by low pass filter 1510. The gain of the output of filter 1510 or the output of attenuation filter 1510 may be adjusted by gain stage 1520. The output of gain stage 1520 may be converted by digital-to-analog converter 320. As indicated above, the digital-to-analog converter 320 may provide the output voltage VPC to the capacitor CPC. In various embodiments of the present invention, pipette capacitance may be better approximated as two or three separate capacitors with a smaller resistance therebetween. In this case, more than one series of filters and gain stages may be included. In this example, a second filter and gain stage comprising filter 1530 and gain

stages

1540 and 1550 may also be included. The output of this additional stage may be added to the output of gain stage 1520 at summing node 1560. In other embodiments of the present invention, to better compensate for pipette capacitance, a further series combination of a low pass filter and a gain stage may be included.

The series combination of RS as RMs may provide a leakage path from V1 to ground. The leakage path may be compensated to reduce resultant errors that the current may cause. Furthermore, filtering of the output signal may be required. Thus, embodiments of the present invention may employ output regulation and leakage reduction circuits. The following figures show examples.

FIG. 17 illustrates an output regulation and leakage reduction circuit according to an embodiment of the present invention. The output conditioning and leakage reduction circuit may be used as the output signal conditioning and leakage reduction circuit 570, or as an output signal conditioning and leakage reduction circuit in other embodiments of the present invention.

In this example, the gain of the output VWF of the waveform generator or the output VWF of the decaying waveform generator may be adjusted by

gain blocks

1610 and 1620 and added to VBOOST at summing node 1630. The output of summing junction 1630 may be filtered by filter 1640 and saved to disk or provided as an analog signal by digital-to-analog converter 1650, or both saved to disk and provided as an analog signal by digital-to-analog converter 1650. The leakage compensation path may be disabled by switch 1660. The low pass filter 1640 may be a Bessel filter or other type of filter. The low pass filter 1640 may have a variable bandwidth.

In the above example, a voltage is forced on the cell and the resulting current is measured. Again, this may be referred to as a voltage clamp configuration. In other test configurations consistent with embodiments of the present invention, a current is forced into the cell and the resulting voltage is measured. This may be referred to as a current clamp configuration. The following figures show examples.

FIG. 18 illustrates a current clamp circuit according to an embodiment of the present invention. The circuitry shown here may be the same as that used in the above example, but reconnected to this new configuration. For example, amplifier 1710 may be the same amplifier as amplifier 312. In a specific embodiment of the present invention, amplifier 312 may be internally reconfigured to have its inverting and non-inverting inputs inverted. Similarly, amplifier 1712 may be amplifier 412 reconnected in this new configuration.

In this configuration, DAC1724 may generate a current command as compared to the voltage command in the example described above. DAC1724 may generate a voltage that may be converted to a current by amplifier 1712 and its surrounding resistors. That is, the voltage across ZF may be generated, thereby generating the desired I1. This I1 is then forced into the output terminal and into the cell. The resulting voltage can then be measured.

In particular, the command waveform may be received and converted by analog-to-digital converter 1754. Alternatively, the command waveform may be read from disk. The selected command waveform may be the output of summing node 1752 and may be filtered by low pass filter 1750. The output of low pass filter 1750 may be converted by digital to analog converter 1724 (command DAC) and provided to amplifier 1712. In the example above, command DAC1724 may be the same DAC as DAC 326. In other embodiments of the present invention, DAC1724 and DAC 326 may be different DACs. This may help to allow for rapid changes in operation from the voltage-clamp mode shown above to the current-clamp mode shown here.

A voltage may be generated across ZF, which may be the same ZF around the amplifier 312 but reconnected. The forced voltage across ZF may generate a current that may be forced into the summing node and into the cell as current 11. The resulting voltage may be buffered by amplifier 1710, gain adjusted by gain block 1714, and converted by analog-to-digital converter 1726 before being filtered by low pass filter 1732. The low pass filter 1732 may be the same as the low pass filter 1640 in the example above. The output of the filter 1732 may then be stored and converted by a digital to analog converter 1734 to an analog voltage that may be observed using an oscilloscope.

In previous configurations, capacitor CWC may be used to eliminate the full cell capacitance of the sample in a voltage clamp configuration where a voltage is forced onto the cell and the resulting current is measured. In this current clamp configuration, it may be desirable to measure the whole-cell capacitance of the cell, so this elimination may not be desirable. It may not be feasible to simply disconnect the CWC from the circuit. Switches, relays or micro-electromechanical (MEM) switches may be used, but errors due to the introduced capacitance may make the use of such components undesirable due to the small value of the CWC.

Thus, embodiments of the invention may provide a signal to the CWC capacitor at the output of the digital-to-analog converter 1722 such that the net or differential voltage across the CWC does not change. When the voltage across the CWC is constant in the current clamp mode, no current flows through the CWC. In this way, the CWC capacitance can be virtually disconnected. In particular, the voltage at the output terminal may be received by the amplifier 1710 and the gain of the voltage at the output terminal adjusted by the analog gain block 1714. This may be converted to a digital signal by an analog to digital converter 1726. This may then be reconverted to an analog signal by digital-to-analog converter 1722 and attenuated by analog gain block 1716. This may generate a voltage at a first terminal of the capacitor CWC that nearly replicates the signal at a second terminal of the CWC that is connected to the output terminal and the non-inverting input of the amplifier 1710. In this way, the voltage across capacitor CWC does not change (i.e. it has zero ac voltage) and CWC does not provide input current to the output terminals. In other embodiments of the present invention, the analog gain block 1716 may be replaced by a digital gain block at the input of the digital to analog converter 1722.

Pipette capacitance CP may be compensated using a technique known as capacitive neutralization. That is, gain stage 1718 and DAC 1720 may be used to generate a negative capacitance that cancels or neutralizes CP. Specifically, the output signal from ADC1726 may be gain adjusted by gain block 1718 with a value between 0 and1 and converted by DAC 1720. DAC 1720 can then provide an analog voltage to capacitor CMJ. The voltage step across capacitor CMJ again generates a current spike into the summing node. This current spike (again, the spike here is a fast edge of exponentially decaying current) can compensate for the slowing down or roll-off of the current into the cell caused by the pipette capacitance CP. After reconnecting to this new configuration,

DACs

1722 and 1720 may be the same DACs as

DACs

322 and 320.

The series resistance RS may generate a voltage proportional to the input current added to the actual output voltage. Thus, embodiments of the present invention may subtract a portion of the input command from the output voltage to be compensated. Specifically, the gain block 1740 may generate a portion of the voltage used to generate the current to be input to the cell and RS. This voltage is subtracted from the output of the ADC1726 at summing node 1730 to compensate for the increase in voltage at the output of the ADC1726 due to the presence of the RS.

In this embodiment of the invention, a feedback loop is formed by gain block 1718, DAC 1720, amplifier 1710, gain block 1714, and ADC 1726. Therefore, this loop may oscillate. Accordingly, embodiments of the present invention may adjust the frequency response of one or more of these loop components to avoid an oscillation condition.

By utilizing many of the same circuits in this current clamp configuration and the voltage clamp configuration described above, the test circuit provided by embodiments of the present invention can alternate between the two modes in a fast manner. This may allow a technique known as discontinuous voltage clamping. This may have the effect of removing the series resistance RS from the measurement and may result in a more reliable system.

In other embodiments of the invention, it may be desirable to provide electrical conductance to the cells. This can be used to mimic current and voltage conditions that may be applied to a cell from a neighboring cell or for other reasons. In this manner, embodiments of the present invention can mimic the signals provided by neighboring cells and measure the results. The circuitry shown above for the voltage clamp circuit and the current clamp circuit may be reconfigured as a conductance clamp circuit, better known as a dynamic clamp circuit. In particular, amplifiers, DACs and filters, gain stages, and other circuitry from above may be reused with additional circuitry to generate the time-varying command signals. The lower diagram shows such a circuit.

FIG. 19 illustrates a dynamic clamp circuit according to an embodiment of the invention. As previously described, the digital command signal may be provided to the DAC 1724. DAC1724 may drive amplifier 1712. The amplifier 1712 may provide a voltage equal or proportional to the command voltage across the impedance ZF to generate the command current I1 into the sample. The resulting voltage may be buffered by amplifier 1710, gain adjusted by block 1714, and converted to a digital signal by analog-to-digital converter 1726. The output of the analog-to-digital converter 1726 may be filtered by the low pass filter 1732 and the result may be recorded or observed at the DAC 1734 as previously described.

The magnitude of the command current, which is the command voltage provided to the DAC1724 divided by the magnitude of the impedance ZF, and the resulting voltage at the output of the low pass filter 1732 may be used to determine the measured conductance. The target conductance value for the next point in time may be read from the memory 1910. The measured conductance may be compared to a target conductance by comparison block 1920 to generate a comparison or error signal. The error signal may be used to generate a new magnitude of the command signal by calculation block 1930.

FIG. 20 is a flow chart illustrating the operation of a dynamic clamping circuit according to an embodiment of the present invention. In act 2010, an amplitude of the command signal is changed. The first time through this loop, a feedback condition may not have been established. Thus, the initial command amplitude may be read from memory, determined based on past results, or otherwise determined. From the command signal amplitude, a current into the sample may be generated in act 2020. The resulting voltage may be measured in act 2030. From this, a measurement may be calculated in act 2040.

In act 2050, a target conductance value may be read from the memory. The target conductance value may be used for the next point in time. The measured conductance value may be compared to the target conductance in act 2060. From the difference of these values, an error signal can be determined. A new command amplitude may be determined based on the error signal in act 2070. The time may be incremented in act 2080. When the loop returns to act 2010, the command amplitude may change.

In various embodiments of the present invention, the new command amplitude may be determined based on the error signal in different ways. In one embodiment of the invention, the change in amplitude of the command signal is the change in amplitude required to change the measured conductance by an amount equal to the error signal. In one embodiment of the invention, this may be determined by a plurality of step change command signals associated with the error signal.

The correlation can be determined by using a typical current-voltage relationship of the sample. That is, by knowing the typical current-voltage relationship of a sample, one can determine how much the current into the cell needs to be changed to achieve the result of the desired change in conductance. For a given error signal in conductance, the required change in sample current can be approximated, and the command signal can be changed accordingly.

In another embodiment of the invention, the clock rate of the signal generating the command signal may be fast enough so that changes in the command signal may track changes in the target conductance by incrementing or decrementing once per time period. In each time period (which may be one or more FPGA clock cycles), the command signal may be incremented by one bit when the conductance is to be increased and decremented by one bit when the conductance is to be decreased. That is, the command signal may be incremented by one bit when the error signal is positive, and decremented by one bit when the error signal is negative.

In another embodiment of the present invention, if the magnitude of the error signal is greater than the first threshold, the command signal may increment or decrement by two bits as needed. This can be extended to any number of thresholds and any number of bits.

The foregoing descriptions of embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is, therefore, to be understood that the invention is intended to cover all modifications and equivalents within the scope of the appended claims.

Claims

1. An electronic device, comprising:

a memory for storing information for digital waveforms;

a digital waveform generator for receiving stored information and generating the digital waveform using the stored information, wherein the digital waveform generator is a synchronous digital hardware circuit;

a series resistance compensation circuit for receiving the digital waveform from the digital waveform generator and providing a digital command signal, wherein the series resistance compensation circuit is a synchronous digital hardware circuit;

a first digital-to-analog converter for converting the digital command signal from the series resistance compensation circuit to an analog command signal;

a pipettor compensation and whole cell compensation circuit for receiving the digital command signal from the series resistance compensation circuit and the digital waveform from the digital waveform generator and providing a digital pipettor compensation signal and a digital whole cell compensation signal, wherein the pipettor compensation and whole cell compensation circuit comprises synchronous digital hardware circuitry;

a second digital-to-analog converter for converting the digital pipettor compensation signals from the pipettor compensation and whole cell compensation circuits to analog pipettor compensation signals;

a third digital-to-analog converter for converting the digital whole-cell compensation signal from the pipettor compensation and whole-cell compensation circuit to an analog whole-cell compensation signal; and

a first analog circuit for receiving the analog command signal, the analog pipettor compensation signal, and the analog whole cell compensation signal and providing an analog probe output signal to a first analog-to-digital converter,

wherein the series resistance compensation circuit also receives a digital probe output signal from the first analog-to-digital converter, an

Wherein the digital waveform generator, the series resistance compensation circuit, and the pipette compensation and whole cell compensation circuits are implemented on a field programmable gate array.

2. The electronic device of claim 1, wherein the series resistance compensation circuit implements a first algorithm to predict and compensate for a series resistance of a cell; and

the pipettor compensation and whole cell compensation circuitry implements a second algorithm to compensate for pipettor capacitance and compensate for the cell capacitance.

3. The electronic device of claim 2, wherein the first analog circuit is a probe circuit including a first amplifier having a non-inverting input coupled to receive the analog command signal and an inverting input coupled to receive the analog pipette compensation signal via a first capacitor and the analog whole cell compensation signal via a second capacitor.

4. The electronic device of claim 3, further comprising a first impedance coupled between an inverting input and an output of the first amplifier of the probe circuit.

5. The electronic device of claim 1, wherein the series resistance compensation circuit comprises a first filter and a first gain stage, and the pipette compensation and whole cell compensation circuit comprises a second filter and a second gain stage.

6. The electronic device of claim 1, wherein the series resistance compensation circuit implements a first algorithm to predict and compensate for a series resistance of a cell, and the pipette compensation and whole cell compensation circuit implements a second algorithm to compensate for a capacitance of a pipette and implements a third algorithm to compensate for a capacitance of the cell.

7. An electronic device, comprising:

a memory for storing information for digital waveforms;

processing circuitry to receive the digital waveform and generate a digital command signal, wherein the processing circuitry includes synchronous digital hardware circuitry;

a first digital-to-analog converter for converting the digital command signal to an analog command signal;

a first analog circuit for receiving the analog command signal and providing a first analog voltage at a first terminal, wherein the first analog voltage generates a first analog current, the first analog circuit further for providing an analog probe output based on the first analog current;

a first analog-to-digital converter for receiving the analog probe output and digitizing the analog probe output to generate a digital probe output;

the processing circuit is used for processing the digital probe output and generating a digital pipettor compensation signal; and

a second digital-to-analog converter for converting the digital pipettor compensation signal to an analog pipettor compensation signal and providing the analog pipettor compensation signal to the first terminal,

wherein the digital waveform generator and the processing circuitry are implemented on a field programmable gate array.

8. The electronic device of claim 7, wherein the first terminal is configured to provide the first analog voltage to a pipette, and wherein the pipette is in contact with a cell.

9. The electronic device of claim 7, wherein the processing circuit further generates a digital whole cell compensation signal, and wherein the electronic device further comprises a third digital-to-analog converter to convert the digital whole cell compensation signal to an analog whole cell compensation signal and provide the analog whole cell compensation signal to the first terminal.

10. The electronic device of claim 9, wherein the analog pipette compensation signal is provided to the first terminal through a first capacitor and the analog whole cell compensation signal is provided to the first terminal through a second capacitor.

11. The electronic device of claim 7, wherein the field programmable gate array is controlled by a microcontroller and wherein the microcontroller is controlled by a host computer.

12. The electronic device of claim 7, wherein the processing circuit comprises:

a series resistance compensation circuit for providing the digital command signal to the first digital to analog converter and for implementing a first algorithm to predict and compensate for the series resistance of the cell; and

pipette compensation circuitry for providing the digital pipette compensation signal to the second digital-to-analog converter and for implementing a second algorithm to compensate for pipette capacitance.

13. The electronic device of claim 9, wherein the processing circuit comprises:

a series resistance compensation circuit for providing the digital command signal to the first digital to analog converter and for implementing a first algorithm to predict and compensate for the series resistance of the cell;

pipette compensation circuitry for providing the digital pipette compensation signal to the second digital-to-analog converter and for implementing a second algorithm to compensate for pipette capacitance; and

a whole-cell compensation circuit for providing the digital whole-cell compensation signal to the third digital-to-analog converter and for implementing a third algorithm to compensate for capacitance of the cell.

14. An electronic device, comprising:

a first amplifier having a first input coupled to the first terminal, and a second output;

a first impedance coupled between a first input of the first amplifier and an output of the first amplifier;

a first analog-to-digital converter having an input coupled to an output of the first amplifier;

a processing circuit coupled to an output of the first analog-to-digital converter, the processing circuit comprising:

a memory for storing information for digital waveforms;

a series resistance compensation circuit having an input for receiving the digital waveform and comprising a first filter and a first gain stage, wherein the series resistance compensation circuit is a synchronous digital hardware circuit;

a pipette compensation circuit having an input for receiving an output from the series resistance compensation circuit and including a second filter and a second gain stage, wherein the pipette compensation circuit is a synchronous digital hardware circuit; and

a whole-cell compensation circuit having an input for receiving the digital waveform and including a third filter and a third gain stage, wherein the whole-cell compensation circuit is a synchronous digital hardware circuit;

a first digital-to-analog converter having an input coupled to an output of the series resistance compensation circuit in the processing circuit and an output coupled to a second input of the first amplifier; and

a second digital-to-analog converter having an input coupled to an output of a pipette compensation circuit in the processing circuit and an output coupled to the first terminal,

wherein the digital waveform generator, the series resistance compensation circuit, the pipette compensation circuit, and the whole cell compensation circuit are implemented on a field programmable gate array.

15. The electronic device of claim 14, wherein the first input of the first amplifier is an inverting input and the second input of the first amplifier is a non-inverting input.

16. The electronic device of claim 15, wherein an output of the second digital-to-analog converter is coupled to the first terminal via a first capacitor.

17. The electronic device of claim 16, further comprising a third digital-to-analog converter having an input coupled to an output of the whole-cell compensation circuit, wherein an output of the third digital-to-analog converter is coupled to the first terminal via a second capacitor.

18. The electronic device of claim 14, wherein the series resistance compensation circuit implements a first algorithm to predict and compensate for a series resistance of a cell, the pipette compensation circuit implements a second algorithm to compensate for a capacitance of a pipette and the whole cell compensation circuit implements a third algorithm to compensate for a capacitance of the cell.