CN108321193B - trench gate charge storage type IGBT and manufacturing method thereof - Google Patents
trench gate charge storage type IGBT and manufacturing method thereof Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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Abstract
a trench gate charge storage type IGBT belongs to the technical field of semiconductor power devices. According to the CSTBT device, the shielding groove structure with the same potential as the emitter metal is introduced on the basis of the traditional CSTBT device structure, and the groove depth of the shielding groove structure is larger than that of the charge storage layer, so that an electric field of the charge storage layer is shielded, the introduction of the shielding groove structure plays an effective charge compensation role for the charge storage layer, the limitation of the doping concentration and thickness of the charge storage layer on the withstand voltage of the device is further improved, and the breakdown voltage of the device is improved; the compromise relation between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the device is favorably improved, a wider short-circuit safe working area is obtained, the saturation current density of the device is favorably reduced, and the short-circuit safe working area of the device is further improved; in addition, the invention obviously reduces the grid capacitance of the device, especially the grid-collector capacitance, thereby improving the switching speed of the device, and reducing the switching loss of the device and the requirement on the capability of deleting the drive circuit.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a trench gate charge storage type insulated gate bipolar transistor (CSTBT).
Background
insulated Gate Bipolar Transistors (IGBTs) are widely used in various fields such as traffic, communication, household appliances, aerospace, and the like as one of the core electronic components in modern power electronic circuits. An Insulated Gate Bipolar Transistor (IGBT) is a novel power electronic device formed by compounding an insulated field effect transistor (MOSFET) and a Bipolar Junction Transistor (BJT), and can be equivalent to the MOSFET driven by the bipolar junction transistor. The IGBT combines the working mechanism of the MOSFET structure and the bipolar junction transistor, has the advantages of easy driving of the MOSFET, low input impedance and high switching speed, and also has the advantages of high on-state current density of the BJT, low on-state voltage, low loss and good stability. Thus, the use of IGBTs greatly improves the performance of power electronic systems.
after the development of IGBTs since the end of the 70 s and the beginning of the 80 s of the 20 th century, efforts have been made to improve the performance of IGBTs. Through development of thirty years, seven generations of IGBT device structures are successively proposed to improve the performance of the device. From non-punch-through (NPT) type IGBT structures with symmetric blocking characteristics to FS IGBT structures employing a field stop layer to reduce the drift region thickness and improve the device turn-on characteristics. In addition, a JFET (junction field effect transistor) region of the original plane gate IGBT structure is eliminated by adopting a trench gate IGBT structure, so that the on-resistance of the device is reduced, higher MOS (metal oxide semiconductor) structure channel density is obtained, and the characteristics of the device are obviously improved. The seventh generation IGBT structure, namely a trench gate charge storage type insulated gate bipolar transistor (CSTBT), introduces an N-type charge storage layer with higher doping concentration and certain thickness below a P-type base region, so that a hole potential barrier is introduced below the P-type base region, the hole concentration of a device close to an emitter terminal is greatly improved, the electron concentration is greatly increased according to the electric neutral requirement, the carrier concentration distribution of the whole N-drift region is improved, the conductivity modulation effect of the N-drift region is enhanced, and the IGBT obtains lower forward conduction voltage drop and better compromise between the forward conduction voltage drop and turn-off loss. The higher the doping concentration of the N-type charge storage layer is, the greater the CSTBT conductivity modulation effect is improved, and the better the forward conduction characteristic of the device is. However, with the increasing doping concentration of the N-type charge storage layer, the breakdown voltage of the csbt device is also significantly reduced, which causes the doping concentration and thickness of the N-type charge storage layer to be limited.
The IGBT is mainly applied in the medium-high voltage stage, and has a high breakdown voltage to ensure the reliability of the device, so that the CSTBT device is required to maintain a high breakdown voltage value while improving the turn-on characteristics. As shown in fig. 1, in order to effectively shield the adverse effect of the above N-type charge storage layer and further obtain a higher device withstand voltage, the following two methods are mainly adopted in the prior art:
(1) The depth of the trench gate is greater than the junction depth of the N-type charge storage layer under normal conditions;
(2) small cell width, i.e. making the MOS structure channel density large to obtain the smallest possible trench gate pitch.
However, the implementation of the above-mentioned means still has significant drawbacks: the implementation of the method (1) increases the gate-emitter capacitance and the gate-collector capacitance, and the switching process of the IGBT is essentially a process of charging/discharging the gate capacitance, so that the increase of the gate capacitance increases the charging/discharging time, and further decreases the switching speed. Therefore, the deep trench gate will reduce the switching speed of the device, increase the switching loss of the device, and affect the compromise characteristic of the conduction voltage drop and the switching loss of the device. On one hand, the implementation of the mode (2) can increase the grid capacitance of the device, so that the switching speed of the device is reduced, the switching loss is increased, and the compromise characteristic of the conduction voltage drop and the switching loss of the device is influenced; on the other hand, too high channel density will also result in increased saturation current density of the device, thus degrading the short-circuit safe operating area (SCSOA) of the device. In addition, the gate oxide layer used in the trench gate structure is usually formed in the trench by a thermal oxidation, which requires a smaller thickness of the entire gate oxide layer in order to ensure a certain threshold voltage. However, the size of the MOS capacitor in the device is inversely proportional to the thickness of the gate oxide layer, which results in a significant increase in the gate capacitance of the conventional CSTBT device, and in addition, the electric field concentration effect at the bottom of the trench also reduces the breakdown voltage of the device, resulting in poor reliability of the device.
disclosure of Invention
in view of the above, the present invention aims to: aiming at the defects in the prior art, a groove gate charge storage type IGBT and a manufacturing method thereof are provided, and the limitation of the doping concentration and thickness of a charge storage layer on the voltage resistance of a device is avoided by introducing a shielding groove structure for shielding an electric field of the charge storage layer, so that the breakdown voltage of the device is improved, the compromise relationship between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the device is improved, the switching performance of the device is improved, and the short-circuit safe working area of the device is improved; in addition, the preparation method provided by the invention is compatible with the traditional manufacturing method of the trench gate charge storage type IGBT.
in order to achieve the purpose, the invention adopts the following technical scheme:
in one aspect, the present invention provides a trench gate charge storage type IGBT, in which a fourth unit cell includes a collector metal 14, a first conductivity type semiconductor collector region 13, a second conductivity type semiconductor drift region 9, and an emitter metal 1, which are stacked in this order from bottom to top; the top layer of the second conductive type semiconductor drift region 9 is provided with a second conductive type semiconductor charge storage layer 6, a first conductive type semiconductor base region 5, a first conductive type semiconductor emitter region 4 and a second conductive type semiconductor emitter region 3 respectively; the first conductive type semiconductor base region 5 is positioned on the top layer of the second conductive type semiconductor charge storage layer 6; the first conduction type semiconductor emitter region 4 and the second conduction type semiconductor emitter region 3 are mutually independent and are arranged on the top layer of the first conduction type semiconductor base region 5 in parallel, and the upper surfaces of the first conduction type semiconductor emitter region 4 and the second conduction type semiconductor emitter region 3 are connected with the emitter metal 1; the method is characterized in that: the top layer of the second conductive type semiconductor drift region 9 is also provided with a trench gate structure and a shielding trench structure, and the trench gate structure and the shielding trench structure are not consistent along the extending direction of the top layer of the device; the trench gate structure comprises a gate electrode 81 and a gate dielectric layer 82, the gate electrode 81 downwards penetrates through the second conductive type semiconductor emitter region 3 and the first conductive type semiconductor base region 5 to enter the second conductive type semiconductor charge storage layer 6, namely the depth of the gate electrode 81 is smaller than the junction depth of the second conductive type semiconductor charge storage layer 6, the gate electrode 81 is connected with the second conductive type semiconductor emitter region 3, the first conductive type semiconductor base region 5 and the second conductive type semiconductor charge storage layer 6 through the gate dielectric layer 82, and the upper surface of the gate electrode 81 is connected with the emitter metal 1 through the isolation dielectric layer 2; the shielding trench structure comprises a shielding electrode 71 and a shielding trench dielectric layer 72, the shielding electrode 71 downwardly passes through the second conductive type semiconductor emitter region 3, the first conductive type semiconductor emitter region 4, the first conductive type semiconductor base region 5 and the second conductive type semiconductor charge storage layer 6 and enters the second conductive type semiconductor drift region 9, namely the depth of the shielding electrode 71 is larger than the junction depth of the second conductive type semiconductor charge storage layer 6, the shielding electrode 71 is isolated from the gate electrode 81 through the gate dielectric layer 82 or the shielding trench dielectric layer 72, the shielding electrode 71 is connected with the second conductive type semiconductor emitter region 3, the first conductive type semiconductor emitter region 4, the first conductive type semiconductor base region 5, the second conductive type semiconductor charge storage layer 6 and the second conductive type semiconductor drift region 9 through the shielding trench dielectric layer 72, the shield electrode 71 is equipotential with the emitter metal 1.
Further, a three-dimensional coordinate system is established by taking any inflection point of a quarter cell as an origin, two edges of the bottom surface of the quarter cell, which intersect at the inflection point, are respectively used as an x axis and a z axis, and a straight line passing through the inflection point and perpendicular to the bottom surface is used as a y axis, so that the gate electrode 81 extends from one end of the device to the other end along the x axis or the z axis, the shielding electrode 71 extends from one end of the device to the gate dielectric layer 82 on the side surface of the gate electrode 81 along the z axis or the x axis, and the extending directions of the gate electrode 81 and the shielding electrode 71 are not consistent.
Further, a three-dimensional coordinate system is established with any inflection point of a quarter cell as an origin, two sides of the bottom surface of the quarter cell, which intersect at the inflection point, are respectively used as an x axis and a z axis, and a straight line passing through the inflection point and perpendicular to the bottom surface is used as a y axis, so that the shielding electrode 71 extends from one end of the device to the other end along the x axis or the z axis, the gate electrode 81 extends from one end of the device to the shielding trench dielectric layer 72 on the side surface of the shielding electrode 71 along the z axis or the x axis, and the extending directions of the shielding electrode 71 and the gate electrode 81 are not consistent.
A depletion layer is formed when a PN junction formed by the second conductivity type semiconductor charge storage layer 6 and the first conductivity type semiconductor base region 5 is reverse biased, and fixed charges different from the free carrier conductivity type are respectively formed in the semiconductor layer: for an N-type semiconductor, positively charged ionization donors exist in a depletion layer, and for a P-type semiconductor, negatively charged ionization acceptors exist in the depletion layer; because the electrode in the shielding groove structure has the same electric potential as the emitter metal 1, the shielding groove structure can equivalently provide charges with the polarity opposite to that of the fixed charges in the charge storage layer, namely the fixed charges in the second conduction type semiconductor charge storage layer 6 are opposite to the type of the charges provided by the shielding groove structure, so that charge compensation is formed, a transverse electric field is formed between the second conduction type semiconductor charge storage layer 6 and the shielding groove structure to reduce the longitudinal electric field of the device, and the breakdown voltage of the device can be improved.
Further, there is a first conductive type semiconductor layer 10 at the bottom of the shield trench structure.
Further, the first conductivity type semiconductor layer 10 laterally extends to both sides into the second conductivity type semiconductor drift region 9 under the second conductivity type semiconductor charge storage layer 6.
Further, the trench gate structure has a first conductivity type semiconductor layer 11 at the bottom.
Further, the trench gate structure also has a split electrode 83 and a thick split electrode dielectric layer 84 therein, thereby forming a split trench gate structure.
further, the thickness of the split electrode dielectric layer 84 is greater than the thickness of the gate dielectric layer 82.
further, the split trench gate structure has a first conductivity type semiconductor layer 11 at the bottom.
further, the first conductivity type semiconductor layer 11 laterally extends to both sides into the second conductivity type semiconductor drift region 9 under the second conductivity type semiconductor charge storage layer 6.
further, a second conductivity type semiconductor field-resistance layer 12 is also provided between the first conductivity type semiconductor collector region 13 and the second conductivity type semiconductor drift region 9.
Further, since the above-mentioned charge compensation effect and the magnitude of the lateral electric field are related to the distance, in order to enhance the electric field shielding effect of the shielding trench structure on the second conductivity type semiconductor charge storage layer, a three-dimensional coordinate system is established with any inflection point of the quarter cell as an origin, two sides of the bottom surface of the quarter cell intersecting the inflection point are respectively used as an x axis and a z axis, and a straight line passing through the inflection point and perpendicular to the bottom surface is used as a y axis.
Further, in order to enhance the electric field shielding effect of the shielding trench structure on the second conductivity type semiconductor charge storage layer, reduce the extraction area of the emitter on the excess minority carrier in the drift region during forward conduction, reduce the gate capacitance, and improve the carrier concentration distribution in the drift region, preferably, the width of the shielding trench structure is greater than the width of the trench gate structure.
Further, the thickness of shield trench dielectric layer 72 is greater than the thickness of gate dielectric layer 82.
specifically, the first conductivity type semiconductor is a P-type semiconductor, and the second conductivity type semiconductor is an N-type semiconductor; or the first conductive type semiconductor is an N-type semiconductor and the second conductive type semiconductor is a P-type semiconductor.
Further, the semiconductor material used by the device is any one or more of Si, SiC, GaAs and GaN, and the structures can adopt the same semiconductor material or different semiconductor materials.
further, the gate electrode in the trench is any one or more of polysilicon, SiC, GaAs and GaN, and each portion can be made of the same material or different materials.
Further, the above-described device structure is applicable not only to IGBT devices but also to MOSFET devices by replacing the first conductivity type semiconductor collector region 14 of the back surface with a second conductivity type semiconductor layer.
on the other hand, the invention provides a manufacturing method of a trench gate charge storage type IGBT, which is characterized by comprising the following steps:
the method comprises the following steps: manufacturing a second conductive type semiconductor drift region;
step two: manufacturing a second conductive type semiconductor charge storage layer 6 and a first conductive type semiconductor base region 5 positioned on the top layer of the second conductive type semiconductor charge storage layer 6 on the front surface of the second conductive type semiconductor drift region through pre-oxidation, photoetching, etching, ion implantation and high-temperature annealing processes;
step three: etching to form a first groove on the second conductive type semiconductor drift region 9 through photoetching, etching, thermal oxidation and deposition processes, wherein the depth of the first groove is greater than the junction depth of the second conductive type semiconductor charge storage layer 6 and extends along the transverse direction of the top layer of the device; forming a shielding groove dielectric layer 72 on the inner wall of the first groove, then depositing an electrode material in the second groove to form a shielding electrode 71, wherein the shielding electrode 71 and the shielding groove dielectric layer 72 on the peripheral side form a shielding groove structure;
Step four: etching a second groove on the second conductive type semiconductor charge storage layer 6 through photoetching, etching, thermal oxidation and deposition processes, wherein the depth of the second groove is smaller than the junction depth of the second conductive type semiconductor charge storage layer 6 and extends along the longitudinal direction of the top layer of the device, and the first groove is not communicated with the second groove; forming a gate dielectric layer 82 on the inner wall of the first trench, then depositing a gate electrode material in the trench to form a gate electrode 81, wherein the gate electrode 81 and the gate dielectric layer 82 on the peripheral side form a trench gate structure;
step five: manufacturing a first conductive type semiconductor emitter region 4 and a second conductive type semiconductor emitter region 3 which are mutually independent and arranged in parallel on the top layer of the first conductive type semiconductor base region 5 through photoetching, etching, ion implantation and high-temperature annealing processes; one side of the second conductive type semiconductor emitting region 3 is connected with the gate electrode 81 through the gate dielectric layer 82 along the longitudinal direction of the top layer of the device, the other side of the second conductive type semiconductor emitting region is connected with the shielding electrode 71 through the shielding groove dielectric layer 72 along the transverse direction of the top layer of the device, and one side of the first conductive type semiconductor emitting region 4 is connected with the shielding electrode 71 through the shielding groove dielectric layer 72 along the transverse direction of the top layer of the device;
Step six: forming an isolation dielectric layer 2 on the upper surfaces of the gate electrode 81 and the gate dielectric layer 82 through photoetching, etching and deposition processes;
Step seven: depositing metal on the surface, and forming emitter metal 1 on the isolation dielectric layer 2, the second conductive type semiconductor emitting region 3, the first conductive type semiconductor emitting region 4, the shielding electrode 71 and the shielding groove dielectric layer 72 through photoetching and etching processes;
step eight: turning over the semiconductor device, reducing the thickness of the semiconductor, and injecting first conductive type impurities into the back of the drift region of the second conductive type semiconductor through ion injection and high-temperature annealing processes to form a first conductive type semiconductor collector region 13;
Step nine: back-side deposition of metal, forming a collector metal 14 on the first conductivity type semiconductor collector region 13; thus, the trench gate charge storage type IGBT device is manufactured.
Further, the order of forming the trench gate structure and the shield trench structure may be interchanged.
further, the following steps are included before forming the first conductivity type semiconductor collector region 13: second conductivity type impurities are implanted into the back surface of the second conductivity type semiconductor drift region to form a second conductivity type semiconductor field stop layer 12.
further, the order of forming the trench gate structure and forming the second conductivity type semiconductor charge storage layer 6 and the first conductivity type semiconductor base region 5 may be exchanged.
Further, by changing the trenching manner, the trench gate structure extends from one end of the device to the other end of the device along the surface of the device and blocks the extension of the shielding trench structure along the surface of the device or the shielding trench structure extends from one end of the device to the other end of the device along the surface of the device and blocks the extension of the trench gate structure along the surface of the device.
Specifically, the first conductivity type semiconductor is a P-type semiconductor, and the second conductivity type semiconductor is an N-type semiconductor; or the first conductive type semiconductor is an N-type semiconductor and the second conductive type semiconductor is a P-type semiconductor.
further, the semiconductor material used by the device is any one or more of Si, SiC, GaAs and GaN, and the structures can adopt the same semiconductor material or different semiconductor materials.
Further, the gate electrode in the trench is any one or more of polysilicon, SiC, GaAs and GaN, and each portion can be made of the same material or different materials.
The working principle of the invention is detailed as follows:
Based on the structure design, the position relation of the shielding groove structure and the groove grid structure on the three-dimensional space provided by the invention is different from that of the existing structure in that the shielding groove structure and the groove grid structure extend in parallel, a depletion layer is formed when PN junctions formed by the charge storage layer and the base region are reversely biased, fixed charges different from the free carrier conduction type of the charge storage layer are respectively formed in a semiconductor layer, and the shielding groove structure can equivalently provide charges with the conduction type opposite to that of the fixed charges in the charge storage layer due to the equipotential of an electrode and an emitter metal in the shielding groove structure, therefore, the three-dimensional design of the shielding groove structure and the groove gate structure provided by the invention can play a role in charge compensation on the charge storage layer, so that the electric field of the charge storage layer is effectively shielded, the limit of the doping concentration and thickness of the charge storage layer on the withstand voltage of the device is further improved, and the aim of improving the breakdown voltage of the device is fulfilled. In addition, the dielectric layer of the inner wall of the groove of the shielding groove structure can be thickened, so that the electric field concentration effect can be relieved, and the breakdown voltage of the device can be further improved. Just because the doping concentration and thickness of the charge storage layer of the charge compensation effect of the shielding groove structure limit the voltage resistance of the device, the carrier concentration distribution of the drift region of the device can be improved by improving the doping concentration and thickness of the charge storage layer by adopting the device structure provided by the invention, so that the compromise relationship between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the device is improved, and a wider short circuit safe working region (SCSOA) is obtained; meanwhile, the device structure provided by the invention can avoid large MOS structure channel density, is beneficial to reducing the saturation current density of the device, and can further improve the Short Circuit Safe Operating Area (SCSOA) of the device. In addition, the effective contact area between the trench gate structure and the collector region and the effective contact area between the trench gate structure and the emitter region are reduced due to the existence of the shielding trench structure, and the large grid-emitter capacitance formed by the trench gate structure and the shielding trench structure is connected in parallel to reduce the grid-emitter capacitance, so that the whole grid-collector capacitance and the whole grid-emitter capacitance are reduced, the switching speed of the device is increased, the switching loss of the device and the requirement on the capacity of a gate driving circuit are reduced, and the compromise between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the device is further improved. Furthermore, the invention reduces the groove depth of the groove gate structure to be smaller than the junction depth of the charge storage layer, thereby further reducing the capacitance of a grid electrode and a collector electrode, improving the switching speed of the device, and reducing the conduction loss Eon of the device and the requirement on the capacity of a gate drive circuit. The existence of the further shielding groove structure reduces the extraction area of the emitter to the excessive minority carriers in the drift region when the emitter is conducted in the forward direction, reduces the capacitance of the grid electrode, improves the carrier concentration distribution of the drift region, and further improves the compromise relation between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the device. In addition, the manufacturing method provided by the invention does not need to add extra process steps and is compatible with the traditional manufacturing method of the trench gate charge storage type IGBT.
Compared with the prior art, the invention has the beneficial effects that:
The invention avoids the limit of the doping concentration and thickness of the charge storage layer on the voltage resistance of the device, not only improves the breakdown voltage of the device and the reliability of the device, but also obviously improves the concentration distribution of carriers removed by the device, thereby improving the compromise relationship between the forward conduction voltage drop Vceon and the turn-off loss Eoff; the invention avoids overlarge channel density of the MOS structure of the device, thereby reducing the saturation current density of the device and improving the short circuit safe working area (SCSOA) of the device; the invention obviously reduces the grid capacitance of the device, particularly the grid-collector capacitance, thereby improving the switching speed of the device, reducing the switching loss of the device and the requirement on the capability of deleting a driving circuit, and further improving the compromise relationship between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the device. In addition, the manufacturing method provided by the invention does not need to add extra process steps and is compatible with the manufacturing process of the traditional trench gate charge storage type IGBT device.
drawings
Fig. 1 is a schematic structural diagram of a quarter cell of a conventional trench gate charge storage type IGBT device;
FIG. 2 is a schematic structural diagram of a conventional trench gate charge storage type IGBT device before an isolation dielectric layer and an emitter metal are formed during front structure manufacturing;
Fig. 3 is a schematic cross-sectional view of a quarter cell structure of a conventional trench gate charge storage type IGBT device along line AB in fig. 1;
Fig. 4 is a schematic structural diagram of a quarter cell of a trench gate charge storage type IGBT device according to embodiment 1 of the present invention;
fig. 5 is a schematic structural diagram of a trench gate charge storage type IGBT device according to embodiment 1 before forming an isolation dielectric layer and an emitter metal during fabrication of a front structure;
fig. 6 is a schematic cross-sectional view of a quarter cell structure of a trench gate charge storage type IGBT device according to embodiment 1 of the present invention, taken along line AB in fig. 4;
fig. 7 is a schematic cross-sectional view of a quarter cell structure of a trench gate charge storage type IGBT device according to embodiment 1 of the present invention, taken along the line a 'B' in fig. 4;
Fig. 8 is a schematic structural diagram of a quarter cell of a trench gate charge storage type IGBT device according to embodiment 2 of the present invention;
Fig. 9 is a schematic structural diagram of a trench gate charge storage type IGBT device according to embodiment 2 before forming an isolation dielectric layer and an emitter metal during fabrication of a front structure;
fig. 10 is a schematic cross-sectional view of a quarter cell structure of a trench gate charge storage type IGBT device according to embodiment 2 of the present invention, taken along line AB in fig. 8;
fig. 11 is a schematic cross-sectional view of a quarter cell structure of a trench gate charge storage type IGBT device according to embodiment 2 of the present invention, taken along the line a 'B' in fig. 8;
Fig. 12 is a schematic structural diagram of a quarter cell of a trench gate charge storage type IGBT device according to embodiment 3 of the present invention;
fig. 13 is a schematic structural diagram of a trench gate charge storage type IGBT device according to embodiment 3 before forming an isolation dielectric layer and an emitter metal during fabrication of a front structure;
Fig. 14 is a schematic cross-sectional view of a quarter cell structure of a trench gate charge storage type IGBT device according to embodiment 3 of the present invention, taken along line AB in fig. 12;
fig. 15 is a schematic cross-sectional view of a quarter cell structure of a trench gate charge storage type IGBT device according to embodiment 3 of the present invention, taken along the line a 'B' in fig. 12;
Fig. 16 is a schematic structural diagram of a quarter cell of a trench gate charge storage type IGBT device according to embodiment 4 of the present invention;
fig. 17 is a schematic structural diagram of a trench gate charge storage type IGBT device according to embodiment 4 before forming an isolation dielectric layer and an emitter metal during fabrication of a front structure;
Fig. 18 is a schematic sectional view of a quarter cell structure of a trench gate charge storage type IGBT device according to embodiment 4 of the present invention, taken along line AB in fig. 16;
fig. 19 is a schematic sectional view of a quarter cell structure of a trench gate charge storage type IGBT device according to embodiment 4 of the present invention, taken along the line a 'B' in fig. 16;
Fig. 20 is a schematic structural diagram of a quarter cell of a trench gate charge storage type IGBT device according to embodiment 5 of the present invention;
fig. 21 is a schematic structural diagram of a trench gate charge storage type IGBT device according to embodiment 5 before forming an isolation dielectric layer and an emitter metal during fabrication of a front structure;
Fig. 22 is a schematic cross-sectional view of a quarter cell structure of a trench gate charge storage type IGBT device according to embodiment 5 of the present invention, taken along line AB in fig. 20;
fig. 23 is a schematic sectional view of a quarter cell structure of a trench gate charge storage type IGBT device according to embodiment 5 of the present invention, taken along the line a 'B' in fig. 20;
Fig. 24 is a schematic structural diagram of a quarter cell of a trench gate charge storage type IGBT device according to embodiment 6 of the present invention;
Fig. 25 is a schematic structural diagram of a trench gate charge storage type IGBT device according to embodiment 6 before forming an isolation dielectric layer and an emitter metal during fabrication of a front structure;
fig. 26 is a schematic sectional view of a quarter cell structure of a trench gate charge storage type IGBT device according to embodiment 6 of the present invention, taken along line AB in fig. 24;
fig. 27 is a schematic sectional view of a quarter cell structure of a trench gate charge storage type IGBT device according to embodiment 6 of the present invention, taken along the line a 'B' in fig. 24;
Fig. 28 is a schematic diagram of a quarter cell structure after a trench of a shielded trench structure is formed in a trench gate charge storage type IGBT device according to embodiment 1 of the present invention;
fig. 29 is a schematic structural diagram of a quarter cell after a trench gate charge storage type IGBT device according to embodiment 1 of the present invention forms a shield trench dielectric layer;
Fig. 30 is a schematic diagram of a quarter cell structure of a trench gate charge storage type IGBT device provided in embodiment 1 of the present invention after forming a shield electrode;
Fig. 31 is a schematic diagram of a quarter cell structure after a trench gate structure is formed in a trench gate IGBT device according to embodiment 1 of the present invention;
Fig. 32 is a schematic diagram of a quarter cell structure after a gate dielectric layer is formed on a trench gate charge storage type IGBT device according to embodiment 1 of the present invention;
fig. 33 is a schematic diagram of a quarter cell structure after a gate electrode is formed on a trench gate charge storage type IGBT device according to embodiment 1 of the present invention;
fig. 34 is a schematic diagram of a quarter cell structure after an N + emitter region and a P + emitter region are formed in a trench gate charge storage type IGBT device according to embodiment 1 of the present invention;
fig. 35 is a schematic diagram of a quarter cell structure after an isolation dielectric layer is formed on a trench gate charge storage type IGBT device according to embodiment 1 of the present invention;
fig. 36 is a schematic diagram of a quarter cell structure after all the processes of the trench gate charge storage type IGBT device according to embodiment 1 of the present invention are completed;
Fig. 37 is a schematic diagram of a quarter cell structure after a trench gate structure is formed on a trench gate IGBT device according to embodiment 3 of the present invention;
Fig. 38 is a schematic diagram of a quarter cell structure after a gate dielectric layer is formed on a trench gate charge storage type IGBT device according to embodiment 3 of the present invention;
Fig. 39 is a schematic diagram of a quarter cell structure after a gate electrode is formed on a trench gate charge storage type IGBT device according to embodiment 3 of the present invention;
fig. 40 is a schematic diagram of a quarter cell structure after a trench of a shielded trench structure is formed in a trench gate charge storage type IGBT device according to embodiment 3 of the present invention;
fig. 41 is a schematic diagram of a quarter cell structure after a P-type layer is formed on a trench gate charge storage type IGBT device according to embodiment 3 of the present invention;
fig. 42 is a schematic diagram of a quarter cell structure after a trench gate charge storage type IGBT device according to embodiment 3 of the present invention forms a shielding trench dielectric layer;
fig. 43 is a schematic diagram of a quarter cell structure of a trench gate charge storage type IGBT device provided in embodiment 3 of the present invention after forming a shielding electrode;
fig. 44 is a schematic diagram of a quarter cell structure after an N + emitter region and a P + emitter region are formed in a trench gate charge storage type IGBT device according to embodiment 3 of the present invention;
fig. 45 is a schematic diagram of a quarter cell structure after an isolation dielectric layer is formed on a trench gate charge storage type IGBT device according to embodiment 3 of the present invention;
Fig. 46 is a schematic diagram of a quarter cell structure after all the processes of a trench gate charge storage type IGBT device according to embodiment 3 of the present invention are completed;
in the figure: the structure comprises a substrate, a substrate.
Detailed Description
The principles and features of the present invention are explained in detail below in conjunction with the drawings and the detailed description of the invention:
In the drawings, the same reference numerals denote the same or similar components or elements. The trench gate charge storage type IGBT device provided by the invention can be an N-channel device and can also be a P-channel device, the N-channel device is taken as an example for explanation, and the structure and the working principle of the P-channel device can be clear to those skilled in the art on the basis of disclosing the N-channel device.
Example 1:
the invention provides a trench gate charge storage type IGBT, wherein a quarter cell of the IGBT is shown in figure 4, a section along an AB line and an A 'B' line is shown in figures 6 and 7, a three-dimensional coordinate system is established by taking any inflection point of the quarter cell as an origin, two sides of the bottom surface of the quarter cell, which intersect at the inflection point, are respectively taken as an x axis and a z axis, a straight line passing through the inflection point and perpendicular to the bottom surface is taken as a y axis, and the directions of the x axis, the y axis and the z axis are shown in figure 4;
the quarter-cell comprises collector metal 14, a P-type collector region 13, an N-type drift region 9 and emitter metal 1 which are sequentially stacked from bottom to top; the top layer of the N-type drift region 9 is provided with an N-type charge storage layer 6, a P-type base region 5, a P + emission region 4 and an N + emission region 3 respectively; the P-type base region 5 is positioned on the upper surface of the N-type charge storage layer 6; the P + emitter region 4 and the N + emitter region 3 are mutually independent and are positioned on the upper surface of the P-type base region 5 in parallel, and the upper surfaces of the P + emitter region 4 and the N + emitter region 3 are connected with the emitter metal 1; the method is characterized in that: the top layer of the N-type drift region 9 is provided with a trench gate structure, the trench gate structure comprises a gate electrode 81 and a gate dielectric layer 82, the gate electrode 81 downwards penetrates through the N + emission region 3 and the P-type base region 5 to enter the N-type charge storage layer 6, namely the depth of the gate electrode 81 is smaller than the junction depth of the N-type charge storage layer 6, the gate electrode 81 extends from one end of the device to the other end along the z axis, the gate electrode 81 is connected with the N + emission region 3, the P-type base region 5 and the N-type charge storage layer 6 through the gate dielectric layer 82, and the upper surface of the gate electrode 81 is connected with the emitter metal 1 through the isolation dielectric; the top layer of the N-type drift region 9 is also provided with a shielding groove structure, the shielding groove structure comprises a shielding electrode 71 and a shielding groove dielectric layer 72, the shielding electrode 71 downwards penetrates through the P + emission region 4, the P-type base region 5 and the N-type charge storage layer 6 to enter the N-type drift region 9, namely the depth of the shielding electrode 71 is larger than the junction depth of the N-type charge storage layer 6, the shielding electrode 71 extends to a gate dielectric layer 82 on the side surface of a gate electrode 81 from one end of a device along an x axis, the shielding electrode 71 is isolated from the gate electrode 81 through the gate dielectric layer 82, the shielding electrode 71 is connected with the N + emission region 3, the P + emission region 4, the P-type base region 5, the N-type charge storage layer 6 and the N-type drift region 9 through the shielding groove dielectric layer 72, and the shielding electrode 71.
in the embodiment, the size of the P + emission region 4 along the z-axis direction is 0.2-0.5 μm, and the size along the y-axis direction, namely, the junction depth is 0.1-0.3 μm; the size of the P-type base region 5 along the x-axis direction is 2-10 mu m, and the size along the y-axis, namely the junction depth, is 0.3-1 mu m; the size of the N-type charge storage layer 6 along the y axis, namely the junction depth, is 0.5-1 mu m; the groove depth of the groove gate structure is 0.6-3 mu m; the groove depth of the shielding groove structure is 4-8 mu m.
The position relation of the shielding groove structure and the groove gate structure in the three-dimensional space provided by the structure of the embodiment is different from that of the two structures in the existing structure which extend in parallel, the electrode in the shielding groove structure and the emitting electrode metal are equipotential and can equivalently provide negative charges, when a PN junction formed by the N-type charge storage layer 6 and the P-type base region 5 is reversely biased, the positively charged ionization donor in the N-type charge storage layer 6 and the negative charges in the shielding groove form charge compensation, and the positively charged ionization donor generates a transverse electric field pointing to the negative charges at the moment so as to reduce a longitudinal electric field of the device, and meanwhile, the gate electrode 81 is exposed on an xoy surface of the device, so that the electrode is favorably.
example 2:
the invention provides a trench gate charge storage type IGBT, wherein a quarter cell of the IGBT is shown in figure 8, a section along an AB line and an A 'B' line is shown in figures 10 and 11, a three-dimensional coordinate system is established by taking any inflection point of the quarter cell as an origin, two sides of the bottom surface of the quarter cell, which intersect at the inflection point, are respectively taken as an x axis and a z axis, a straight line passing through the inflection point and perpendicular to the bottom surface is taken as a y axis, and the directions of the x axis, the y axis and the z axis are shown in figure 8;
the present implementation differs from example 1 in that: the first P-type layer 10 is introduced to the bottom of the shielding trench structure, and the first P-type layer 10 is connected to the shielding electrode 71 through the shielding electrode dielectric layer 72, except that the other structures are the same as those in embodiment 1, in this embodiment, the junction depth of the first P-type layer 10 is 0.5 to 1 μm.
as a preferred embodiment, the first P-type layer 10 extends laterally into the N-type drift region 9 below the N-type charge storage layer 6 towards two sides, so as to shield the influence of negative charges in the N-type charge storage layer 6, further reduce the gate capacitance, and also contribute to improving the electric field concentration at the bottom of the trench, thereby improving the breakdown voltage and reliability of the device.
Example 3:
The invention provides a trench gate charge storage type IGBT, wherein a quarter cell of the IGBT is shown in figure 12, a section along an AB line and an A 'B' line is shown in figures 14 and 15, a three-dimensional coordinate system is established by taking any inflection point of the quarter cell as an origin, two sides of the bottom surface of the quarter cell, which intersect at the inflection point, are respectively taken as an x axis and a z axis, a straight line passing through the inflection point and perpendicular to the bottom surface is taken as a y axis, and the directions of the x axis, the y axis and the z axis are shown in figure 12;
The present implementation differs from example 2 in that: the structure of shield electrode 71 is the same as that of embodiment 2, except that shield electrode 71 extends from one end of the device to the other end along the x-axis, gate electrode 81 extends from one end of the device to shield trench dielectric layer 72 on the side of shield electrode 71 along the z-axis, and shield electrode 71 and gate electrode 81 are connected by shield trench dielectric layer 72.
According to the embodiment, the depth of the groove gate structure extending along the z-axis direction is reduced, so that the channel density of the MOS structure is reduced, the saturation current density of the device is reduced, and the SCSOA (short-circuit safe operating area) characteristic of the device is improved.
Example 4:
the invention provides a trench gate charge storage type IGBT, wherein a quarter cell of the IGBT is shown in figure 16, a section along an AB line and an A 'B' line is shown in figures 18 and 19, a three-dimensional coordinate system is established by taking any inflection point of the quarter cell as an origin, two sides of the bottom surface of the quarter cell, which intersect at the inflection point, are respectively taken as an x axis and a z axis, a straight line passing through the inflection point and perpendicular to the bottom surface is taken as a y axis, and the directions of the x axis, the y axis and the z axis are shown in figure 16;
the present implementation differs from example 3 in that: the bottom of the trench gate structure is introduced with a second P-type layer 11, the second P-type layer 11 is connected with a gate electrode 81 through a gate dielectric layer 82, and other structures are the same as those in embodiment 3, in this embodiment, the junction depth of the second P-type layer 11 is 0.5 to 1 μm.
as a preferred embodiment, the second P-type layer 11 laterally extends into the N-type drift region 9 below the N-type charge storage layer 6 towards two sides, so as to shield the influence of negative charges in the N-type charge storage layer 6, further reduce the gate capacitance, and also contribute to improving the electric field concentration at the bottom of the trench, thereby improving the breakdown voltage and reliability of the device.
Example 5:
the invention provides a trench gate charge storage type IGBT, wherein a quarter cell of the IGBT is shown in figure 20, a section along an AB line and an A 'B' line is shown in figures 22 and 23, a three-dimensional coordinate system is established by taking any inflection point of the quarter cell as an origin, two sides of the bottom surface of the quarter cell, which intersect at the inflection point, are respectively taken as an x axis and a z axis, a straight line passing through the inflection point and perpendicular to the bottom surface is taken as a y axis, and the directions of the x axis, the y axis and the z axis are shown in figure 20;
the present implementation differs from example 3 in that: a split electrode 83 and a thick split electrode dielectric layer 84 are introduced into the trench gate structure, the split electrode 83 and the emitter metal 1 are equipotential, and the thickness of the split electrode dielectric layer 84 is larger than that of the gate dielectric layer 82. The embodiment reduces the gate capacitance of the device by introducing the split electrode 83, thereby improving the switching speed of the device and reducing the switching loss, and the thick split electrode dielectric layer improves the breakdown voltage of the device and improves the reliability of the device.
example 6:
The invention provides a trench gate charge storage type IGBT, wherein a quarter cell of the IGBT is shown in figure 24, a section along an AB line and an A 'B' line is shown in figures 26 and 27, a three-dimensional coordinate system is established by taking any inflection point of the quarter cell as an origin, two sides of the bottom surface of the quarter cell, which intersect at the inflection point, are respectively taken as an x axis and a z axis, a straight line passing through the inflection point and perpendicular to the bottom surface is taken as a y axis, and the directions of the x axis, the y axis and the z axis are shown in figure 24;
The present implementation differs from example 5 in that: and a second P-type layer 11 is introduced into the bottom of the split trench gate structure, the second P-type layer 11 is connected with a split electrode 83 through a split electrode dielectric layer 84, and the junction depth of the second P-type layer 11 is 0.5-1 mu m. This example combines the features and superior characteristics of examples 4 and 5.
Example 7:
In this embodiment, a trench gate charge storage IGBT with a voltage level of 1200V is taken as an example for explanation, and devices with different performance parameters can be prepared according to actual requirements based on common knowledge in the art.
a manufacturing method of a trench gate charge storage type IGBT is characterized by comprising the following steps:
Step 1, adopting an N-type lightly doped monocrystalline silicon wafer as an N-type drift region 9 of a device, wherein the thickness of the selected silicon wafer is 300-600 mu m, and the doping concentration is 10 13 -10 14/cm 3;
Step 2, growing a field oxide layer on the surface of a silicon wafer, photoetching to obtain an active region, growing a pre-oxide layer, implanting N-type impurities by ions to obtain an N-type charge storage layer 6, wherein the energy of the ion implantation is 200-500 keV, and the implantation dosage is 10 13 -10 14/cm 2, implanting P-type impurities by ions above the N-type charge storage layer 6, annealing to obtain a P-type base region 5, wherein the energy of the ion implantation is 60-120 keV, the implantation dosage is 10 13 -10 14/cm 2, the annealing temperature is 1100-1150 ℃, and the annealing time is 10-30 minutes;
and step 3: depositing a TEOS protective layer with the thickness of 700-1000 nm on the surface of a silicon wafer, photoetching a window to perform groove silicon etching, and further etching on an N-type drift region 9 to form a first groove, wherein as shown in figure 16, the first groove extends from the right end of a device to the left end of the device, and the depth of the first groove is greater than the junction depth of an N-type charge storage layer 6;
Step 4, forming a dielectric layer on the inner wall of the first trench as a shielding electrode dielectric layer 72 at 1050-1150 ℃ in O 2 atmosphere, as shown in FIG. 17, and then depositing a shielding electrode material in the first trench at 750-950 ℃ to form a shielding electrode 71, wherein the embodiment adopts a polysilicon material as the shielding electrode material, the shielding electrode 71 in the first trench and the shielding electrode dielectric layer 72 on the peripheral side thereof form a shielding trench structure which shields the electric field of the N-type charge storage layer 6, and the shielding trench structure is as shown in FIG. 18;
and 5: depositing a TEOS protective layer with the thickness of 700-1000 nm on the surface of a silicon wafer, photoetching a window to perform groove silicon etching, and further etching on the N-type drift region 9 to form a second groove, wherein the second groove extends from the front end to the rear end of the device as shown in figure 19; the depth of the second groove is smaller than the junction depth of the N-type charge storage layer 6;
Step 6, forming a dielectric layer on the inner wall of the second trench as a gate dielectric layer 82 in an O 2 atmosphere at 1050-1150 ℃, as shown in fig. 20, wherein the second trench is spatially perpendicular to and not communicated with the first trench, and the second trench is isolated from the first trench by the gate dielectric layer 82, and then depositing a gate electrode material in the second trench as a gate electrode 81 at 750-950 ℃, in the embodiment, a polysilicon material is used as the gate electrode material, the gate electrode 81 and the gate dielectric layer 82 in the second trench form a trench gate structure, and the trench gate structure is shown in fig. 21;
Step 7, respectively injecting N-type impurities and P-type impurities into the top layer of a P-type base region 5 between a first groove and a second groove through photoetching and ion injection processes, wherein the energy of the N-type impurities injected by ions is 30-60 keV, the injection dosage is 10 15 -10 16/cm 2, the energy of the P-type impurities injected by ions is 60-80 keV, the injection dosage is 10 15 -10 16/cm 2, the annealing temperature is 900 ℃, the time is 20-30 minutes, and an N + emission region 3 and a P + emission region 4 which are mutually contacted and arranged in parallel are prepared;
and 8: as shown in fig. 23, a dielectric layer is deposited on the surface of the device, and an isolation dielectric layer 2 is formed on the upper surfaces of the gate electrode 81 and the gate dielectric layer 82 by using photolithography and etching processes;
and step 9: depositing metal on the surface of the device, and forming emitter metal 1 on the isolation dielectric layer 2, the N + emitter region 3, the P + emitter region 4, the shielding electrode 71 and the shielding groove dielectric layer 72 by adopting photoetching and etching processes;
step 10, turning over the silicon wafer, reducing the thickness of the silicon wafer, injecting N-type impurities into the back of the silicon wafer, annealing to manufacture an N-type field stop layer 12 of the device, wherein the thickness of the N-type field stop layer 12 is 15-30 microns, the ion injection energy is 1500-2000 keV, the injection dosage is 10 13 -10 14/cm 2, the annealing temperature is 1200-1250 ℃, the annealing time is 300-600 minutes, injecting P-type impurities into the back of the N-type field stop layer 12 to form a P-type collector region 13, the injection energy is 40-60 keV, the injection dosage is 10 12 -10 13/cm 2, carrying out back annealing in the mixed atmosphere of H 2 and N 2, the back annealing temperature is 400-450 ℃, the back annealing time is 20-30 minutes, depositing metal on the back to form collector metal 14, and finishing the preparation of the trench gate charge storage type IGBT as shown in figure 24.
It should be noted that, in the manufacturing method provided in this embodiment, the lateral position of the device surface corresponds to the x-axis direction of the coordinate system shown in the drawings of the specification, and the longitudinal position of the device surface corresponds to the z-axis direction of the coordinate system shown in the drawings of the specification, which is not described in detail below.
further, the order of forming the trench gate structure and the shield trench structure in the present invention may be switched.
further, the order of forming the trench structure and forming the N-type charge storage layer 6 and the P-type base region 5 in the present invention may be interchanged.
Further, as shown in fig. 25 to 34, in the present invention, by changing the trench digging manner, the shielding electrode 71 in the shielding trench structure extends from one end to the other end along the transverse direction of the device top layer, such as the x-axis direction in fig. 12, while the gate electrode 81 in the trench gate structure extends from one end to the shielding trench dielectric layer 72 along the longitudinal direction of the device top layer, such as the z-axis direction in fig. 12, and the gate electrode 81 and the shielding electrode 71 are both isolated by the shielding trench dielectric layer 72.
Further, in step 4 of the present invention, an ion implantation step may be added to form the first P-type layer 10 at the bottom of the shielding trench structure, so as to obtain the device structure as illustrated in embodiment 2.
Further, the preparation of the N-type field stop layer 12 in step 10 of the present invention may be performed before the front structure of the device is prepared; or directly selecting a double-layer epitaxial material with the N-type field stop layer 12 and the N-type drift region 9 as a silicon wafer material for starting the process.
Further, the preparation of the N-type field stop layer 12 in step 10 of the present invention can also be omitted.
furthermore, the materials of the isolation dielectric layer 2, the shielding trench dielectric layer 72 and the gate dielectric layer 82 may be the same material or different materials.
Further, the device structure and the manufacturing method are described by taking an N-channel IGBT device as an example, but the present invention is also applicable to the manufacturing of a P-channel IGBT device, and details are not described herein.
the above is a preferred embodiment of the present invention, and various changes and modifications can be made by those skilled in the art without departing from the technical spirit of the present invention from the above description. Therefore, the technical scope of the present invention is not limited to the content of the specification, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.
Claims (10)
1. a trench gate charge storage type IGBT is characterized in that a fourth unit cell comprises a collector metal (14), a first conduction type semiconductor collector region (13), a second conduction type semiconductor drift region (9) and an emitter metal (1) which are sequentially stacked from bottom to top; the second conduction type semiconductor drift region (9) is respectively provided with a second conduction type semiconductor charge storage layer (6), a first conduction type semiconductor base region (5) arranged on the top layer of the second conduction type semiconductor charge storage layer (6), a first conduction type semiconductor emission region (4) arranged on the top layer of the first conduction type semiconductor base region (5) and a second conduction type semiconductor emission region (3), wherein: the first conduction type semiconductor emitter region (4) and the second conduction type semiconductor emitter region (3) are mutually independent and are arranged on the top layer of the first conduction type semiconductor base region (5) in parallel, and the upper surfaces of the first conduction type semiconductor emitter region (4) and the second conduction type semiconductor emitter region (3) are connected with the emitter metal (1); the method is characterized in that: the top layer of the second conduction type semiconductor drift region (9) is also provided with a trench gate structure and a shielding trench structure, and the trench gate structure and the shielding trench structure are not consistent along the extending direction of the top layer of the device; the trench gate structure comprises a gate electrode (81) and a gate dielectric layer (82), the gate electrode (81) downwards penetrates through the second conductive type semiconductor emission region (3) and the first conductive type semiconductor base region (5) to enter the second conductive type semiconductor charge storage layer (6), the gate electrode (81) is connected with the second conductive type semiconductor emission region (3), the first conductive type semiconductor base region (5) and the second conductive type semiconductor charge storage layer (6) through the gate dielectric layer (82), and the upper surface of the gate electrode (81) is connected with the emitter metal (1) through the dielectric layer (2); the shielding trench structure comprises a shielding electrode (71) and a shielding trench dielectric layer (72), wherein the shielding electrode (71) downwards passes through the second conductive type semiconductor emitter region (3), the first conductive type semiconductor emitter region (4), the first conductive type semiconductor base region (5) and the second conductive type semiconductor charge storage layer (6) and enters the second conductive type semiconductor drift region (9), the shielding electrode (71) is isolated from the gate electrode (81) through the gate dielectric layer (82) or the shielding trench dielectric layer (72), the shielding electrode (71) is connected with the second conductive type semiconductor emitter region (3), the first conductive type semiconductor emitter region (4), the first conductive type semiconductor base region (5), the second conductive type semiconductor charge storage layer (6) and the second conductive type semiconductor drift region (9) through the shielding trench dielectric layer (72), the shield electrode (71) is at the same potential as the emitter metal (1).
2. the trench gate charge storage IGBT of claim 1, wherein: the first conductive type semiconductor is a P-type semiconductor, and the second conductive type semiconductor is an N-type semiconductor; or the first conductive type semiconductor is an N-type semiconductor and the second conductive type semiconductor is a P-type semiconductor.
3. the trench gate charge storage IGBT of claim 2, wherein: a three-dimensional coordinate system is established by taking any inflection point of a quarter cell as an origin, two edges of the bottom surface of the quarter cell, which intersect at the inflection point, are respectively used as an x axis and a z axis, a straight line which passes through the inflection point and is perpendicular to the bottom surface is used as a y axis, a gate electrode (81) extends from one end of a device to the other end along the x axis or the z axis, a shielding electrode (71) extends from one end of the device to a gate dielectric layer (82) on the side surface of the gate electrode (81) along the z axis or the x axis, and the extending directions of the gate electrode (81) and the shielding electrode (71) are inconsistent.
4. The trench gate charge storage IGBT of claim 2, wherein: a three-dimensional coordinate system is established by taking any inflection point of a quarter cell as an origin, two sides of the bottom surface of the quarter cell, which intersect at the inflection point, are respectively used as an x axis and a z axis, a straight line passing through the inflection point and perpendicular to the bottom surface is used as a y axis, a shielding electrode (71) extends from one end of a device to the other end along the x axis or the z axis, a gate electrode (81) extends from one end of the device to a shielding groove dielectric layer (72) on the side surface of the shielding electrode (71) along the z axis or the x axis, and the extending directions of the shielding electrode (71) and the gate electrode (81) are inconsistent.
5. the trench gate charge storage IGBT of claim 2, wherein: a second-conductivity-type semiconductor field resistance layer (12) is further arranged between the first-conductivity-type semiconductor collector region (13) and the second-conductivity-type semiconductor drift region (9).
6. a trench gate charge storage type IGBT according to any one of claims 2 to 5, characterized in that: the shielding trench structure also has a first conductivity type semiconductor layer (10) at the bottom.
7. The trench gate charge storage IGBT of claim 6, wherein: the first conductivity type semiconductor layer (10) extends laterally to two sides into a second conductivity type semiconductor drift region (9) below the second conductivity type semiconductor charge storage layer (6).
8. a manufacturing method of a trench gate charge storage type IGBT is characterized by comprising the following steps:
the method comprises the following steps: manufacturing a second conductive type semiconductor drift region (9);
step two: manufacturing a second conductive type semiconductor charge storage layer (6) and a first conductive type semiconductor base region (5) positioned on the top layer of the second conductive type semiconductor charge storage layer (6) on the front surface of the second conductive type semiconductor drift region (9) through pre-oxidation, photoetching, etching, ion implantation and high-temperature annealing processes;
Step three: etching on the second conductive type semiconductor charge storage layer (6) to form a first groove through photoetching, etching, thermal oxidation and deposition processes, wherein the depth of the first groove is greater than the junction depth of the second conductive type semiconductor charge storage layer (6) and extends along the transverse direction of the top layer of the device; forming a shielding electrode dielectric layer (72) on the inner wall of the first groove, then depositing a shielding electrode material in the groove to form a shielding electrode (71), wherein the shielding electrode (71) and the shielding electrode dielectric layer (72) on the peripheral side of the shielding electrode form a shielding groove structure;
Step four: etching and forming a second groove on the second conductive type semiconductor drift region (9) through photoetching, etching, thermal oxidation and deposition processes, wherein the depth of the second groove is less than the junction depth of the second conductive type semiconductor charge storage layer (6) and extends along the longitudinal direction of the top layer of the device, and the first groove is not communicated with the second groove; forming a gate dielectric layer (82) on the inner wall of the second groove, then depositing a gate electrode material in the second groove to form a gate electrode (71), wherein the gate electrode (71) and the gate dielectric layer (82) on the peripheral side of the gate electrode form a groove gate structure;
step five: manufacturing a first conductive type semiconductor emitter region (4) and a second conductive type semiconductor emitter region (3) which are mutually independent and arranged in parallel on the top layer of the first conductive type semiconductor base region (5) through photoetching, etching, ion implantation and high-temperature annealing processes; one side of the second conductive type semiconductor emitting region (3) is connected with a gate electrode (81) through a gate dielectric layer (82) along the longitudinal direction of the top layer of the device, the other side of the second conductive type semiconductor emitting region is connected with a shielding electrode (71) through a shielding groove dielectric layer (72) along the transverse direction of the top layer of the device, and one side of the first conductive type semiconductor emitting region (4) is connected with the shielding electrode (71) through the shielding groove dielectric layer (72) along the transverse direction of the top layer of the device;
Step six: forming a dielectric layer (2) on the upper surfaces of the gate electrode (81) and the gate dielectric layer (82) through photoetching, etching and deposition processes;
step seven: depositing metal on the surface, and forming emitter metal (1) on the dielectric layer (2), the second conductive type semiconductor emitting region (3), the first conductive type semiconductor emitting region (4), the shielding electrode (71) and the shielding groove dielectric layer (72) through photoetching and etching processes;
step eight: overturning the semiconductor device, reducing the thickness of the semiconductor, and injecting first conductive type impurities into the back surface of the second conductive type semiconductor drift region (9) through ion injection and high-temperature annealing process to form a first conductive type semiconductor collector region (13);
Step nine: back side deposition of metal, forming a collector metal (14) on the first conductivity type semiconductor collector region (13); thus, the trench gate charge storage type IGBT device is manufactured.
9. The method of claim 8, wherein the method comprises the following steps: the first conductive type semiconductor is a P-type semiconductor, and the second conductive type semiconductor is an N-type semiconductor; or the first conductive type semiconductor is an N-type semiconductor and the second conductive type semiconductor is a P-type semiconductor.
10. the method of claim 9, wherein the method comprises the following steps: by changing the trenching mode, the trench gate structure extends from one end of the device to the other end of the device along the top layer of the device and blocks the extension of the shielding trench structure along the top layer of the device or the shielding trench structure extends from one end of the device to the other end of the device along the top layer of the device and blocks the extension of the trench gate structure along the top layer of the device.
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| CN110444471A (en) * | 2019-08-22 | 2019-11-12 | 电子科技大学 | A kind of preparation method of 3 dimension separation gate groove charge storage type IGBT |
| CN110459606B (en) * | 2019-08-29 | 2023-03-24 | 电子科技大学 | Transverse groove type IGBT with self-bias PMOS and preparation method thereof |
| CN110504260B (en) * | 2019-08-29 | 2022-11-04 | 电子科技大学 | Transverse groove type IGBT with self-bias PMOS and preparation method thereof |
| CN111211169A (en) * | 2020-02-26 | 2020-05-29 | 无锡新洁能股份有限公司 | Shielded IGBT structure and manufacturing method thereof |
| CN111261711A (en) * | 2020-03-10 | 2020-06-09 | 瑞能半导体科技股份有限公司 | Power device and forming method thereof |
| JP7297709B2 (en) * | 2020-03-19 | 2023-06-26 | 株式会社東芝 | Semiconductor devices and semiconductor circuits |
| CN115483284A (en) * | 2022-07-20 | 2022-12-16 | 上海林众电子科技有限公司 | Preparation method and application of improved SG IGBT |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101980356A (en) * | 2002-03-22 | 2011-02-23 | 西利康尼克斯股份有限公司 | Structures of and methods of fabricating trench-gated mis devices |
| US8178922B2 (en) * | 2010-01-14 | 2012-05-15 | Force Mos Technology Co., Ltd. | Trench MOSFET with ultra high cell density and manufacture thereof |
| CN103094321A (en) * | 2011-11-01 | 2013-05-08 | 万国半导体股份有限公司 | Two-dimensional Shielded Gate Transistor Device And Method Of Manufacture |
| CN105932055A (en) * | 2016-06-13 | 2016-09-07 | 电子科技大学 | Plane gate IGBT and manufacturing method therefor |
| CN107452789A (en) * | 2016-05-09 | 2017-12-08 | 安世有限公司 | Improvement layout for device manufacture |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7768064B2 (en) * | 2006-01-05 | 2010-08-03 | Fairchild Semiconductor Corporation | Structure and method for improving shielded gate field effect transistors |
| CN102263133B (en) * | 2011-08-22 | 2012-11-07 | 无锡新洁能功率半导体有限公司 | Low-gate charge low-on resistance deep trench power metal oxide semiconductor field effect transistor (MOSFET) device and manufacturing method |
-
2018
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101980356A (en) * | 2002-03-22 | 2011-02-23 | 西利康尼克斯股份有限公司 | Structures of and methods of fabricating trench-gated mis devices |
| US8178922B2 (en) * | 2010-01-14 | 2012-05-15 | Force Mos Technology Co., Ltd. | Trench MOSFET with ultra high cell density and manufacture thereof |
| CN103094321A (en) * | 2011-11-01 | 2013-05-08 | 万国半导体股份有限公司 | Two-dimensional Shielded Gate Transistor Device And Method Of Manufacture |
| CN107452789A (en) * | 2016-05-09 | 2017-12-08 | 安世有限公司 | Improvement layout for device manufacture |
| CN105932055A (en) * | 2016-06-13 | 2016-09-07 | 电子科技大学 | Plane gate IGBT and manufacturing method therefor |
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