CN108320690B - Display panel, detection method thereof and display device - Google Patents
Display panel, detection method thereof and display device Download PDFInfo
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- CN108320690B CN108320690B CN201810102273.5A CN201810102273A CN108320690B CN 108320690 B CN108320690 B CN 108320690B CN 201810102273 A CN201810102273 A CN 201810102273A CN 108320690 B CN108320690 B CN 108320690B
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Abstract
The invention provides a display panel, a detection method thereof and a display device, and belongs to the technical field of display. The display panel of the present invention includes: the pixel detection circuit comprises M pixel detection circuit groups, a control unit and N time sequence units; m is more than or equal to 2, and N is more than or equal to 2; the N time sequence units are connected with the control unit and work one by one under the control of the control unit; the scanning lines connected with the ith row of pixel detection circuits in each pixel detection circuit group are all connected with the ith time sequence unit, wherein i is more than or equal to 1 and less than or equal to N; each time sequence unit is used for inputting working level signals to the scanning lines connected with the time sequence unit line by line in a resetting stage so as to open the corresponding first switch unit and reset the corresponding photosensitive units through the reset signals input on the reading lines; and the scanning line is used for inputting working level signals to the scanning lines connected with the scanning line by line in a sampling stage so as to open the corresponding first switch unit and read the electric signals generated by the photosensitive units through the reading lines.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to a display panel, a detection method thereof and a display device.
Background
As shown in fig. 1, a display panel having a plurality of passive pixel detection circuits arranged in an array is provided in the prior art. The pixel detection circuits in the same row are connected to a same gate line, and the pixel detection circuits in the same column are connected to a same readout line. Which includes one photodiode PD and one switching transistor T for each pixel detection circuit; when the photodiode is illuminated by the PD, a photocurrent is generated, the switching transistor T is controlled to be turned on by the scan line gate line in the sampling stage, and the photocurrent generated by the photodiode PD is read by the read line, so that the control unit can analyze the information detected by the pixel detection circuit.
In order to provide a detection speed of each pixel detection circuit on the display panel, the timing is controlled by a rolling method. Specifically, as shown in FIGS. 2 and 3, time t1To turn on the first switching transistor T1For the first photodiode PD1Reset (reset to a reset voltage on the read line), the first switching transistor T1After being turned off, the first photodiode PD1Light accumulation starts and continues for Tint, then t2The next row of pixel detection circuits immediately adjacent is reset and light is accumulated again, t3It is again for the first switching transistor T1Turn on to read value, t4Then to the second switching transistor T2And starting to read the value. However, due to the wiring, the scan line and the readout line are overlapped, and the turn-on voltage applied to the scan line is often very large, so that when the pixel detection circuit in the second row is in the reset stage, i.e. t2At the moment, after the start voltage is applied to the second row scanning line, the capacitance C between the second row scanning line and the reading lineGR2Coupled to a read line, followed by t3At the moment, i.e. the first switching transistor T1Turn on to read value due to t2Time t and3the time interval between moments, at which the capacitance C is very shortGR2
Will pass through the first switching transistor T after being coupled to the read line1Affecting the first photodiode PD1。
Disclosure of Invention
The present invention is directed to at least one of the technical problems in the prior art, and provides a display panel, a detection method thereof, and a display device, which are used to prevent the influence on the photosensitive cells in the upper row of pixel detection circuits when the pixel detection circuits are reset.
The technical scheme adopted for solving the technical problem of the invention is a display panel, which comprises a plurality of scanning lines and a plurality of reading lines which are arranged in a crossed manner; a pixel detection circuit is arranged at the intersection position of the scanning line and the reading line; the pixel detection circuit comprises a first switch unit and a photosensitive unit connected with the first switch unit; the first switch units in the pixel detection circuits in the same row are connected with the same scanning line; the first switch units in the pixel detection circuits in the same column are connected with the same reading line; the display panel is divided into M pixel detection circuit groups; each pixel detection circuit group comprises N rows of pixel detection circuits; the display panel further includes: the device comprises a control unit and N time sequence units; m is more than or equal to 2, and N is more than or equal to 2; wherein the content of the first and second substances,
the N time sequence units are connected with the control unit and work one by one under the control of the control unit;
the scanning lines connected with the pixel detection circuits in the ith row in each pixel detection circuit group are connected with the ith time sequence unit, wherein i is more than or equal to 1 and less than or equal to N;
each time sequence unit is used for inputting working level signals to the scanning lines connected with the time sequence unit line by line in a resetting stage so as to open the corresponding first switch unit and reset the corresponding photosensitive units through the reset signals input on the reading lines; and the scanning line circuit is used for inputting working level signals to the scanning lines connected with the scanning line circuit by line in a sampling stage so as to open the corresponding first switch units and read the electric signals generated by the photosensitive units through the reading lines.
Preferably, a second switch unit is arranged on each reading line and at a position corresponding to a position between any two adjacent pixel detection circuit groups; wherein the content of the first and second substances,
when the pixel detection circuit of the ith row in the kth pixel detection circuit group is reset, controlling each second switch unit between the kth-1 and the kth pixel detection circuit groups to be switched off; wherein k is more than or equal to 2 and less than or equal to M.
It is further preferable that each of the second switch units located between two adjacent pixel detection circuit groups is connected to the same switch control line.
It is further preferable that the second switching unit includes a second transistor; wherein the content of the first and second substances,
and the first pole and the second pole of the second transistor are connected to the reading line, and the control pole of the second transistor is connected to the switch control line.
Preferably, N of the timing units are integrated in the same timing control chip.
Preferably, the display panel further includes: a plurality of operational amplifiers; wherein the content of the first and second substances,
the positive input end of each operational amplifier is connected with a reset voltage end; the reading line is connected with a first end of the capacitor, and an output end of the reading line is connected with a control unit and a second end of the capacitor; the operational amplifier is used for amplifying the signal output by the reading line so that the control unit identifies the information detected by the pixel detection circuit.
Preferably, the first switching unit includes a first transistor; wherein the content of the first and second substances,
the first electrode of the first transistor is connected with the photosensitive unit, the second electrode of the first transistor is connected with the reading line, and the control electrode of the first transistor is connected with the scanning line.
Preferably, the photosensitive unit includes: a photodiode; wherein the content of the first and second substances,
the first pole of the photodiode is connected with the first switch unit, and the second pole of the photodiode is connected with a reverse bias voltage end.
The technical scheme adopted for solving the technical problem of the invention is a detection method of the display panel, which comprises the following steps:
controlling N sequential units by a control unit; and controlling the pixel detection circuit connected with the timing unit to work through the timing unit;
the step of controlling the pixel detection circuit connected with the timing unit to work through the timing unit comprises the following steps:
in the resetting stage, working level signals are input to the scanning lines connected with the timing sequence unit line by line to enable the corresponding first switch units to be opened, and the corresponding photosensitive units are reset through the reset signals input on the reading lines;
and in the sampling stage, working level signals are input to the scanning lines connected with the timing sequence unit line by line so as to open the corresponding first switch unit, and the electric signals generated by the photosensitive units are read through the reading lines.
The technical scheme adopted for solving the technical problem of the invention is a display device which comprises the display panel.
The invention has the following beneficial effects:
since the display panel of this embodiment includes a plurality of timing units and the control unit controls the timing units to operate one by one, compared with the prior art, the scanning time interval of two adjacent scanning lines is prolonged, thereby effectively avoiding the parasitic capacitance generated by overlapping of the scanning lines and the readout lines.
Drawings
FIG. 1 is a schematic diagram of a conventional display panel with a pixel detection circuit;
FIG. 2 is a schematic diagram of two pixel detection circuits in two adjacent rows;
FIG. 3 is a timing diagram illustrating operation of the two pixel detection circuits of FIG. 2;
fig. 4 is a schematic structural diagram of a display panel with a pixel detection circuit according to embodiment 1 of the present invention;
FIG. 5 is a simplified diagram of the display panel of FIG. 4;
FIG. 6 is a timing diagram illustrating the operation of the pixel detection circuit in the display panel of FIG. 5;
fig. 7 is a schematic structural diagram of a preferred display panel according to embodiment 1 of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Example 1:
as shown in fig. 4, the present embodiment provides a display panel, which includes a plurality of scan lines gate line and a plurality of read lines read line arranged in a crossing manner; a pixel detection circuit is arranged at the crossing position of the scanning line gate line and the reading line read line; the pixel detection circuit comprises a first switch unit and a photosensitive unit connected with the first switch unit; the first switch units in the pixel detection circuits in the same row are connected with the same scanning line gate line; the first switch units in the pixel detection circuits in the same column are connected to the same read line.
Dividing the display panel in the embodiment into M pixel detection circuit groups Zone; each pixel detection circuit group Zone comprises N rows of pixel detection circuits; the display panel particularly comprises: the device comprises a control unit and N time sequence units; m is more than or equal to 2, and N is more than or equal to 2.
The N time sequence units are connected with the control unit and work one by one under the control of the control unit.
And the scanning line gate line connected with the ith row of pixel detection circuits in each pixel detection circuit group Zone is connected with the ith time sequence unit, wherein i is more than or equal to 1 and less than or equal to N.
Each time sequence unit is used for inputting working level signals to a scanning line gate line connected with the time sequence unit line by line in a reset stage so as to open a corresponding first switch unit and reset a corresponding photosensitive unit by reading reset signals input on a line read line; and the scanning circuit is used for inputting working level signals to the scanning line gate line connected with the scanning circuit row by row in a sampling stage so as to open the corresponding first switch unit and read the electric signals generated by the photosensitive unit through the reading line read line.
In order to make the display panel structure more clear in the present embodiment, M is 5, N is 2; the display panel described above will be specifically described.
As shown in fig. 5 and 6, the display panel includes a control unit, 2 timing units, which are a first timing unit and a second timing unit respectively; 5 pixel detection circuit groups Zone, each pixel detection circuit group Zone comprises 2 rows of pixel detection circuits; the scanning line gate line connected with the first row of pixel detection circuits in each pixel detection circuit group Zone is connected with a first timing unit; the scanning line gate line connected with the second row of pixel detection circuits in each pixel detection circuit group Zone is connected with a second time sequence unit; that is, gate line1-1, gate line2-1, gate line3-1, gate line4-1, gate line5-1 are linked to the first timing unit; the gate line1-2, gate line2-2, gate line3-2, gate line4-2 and gate line5-2 are connected with the second timing unit. The control unit is used for controlling the first timing unit and the second timing unit to work one by one, namely, after one of the first timing unit and the second timing unit finishes working, the other one does work. The first timing unit is first operated as an example for explanation.
When the pixel detection circuit connected with the gate line1-1, gate line2-1, gate line3-1, gate line4-1 and gate line5-1 is operated, the first phase is a reset phase, the first timing unit scans the gate line1-1, gate line2-1, gate line3-1, gate line4-1 and gate line5-1 line by line, specifically, when the first line scan line gate line, namely, gate line1-1 is scanned, an operating level signal is input for the gate line1-1, a switch unit in the pixel detection circuit connected with the gate line1-1 is opened, and at this time, a reset signal can be input through a read line, and a photosensitive unit in the pixel detection circuit connected with the gate line1-1 is reset; in the same manner, the reset of the pixel detection circuits connected to the gate line2-1, gate line3-1, gate line4-1, and gate line5-1 is completed in sequence. Then, a second phase, i.e. a sampling phase, is entered, and it should be noted that the light sensing units in the row of pixel detection circuits accumulate light between each row of pixel detection circuits and the sampling phase, so that the photocurrent generated by the light sensing units can be read in the sampling phase.
Next, the sampling phase of the pixel detection circuit to which the gate line1-1, gate line2-1, gate line3-1, gate line4-1 and gate line5-1 are connected will be explained. The first timing unit scans the gate line1-1, gate line2-1, gate line3-1, gate line4-1 and gate line5-1 line by line, and specifically, when scanning the first row of scan lines, namely gate line1-1, an operating level signal is input to the gate line1-1, and a switch unit in a pixel detection circuit connected with the gate line1-1 is turned on, at this time, a photocurrent generated by a photosensitive unit in the pixel detection circuit connected with the gate line1-1 can be read by reading a line read; in the same manner, sampling of the pixel detection circuits connected to the gate line2-1, gate line3-1, gate line4-1, and gate line5-1 is sequentially completed.
In summary, the first timing unit completes the scanning of the gate line1-1, gate line2-1, gate line3-1, gate line4-1 and gate line5-1 to end the resetting and sampling of the pixel detection circuits connected to the gate line1-1, gate line2-1, gate line3-1, gate line4-1 and gate line 5-1; then, according to the same method as described above, the gate line1-2, gate line2-2, gate line3-2, gate line4-2 and gate line5-2 are scanned by the second timing unit, so as to reset the pixel detection circuits connected with the gate line1-2, gate line2-2, gate line3-2, gate line4-2 and gate line5-2 line by line; after reset, gate line1-2, gate line2-2, gate line3-2, gate line4-2, and gate line5-2 are scanned again to sample the pixel detection circuits connected to gate line1-2, gate line2-2, gate line3-2, gate line4-2, and gate line5-2 line by line.
It can be seen that when an operating level signal is input to gate line2-1 to reset the pixel detection circuit connected to the row of scan lines gate line, the time interval between the time when gate line1-1 is scanned and the time when gate line2-1 is scanned is much longer than the time interval between the time when gate line1-1 is scanned and the time when gate line2-1 is scanned immediately after the sampling phase of the pixel detection circuit connected to gate line1-1, gate line2-1, gate line3-1, gate line4-1, gate line5-1 is completed, and therefore the high level input when gate line2-1 is scanned does not affect the sensing of the pixel detection circuit connected to gate line1 even though the pixel detection circuit connected to gate line1 is only read by the parasitic capacitance coupling formed by gate line2-1 and the line read line arranged across it And (5) Yuan.
The N timing units in the display panel of the embodiment are integrated in the same timing control chip, so that the display panel has a simple structure.
Wherein, the display panel of this embodiment still includes: a plurality of operational amplifiers OP. Specifically, the positive input end of each operational amplifier OP is connected to the reset voltage end VCM; the read line is connected with a first end of a capacitor C, and an output end of the read line is connected with a second end of the capacitor C; the operational amplifier OP is configured to amplify a signal output by the read line so that the control unit identifies information detected by the pixel detection circuit.
The first switch unit in the display panel of the present embodiment includes a first transistor T. Specifically, a first pole of the first transistor T is connected to the light sensing unit, a second pole of the first transistor T is connected to the read line, and a control pole of the first transistor T is connected to the scan line gate line.
The first transistor T may be a P-type transistor or an N-type transistor; when the first transistor T is a P-type transistor and the working level input on the scanning line gate line is low level, the first transistor T is conducted; when the first transistor T is an N-type transistor, and the working level input on the scan line gate line is a high level, the first transistor T is turned on.
The photosensitive unit in the display panel of the embodiment includes: a photodiode PD; specifically, the first pole of the photodiode PD is connected to the switching unit, and the second pole is connected to the reverse bias voltage terminal.
Since the display panel of this embodiment includes a plurality of timing units and the control unit controls the timing units to operate one by one, compared with the prior art, the scanning time interval of two adjacent scanning lines gate line is prolonged, so as to effectively avoid the parasitic capacitance generated by overlapping of the scanning lines gate line and the readout line.
Further, on the basis of the display panel, the present embodiment further provides a preferred implementation manner, as shown in fig. 7, the display panel may include not only the structures of the display panel, but also, in particular, second switch units are disposed on each read line and at positions corresponding to any two adjacent pixel detection circuit groups Zone; when the ith row of pixel detection circuits in the kth pixel detection circuit group Zone are reset, controlling the second switch units between the kth-1 and the kth pixel detection circuit group Zone to be switched off; wherein k is more than or equal to 2 and less than or equal to M.
And each second switch unit positioned between two adjacent pixel detection circuit Zone groups is connected with the same switch control line. This facilitates control of the second switching unit and facilitates wiring.
Wherein the second switching unit includes a second transistor M; a first pole and a second pole of the second transistor M are connected to the read line, and a control pole is connected to the switch control line ctrl.
The second transistor M may be a P-type transistor or an N-type transistor; when the second transistor M is a P-type transistor and the working level input on the switch control line ctrl is a low level, the second transistor M is turned on; when the second transistor M is an N-type transistor, and the operating level input to the switch control line ctrl is a high level, the second transistor M is turned on.
The display panel also comprises a control unit and 2 time sequence units which are respectively a first time sequence unit and a second time sequence unit; each of the 5 pixel detection circuit groups Zone includes 2 rows of pixel detection circuits as an example.
Specifically, when the second timing unit inputs the operating level signal to the scan line gate line connected to the 2 nd row of pixel detection circuits in the 2 nd pixel detection circuit group Zone, so that the row of pixel detection circuits is reset, the switch unit on the read line between the 1 st pixel detection circuit group Zone and the 2 nd pixel detection circuit group Zone is controlled to be turned off, so as to prevent the high level signal on the scan line gate line connected to the 2 nd row of pixel detection circuits from being coupled to the read line through the parasitic capacitor formed by the scan line gate line and the read line, so as to affect the light sensing unit in the 1 st pixel detection circuit group Zone.
Correspondingly, the present embodiment provides a method for detecting the display panel, where the method includes:
controlling N sequential units by a control unit; and controlling the pixel detection circuit connected with the timing unit to work through the timing unit;
the step of controlling the pixel detection circuit connected with the timing unit to work through the timing unit comprises the following steps:
in the reset stage, working level signals are input to the scan line gate line connected with the timing sequence unit line by line so as to open the corresponding first switch unit, and the corresponding photosensitive unit is reset by reading reset signals input on the line read line.
In the sampling stage, working level signals are input to a scanning line gate line connected with the timing unit line by line through the timing unit, so that the corresponding first switch unit is switched on, and the electric signals generated by the photosensitive unit are read through a reading line read line.
The display panel comprises a control unit and 2 time sequence units, namely a first time sequence unit and a second time sequence unit; the detection method in this embodiment will be described with an example of 5 pixel detection circuit groups Zone, each of which includes 2 rows of pixel detection circuits. The scanning line gate line connected with the first row of pixel detection circuits in each pixel detection circuit group Zone is connected with a first timing unit; the scanning line gate line connected with the second row of pixel detection circuits in each pixel detection circuit group Zone is connected with a second time sequence unit; that is, gate line1-1, gate line2-1, gate line3-1, gate line4-1, gate line5-1 are linked to the first timing unit; the gate line1-2, gate line2-2, gate line3-2, gate line4-2 and gate line5-2 are connected with the second timing unit. The control unit is used for controlling the first timing unit and the second timing unit to work one by one, namely, after one of the first timing unit and the second timing unit finishes working, the other one does work. The first timing unit is first operated as an example for explanation.
When the pixel detection circuit connected with the gate line1-1, gate line2-1, gate line3-1, gate line4-1 and gate line5-1 is operated, the first phase is a reset phase, the first timing unit scans the gate line1-1, gate line2-1, gate line3-1, gate line4-1 and gate line5-1 line by line, specifically, when the first line scan line gate line, namely, gate line1-1 is scanned, an operating level signal is input for the gate line1-1, a switch unit in the pixel detection circuit connected with the gate line1-1 is opened, and at this time, a reset signal can be input through a read line, and a photosensitive unit in the pixel detection circuit connected with the gate line1-1 is reset; in the same manner, the reset of the pixel detection circuits connected to the gate line2-1, gate line3-1, gate line4-1, and gate line5-1 is completed in sequence. Then, a second phase, i.e. a sampling phase, is entered, and it should be noted that the light sensing units in the row of pixel detection circuits accumulate light between each row of pixel detection circuits and the sampling phase, so that the photocurrent generated by the light sensing units can be read in the sampling phase.
Next, the sampling phase of the pixel detection circuit to which the gate line1-1, gate line2-1, gate line3-1, gate line4-1 and gate line5-1 are connected will be explained. The first timing unit scans the gate line1-1, gate line2-1, gate line3-1, gate line4-1 and gate line5-1 line by line, and specifically, when scanning the first row of scan lines, namely gate line1-1, an operating level signal is input to the gate line1-1, and a switch unit in a pixel detection circuit connected with the gate line1-1 is turned on, at this time, a photocurrent generated by a photosensitive unit in the pixel detection circuit connected with the gate line1-1 can be read by reading a line read; in the same manner, sampling of the pixel detection circuits connected to the gate line2-1, gate line3-1, gate line4-1, and gate line5-1 is sequentially completed.
In summary, the first timing unit completes the scanning of the gate line1-1, gate line2-1, gate line3-1, gate line4-1 and gate line5-1 to end the resetting and sampling of the pixel detection circuits connected to the gate line1-1, gate line2-1, gate line3-1, gate line4-1 and gate line 5-1; then, according to the same method as described above, the gate line1-2, gate line2-2, gate line3-2, gate line4-2 and gate line5-2 are scanned by the second timing unit, so as to reset the pixel detection circuits connected with the gate line1-2, gate line2-2, gate line3-2, gate line4-2 and gate line5-2 line by line; after reset, gate line1-2, gate line2-2, gate line3-2, gate line4-2, and gate line5-2 are scanned again to sample the pixel detection circuits connected to gate line1-2, gate line2-2, gate line3-2, gate line4-2, and gate line5-2 line by line.
It can be seen that, when an operation level signal is inputted to gate line2-1 to reset the pixel detection circuit connected to the row of scanning lines gate line, the time interval between the time when the pixel detection circuit connected to gate line1-1, gate line2-1, gate line3-1, gate line4-1 and gate line5-1 is scanned is much longer than the time interval between the time when the gate line1-1 is scanned and the time when the gate line2-1 is scanned immediately after the gate line1-1 is scanned in the prior art, so that the high level inputted when the gate line2-1 is scanned does not affect the pixel detection circuit connected to gate line1 even if the pixel detection circuit connected to gate line1 is read by the parasitic capacitance coupling formed by the gate line2-1 and the line read line arranged across the gate line2-1 .
Preferably, when the display panel in this embodiment may include not only the structures of the display panel described above, but also the second switch unit disposed on each readout line and at the position corresponding to any two adjacent pixel detection circuit groups Zone, the method for detecting a display panel in this embodiment further includes: when the ith row of pixel detection circuits in the kth pixel detection circuit group Zone are reset, controlling the second switch units between the kth-1 and the kth pixel detection circuit group Zone to be switched off; wherein k is more than or equal to 2 and less than or equal to M.
The display panel also comprises a control unit and 2 time sequence units which are respectively a first time sequence unit and a second time sequence unit; each of the 5 pixel detection circuit groups Zone includes 2 rows of pixel detection circuits as an example.
Specifically, when the second timing unit inputs the operating level signal to the scan line gate line connected to the 2 nd row of pixel detection circuits in the 2 nd pixel detection circuit group Zone, so that the row of pixel detection circuits is reset, the switch unit on the read line between the 1 st pixel detection circuit group Zone and the 2 nd pixel detection circuit group Zone is controlled to be turned off, so as to prevent the high level signal on the scan line gate line connected to the 2 nd row of pixel detection circuits from being coupled to the read line through the parasitic capacitor formed by the read line and the scan line gate line, so as to affect the light sensing unit in the 1 st pixel detection circuit group Zone.
Example 3:
the present embodiment provides a display device including the display panel in embodiment 1. Therefore, the display device of the embodiment has better display effect.
The display device may be a liquid crystal display device or an electroluminescent display device, such as any product or component with a display function, such as a liquid crystal panel, electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (10)
1. A display panel comprises a plurality of scanning lines and a plurality of reading lines which are arranged in a crossed manner; a pixel detection circuit is arranged at the intersection position of the scanning line and the reading line; the pixel detection circuit comprises a first switch unit and a photosensitive unit connected with the first switch unit; the first switch units in the pixel detection circuits in the same row are connected with the same scanning line; the first switch units in the pixel detection circuits in the same column are connected with the same reading line; the display panel is divided into M pixel detection circuit groups; each pixel detection circuit group comprises N rows of pixel detection circuits; the display panel further includes: the device comprises a control unit and N time sequence units; m is more than or equal to 2, and N is more than or equal to 2; wherein the content of the first and second substances,
the N time sequence units are connected with the control unit and work one by one under the control of the control unit;
the scanning lines connected with the pixel detection circuits in the ith row in each pixel detection circuit group are connected with the ith time sequence unit, wherein i is more than or equal to 1 and less than or equal to N;
each time sequence unit is used for inputting working level signals to the scanning lines connected with the time sequence unit line by line in a resetting stage so as to open the corresponding first switch unit and reset the corresponding photosensitive units through the reset signals input on the reading lines; and the scanning line circuit is used for inputting working level signals to the scanning lines connected with the scanning line circuit by line in a sampling stage so as to open the corresponding first switch units and read the electric signals generated by the photosensitive units through the reading lines.
2. The display panel according to claim 1, wherein a second switch unit is provided at a position on each of the read lines corresponding to a position between any two adjacent pixel detection circuit groups; wherein the content of the first and second substances,
when the pixel detection circuit of the ith row in the kth pixel detection circuit group is reset, controlling each second switch unit between the kth-1 and the kth pixel detection circuit groups to be switched off; wherein k is more than or equal to 2 and less than or equal to M.
3. The display panel according to claim 2, wherein each of the second switch units between two adjacent pixel detection circuit groups is connected to the same switch control line.
4. The display panel according to claim 3, wherein the second switch unit includes a second transistor; wherein the content of the first and second substances,
and the first pole and the second pole of the second transistor are connected to the reading line, and the control pole of the second transistor is connected to the switch control line.
5. The display panel according to claim 1, wherein the N timing units are integrated in the same timing control chip.
6. The display panel according to claim 1, further comprising: a plurality of operational amplifiers; wherein the content of the first and second substances,
the positive input end of each operational amplifier is connected with a reset voltage end, the negative input end of each operational amplifier is connected with one reading line and the first end of the capacitor, and the output end of each operational amplifier is connected with the control unit and the second end of the capacitor; the operational amplifier is used for amplifying the signal output by the reading line so that the control unit identifies the information detected by the pixel detection circuit.
7. The display panel according to claim 1, wherein the first switching unit comprises a first transistor; wherein the content of the first and second substances,
the first electrode of the first transistor is connected with the photosensitive unit, the second electrode of the first transistor is connected with the reading line, and the control electrode of the first transistor is connected with the scanning line.
8. The display panel according to claim 1, wherein the light sensing unit comprises: a photodiode; wherein the content of the first and second substances,
the first pole of the photodiode is connected with the first switch unit, and the second pole of the photodiode is connected with a reverse bias voltage end.
9. A method of inspecting the display panel of any one of claims 1-8, comprising:
controlling N sequential units by a control unit; and controlling the pixel detection circuit connected with the timing unit to work through the timing unit;
the step of controlling the pixel detection circuit connected with the timing unit to work through the timing unit comprises the following steps:
in the resetting stage, working level signals are input to the scanning lines connected with the timing sequence unit line by line to enable the corresponding first switch units to be opened, and the corresponding photosensitive units are reset through the reset signals input on the reading lines;
and in the sampling stage, working level signals are input to the scanning lines connected with the timing sequence unit line by line so as to open the corresponding first switch unit, and the electric signals generated by the photosensitive units are read through the reading lines.
10. A display device characterized by comprising the display panel according to any one of claims 1 to 8.
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| CN109547713B (en) | 2018-11-23 | 2022-01-28 | 京东方科技集团股份有限公司 | Flat panel detector and pixel driving circuit thereof |
| CN109872689A (en) * | 2019-03-21 | 2019-06-11 | 京东方科技集团股份有限公司 | Pixel circuit, touch-control display panel and display device |
| CN109860271B (en) * | 2019-04-16 | 2021-03-02 | 京东方科技集团股份有限公司 | Display panel, reading circuit thereof and display terminal |
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| KR100701086B1 (en) * | 2004-02-04 | 2007-03-29 | 비오이 하이디스 테크놀로지 주식회사 | Driving circuit of LCD |
| TWI469028B (en) * | 2009-02-24 | 2015-01-11 | Au Optronics Corp | Display apparatus and touch detection method |
| RU2011139956A (en) * | 2009-03-02 | 2013-04-10 | Шарп Кабусики Кайся | DISPLAY DEVICE |
| KR101257607B1 (en) * | 2009-03-30 | 2013-04-29 | 샤프 가부시키가이샤 | Display device and method of operation thereof |
| US20130032696A1 (en) * | 2010-04-30 | 2013-02-07 | Konica Minolta Medical & Graphic, Inc. | Radiation image capturing apparatus |
| CN105187741A (en) * | 2015-08-27 | 2015-12-23 | 友达光电股份有限公司 | Optical sensor read-out circuit capable of reducing noise |
| CN107609518B (en) * | 2017-09-14 | 2020-06-02 | 京东方科技集团股份有限公司 | Driving method and driving device of pixel detection circuit |
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