CN108319465B - Circuit and method for upgrading FPGA configuration data - Google Patents
Circuit and method for upgrading FPGA configuration data Download PDFInfo
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Abstract
The present disclosure provides a circuit for upgrading FPGA configuration data, comprising: the package body internally comprises at least one memory unit and a controller unit, wherein the controller unit is connected to the memory unit and comprises JTAG processing circuits, memory control circuits, configuration control circuits, memory control switching circuits, version switching control circuits and a re-injection data receiving and transmitting circuit. Because the control unit structure in the circuit is improved, the matching code re-injection and the matching code version switching of the FPGA can be completed only by matching the FPGA with the circuit chip, no additional components are needed, and the hardware cost of the system is reduced.
Description
Technical Field
The present disclosure relates to the field of FPGAs (Field Programmable Gate Array, field programmable gate arrays), and more particularly to a circuit and method for upgrading FPGA configuration data.
Background
Because of the excellent flexibility and versatility of FPGAs, FPGAs are increasingly being used in the field of aerospace equipment, satellites, and the like. Among them, the most widely used is an SRAM (Static Random Access Memory ) FPGA, that is, an SRAM array is used inside an FPGA chip to store configuration code stream (bit stream, configuration bitstream, abbreviated as code allocation) information of the FPGA, where the configuration information defines the chip function of the FPGA.
Since SRAM is a volatile memory, SRAM FPGAs lose all their configuration information after they are powered down, in practical FPGA application systems, the FPGA configuration code is typically stored in another EEPROM, PROM or other nonvolatile memory, which is collectively referred to as configuration memory (Configuration Memory, configuration PROM). After each time the system is powered on, the Configuration data stored in the Configuration memory is read into the FPGA, and this process of reading the Configuration code is called loading or Configuration (Configuration) of the FPGA. After the configuration is completed, the FPGA starts to execute the functions defined by the user.
In a typical FPGA application system, a special PROM memory chip is generally used to load and configure the FPGA, and the PROM chip itself has a JTAG interface, and can perform operations such as reading, writing, and erasing on the PROM from an upper computer through a JTAG download line, which is called In-system programming (ISP, in-System Programming). After finishing updating the data in the PROM through an ISP link from the upper computer, powering down the system and powering up again, automatically reading the data in the PROM by the FPGA after powering up, finishing self initialization, and finishing the powering up configuration loading of the FPGA by the cooperation of the PROM and the FPGA. During the development and debugging of the system, a user can very conveniently modify the data in the PROM, update the configuration code of the FPGA and further update the functions of the FPGA. However, for aerospace and satellite applications, this application also has significant drawbacks:
1. after the satellite is assembled and the satellite is integrated, the data in the PROM becomes very difficult or even impossible to modify; if the data in the PROM must be modified and updated after integrating the cover for the task, JTAG connecting lines and corresponding interfaces often need to be reserved, which makes system development more complicated;
2. after satellite emission goes empty, the data in the PROM can not be updated any more, which means that the FPGA can only fixedly load the matched codes which are already solidified in the PROM, and the functions of the FPGA can not be updated.
To overcome the above-mentioned drawbacks, engineering technicians in this field have performed a great deal of related work; around the subject of the code matching and upgrading of the FPGA, researchers update the FPGA configuration file stored in the Flash memory by adopting a baseboard management controller as a controller unit so as to perform FPGA configuration, but the scheme needs to use more circuit units, which increases the weight of a circuit system and the complexity of the system; in addition, the method cannot support multiple versions of configuration codes at the same time, and the FPGA can only obtain one new configuration code after updating the data in the Flash memory once; the technical staff adopts the FPGA and 2 configuration units, the FPGA chip controls the state retainer and the electronic switch of the configuration units, receives configuration data from the upper computer or the remote equipment and writes the configuration data into the memory, but the scheme needs 2 configuration units, has high circuit complexity, occupies more circuit board area and has larger system weight; and 2 configuration units can only store 2 versions of design configuration codes and do not support more versions of configuration codes.
Disclosure of Invention
First, the technical problem to be solved
The present disclosure provides a circuit and method for upgrading FPGA configuration data to at least partially solve the technical problems set forth above.
(II) technical scheme
According to one aspect of the present disclosure, there is provided a circuit for upgrading FPGA configuration data, comprising: a package having at least one memory unit contained therein, and a controller unit, wherein the controller unit is coupled to the memory unit, comprising: JTAG processing circuitry, memory control circuitry, configuration control circuitry, memory control switching circuitry, versioning control circuitry, and re-injection data receiving and transmitting circuitry.
In some embodiments of the present disclosure, the JTAG processing circuit includes a JTAG interface circuit and a first operation data processing circuit, and is connected to the upper computer through the JTAG interface circuit; the JTAG interface circuit comprises a JTAG clock interface, a JTAG mode interface and a plurality of interface circuits of a JTAG data input/output interface; the first operation data processing circuit comprises an operation instruction detection extraction and output sub-circuit, an operation target address detection extraction and output sub-circuit, an operation response handshake signal output sub-circuit and a first data input and output sub-circuit.
In some embodiments of the present disclosure, the memory control circuit is connected to the JTAG processing circuit, including a second operational data processing circuit, a first memory operational circuit, a first read data circuit, and a first toggle selection circuit; the second operation data processing circuit is connected to the first operation data processing circuit and comprises an operation instruction receiving sub-circuit, an operation target address receiving sub-circuit, an operation response handshake signal receiving sub-circuit and a second data input and output sub-circuit; the first memory operation circuit comprises a memory chip selection output sub-circuit, a memory working clock output sub-circuit and a memory read-write data sub-circuit; the first read data circuit comprises a read data output sub-circuit and a read data request receiving sub-circuit; the first version switching selection circuit comprises a switching version target address receiving sub-circuit and a switching version request receiving sub-circuit.
In some embodiments of the present disclosure, the configuration control circuit is connected to a memory control circuit, including a second read data circuit and an FPGA configuration circuit, wherein the second read data circuit is connected to a first read data circuit, including a read data receiving sub-circuit and a read data enabling sub-circuit; the FPGA configuration circuit is connected to the FPGA configuration interface.
In some embodiments of the present disclosure, the version switch control circuit is connected to the memory control circuit and includes a second version switch selection circuit and a first version switch configuration circuit, where the second version switch selection circuit is connected to the first version switch selection circuit and includes a switch version target address transmitting sub-circuit and a switch version enabling sub-circuit; the version switching configuration circuit is connected to the communication interface and comprises a version switching chip selection sub-circuit, a version switching clock sub-circuit and a version switching read-write data sub-circuit.
In some embodiments of the present disclosure, the refill data receiving and transmitting circuit is connected to the memory selection circuit and the communication interface of the memory control switching circuit, and includes a second memory operation circuit including a second memory chip selection sub-circuit, a second memory clock sub-circuit, and a second memory read-write data sub-circuit.
In some embodiments of the present disclosure, the data receiving and transmitting circuit is an SPI pass-through circuit, and the memory unit is an SPI Flash memory chip.
In some embodiments of the present disclosure, the memory control switching circuit is connected to the memory control circuit and the at least one memory cell, and includes a memory selection and read-write control circuit, a third memory operation circuit, and a fourth memory operation circuit corresponding to the at least one memory cell; the memory selecting and reading/writing control circuit comprises a memory selecting circuit and at least one memory reading/writing control circuit, wherein the memory reading/writing control circuit corresponds to the memory units one by one; the third memory operation circuit is connected to the first memory operation circuit of the memory control circuit and comprises a memory chip selection receiving sub-circuit, a memory working clock receiving sub-circuit and a memory read-write data sub-circuit; the fourth memory operation circuit is connected to the second memory operation circuit of the re-injection data receiving and transmitting circuit, the first memory chip selection sub-circuit, the first memory clock sub-circuit, the first memory read-write data sub-circuit and the memory working mode switching sub-circuit.
According to another aspect of the present disclosure, there is provided a method for upgrading FPGA configuration data, wherein the step of updating the configuration code includes: step S0: the FPGA receives an instruction for determining to update the FPGA configuration code from the main control or the upper computer, erases the old configuration code to be replaced from the memory, and receives the configuration code data of the new version through the interface of the main control or the upper computer. Step S1: the controller unit of the circuit for upgrading the FPGA configuration data receives new code matching data transmitted by an external controller through a communication interface; step S2: after receiving the new configuration code data, the communication interface of the controller unit forwards the data to the memory control switching circuit; step S3: the memory control switching circuit writes data to a target address in the memory.
In some embodiments of the present disclosure, the step of performing the code matching version switching includes: step 10: pulling down the FPGA configuration reset signal and keeping the FPGA configuration reset signal for a period of time, so that the configuration logic of the FPGA is reset by the FPGA configuration reset signal, and restarting a new round of configuration process; step 11: the controller unit receives the target code allocation address through the communication interface; step 12: the controller unit reads the configuration code file according to the target configuration code address, and writes the configuration code file to the FPGA through the configuration interface, so that the FPGA completes configuration according to the re-injected new configuration code.
(III) beneficial effects
According to the technical scheme, the circuit and the method for upgrading the FPGA configuration data have at least one of the following beneficial effects:
(1) Because of the improvement of the control unit structure in the circuit, the matching code re-injection and the matching code version switching of the FPGA can be completed only by matching the FPGA with the circuit chip, and extra components are not needed, compared with the traditional method, the hardware cost of the system is reduced;
(2) In the aerospace application, after the spacecraft is launched and lifted off, the configuration code of the FPGA can be updated conveniently through a code updated data path;
(3) The supported code allocation version is more flexible, and the number of the code allocation versions is limited only by the size of a single code allocation file.
Drawings
Fig. 1 is a schematic structural diagram of a circuit for upgrading FPGA configuration data according to a first embodiment of the present disclosure.
Fig. 2 is a photomicrograph of an actual chip after circuit flow for upgrading FPGA configuration data according to a first embodiment of the present disclosure.
Fig. 3 (a) is a block diagram of a circuit controller unit for upgrading FPGA configuration data according to a first embodiment of the present disclosure.
Fig. 3 (b) is a diagram of the circuit internal connection relationship for upgrading FPGA configuration data according to the first embodiment of the present disclosure.
Fig. 4 is a block diagram of a system application when the package of the first embodiment of the present disclosure is used with an FPGA.
Fig. 5 is a schematic diagram of an implementation of the logic unit of the first embodiment of the present disclosure outside the FPGA chip.
Fig. 6 is a schematic diagram of data organization in a memory according to a first embodiment of the present disclosure.
Fig. 7 is a schematic diagram of data organization in a memory when multiple versions of a configuration code are stored according to a first embodiment of the disclosure.
Fig. 8 is a schematic structural diagram of a circuit for upgrading FPGA configuration data according to a second embodiment of the present disclosure.
Fig. 9 illustrates an exemplary implementation architecture for a second embodiment of the present disclosure when used with an FPGA.
Fig. 10 is a schematic diagram of a data link when the second embodiment of the present disclosure is used with an FPGA.
Description of the embodiments
For the purposes of promoting an understanding of the principles and advantages of the disclosure, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same.
Certain embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments are shown. Indeed, various embodiments of the disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements.
In a first exemplary embodiment of the present disclosure, a circuit for upgrading FPGA configuration data is provided. Fig. 1 is a schematic structural diagram of a circuit for upgrading FPGA configuration data according to a first embodiment of the present disclosure. As shown in fig. 1, a circuit for upgrading FPGA configuration data according to the present disclosure includes:
the package body internally comprises at least one memory unit and a controller unit, wherein the controller unit is connected to the memory unit and comprises JTAG processing circuits, memory control circuits, configuration control circuits, memory control switching circuits, version switching control circuits and a re-injection data receiving and transmitting circuit. As shown in fig. 1, the controller unit is provided with 4 external interfaces: (1) JTAG interface, (2) memory access and control interface, (3) FPGA configuration interface, and (4) communication interface. The memory access interface is used for performing operations such as reading, writing, erasing and the like on 1 or more memory units; the JTAG communication interface communicates with the upper computer through a JTAG circuit to transmit control information, address, data and other information; the FPGA configuration interface loads configuration codes of the power-on initialization configuration of the FPGA; when the circuit works in the code matching and re-injection mode, the communication interface receives code matching data information and other address information and control information sent by the FPGA; when the circuit works in the multi-version switching mode, the address information of the new version is received through the communication interface. The communication interface may be in the form of an SPI serial interface, a UART asynchronous serial interface, or an IIC interface.
The following describes each component of the circuit for upgrading FPGA configuration data in this embodiment in detail. The actual chip photo after the circuit for upgrading the configuration data of the FPGA is shown in fig. 2. The chip is prepared by adopting a wafer to carry out processes such as film deposition, photoresist coating, exposure, photoresist removal, etching, doping, thermal annealing and the like, and the packaging form comprises the following steps: QFP, QFN, PGA, BGA, etc.
Fig. 3 (a) is a block diagram of a circuit controller unit for upgrading FPGA configuration data according to a first embodiment of the present disclosure. As shown in fig. 3 (a), the circuit unit inside the controller unit includes:
(1) JTAG processing circuitry: the JTAG interface circuit is communicated with the upper computer through the JTAG interface circuit to transmit instructions, addresses and data.
The JTAG interface circuit comprises a JTAG clock interface, a JTAG mode interface and a plurality of interface circuits of a JTAG data input/output interface.
The first operation data processing circuit comprises an operation instruction detection extraction and output sub-circuit, an operation target address detection extraction and output sub-circuit, an operation response handshake signal output sub-circuit and a first data input and output sub-circuit, and is used for realizing transmission of operation instructions and operation addresses and transmission of data.
(2) A memory control circuit: the JTAG processing circuit comprises a second operation data processing circuit, a first memory operation circuit, a first read data circuit and a first version switching selection circuit, and realizes the read-write-erase function of the memory unit.
The second operation data processing circuit is connected to the first operation data processing circuit and comprises an operation instruction receiving sub-circuit, an operation target address receiving sub-circuit, an operation response handshake signal receiving sub-circuit and a second data input/output sub-circuit, and the second operation data processing circuit is used for receiving operation instructions and operation addresses and transmitting data.
The first memory operation circuit comprises a memory chip selection output sub-circuit, a memory working clock output sub-circuit and a memory read-write data sub-circuit, and is used for memory chip selection and data transmission with a memory.
The first read data circuit comprises a read data output sub-circuit and a read data request receiving sub-circuit, and is used for outputting configuration data to be read.
The first version switching selection circuit comprises a switching version target address receiving sub-circuit and a switching version request receiving sub-circuit, and is used for receiving the switching version target address.
(3) Configuration control circuit: the data storage unit is connected to the memory control circuit and comprises a second data reading circuit and an FPGA configuration circuit, and the received data in the storage unit is arranged into an interface form suitable for an FPGA configuration interface and is sent to the FPGA.
The second read data circuit is connected to the first read data circuit, and comprises a read data receiving sub-circuit and a read data enabling sub-circuit, and is used for requesting to read configuration data and receiving the configuration data.
The FPGA configuration circuit is connected to the FPGA configuration interface and is used for outputting clock and control signals and configuring the FPGA.
(4) Version switching control circuit: the system is connected to a memory control circuit, comprises a second version switching selection circuit and a first version switching configuration circuit, receives a version switching instruction, and analyzes an address of a target configuration code in a memory unit from the version switching instruction for addressing the memory unit in the next FPGA configuration.
The second version switching selection circuit is connected to the first version switching selection circuit, and comprises a switching version target address sending sub-circuit and a switching version enabling sub-circuit, and is used for receiving the switching version target address.
The version switching configuration circuit is connected to the communication interface and comprises a version switching chip selection sub-circuit, a version switching clock sub-circuit and a version switching read-write data sub-circuit.
(5) And the refill data receiving and transmitting circuit: the memory selecting circuit and the communication interface are connected to the memory control switching circuit, and comprise a second memory operating circuit, in particular a second memory chip selecting sub-circuit, a second memory clock sub-circuit and a second memory read-write data sub-circuit, and are used for receiving the re-injection data from the outside through the communication interface and sending the re-injection data to the memory control switching circuit or directly sending the data to the memory unit.
(6) A memory control switching circuit: the memory control circuit is connected with the at least one memory unit, comprises a memory selection and read-write control circuit corresponding to the at least one memory unit, a third memory operation circuit and a fourth memory operation circuit, and is used for switching between two links, namely a memory control logic and a reinjection data receiving and transmitting logic, and only 1 link is selected at any moment to control the memory.
The memory selecting and reading/writing control circuit comprises a memory selecting circuit and at least one memory reading/writing control circuit, the memory reading/writing control circuit corresponds to the memory units one by one, in some embodiments, the number of the memory units in the package is 3, the number of the memory reading/writing control circuits is also 3, and the memory selecting circuit is a three-mode voting circuit.
The third memory operation circuit is connected to the first memory operation circuit of the memory control circuit and comprises a memory chip selection receiving sub-circuit, a memory working clock receiving sub-circuit and a memory read-write data sub-circuit, and is used for memory chip selection and data transmission with a memory.
The fourth memory operation circuit is connected to the second memory operation circuit of the re-injection data receiving and transmitting circuit, the first memory chip selection sub-circuit, the first memory clock sub-circuit, the first memory read-write data sub-circuit and the memory working mode switching sub-circuit.
The connection relationship between circuits for upgrading the configuration data of the FPGA is shown in fig. 3 (a) and 3 (b), and the description of interface signals of each circuit in fig. 3 (a) and 3 (b) is shown in table 1.
TABLE 1
In this embodiment, when the package body of this embodiment is used in cooperation with an FPGA, a system application block diagram is shown in fig. 4.
1, logic cells within an fpga comprise:
version switching unit: according to the instruction of the upper computer or the running state of the FPGA, selecting a specific new version configuration code, and sending a version switching instruction to the controller unit in the package body of the embodiment.
A refill data transmission unit: the new configuration code is received from the upper computer communication link and sent to the controller unit of the present embodiment. If the controller unit of the present embodiment adopts an SPI interface for the external communication interface, the refill data transmitting unit in the FPGA may be regarded as an SPI master.
In some embodiments, the two units may be independent of each other; in other embodiments, the two units may be combined together.
The upper computer bus interface unit: and communicating with an upper computer through a bus to acquire the data of the reinjection allocation codes and acquire the version switching instruction. In some embodiments, the upper computer bus interface unit may be combined with the first 2 units.
In some embodiments, the logic unit in the FPGA may also be implemented off-chip in the form of a CPLD, a single-chip microcomputer, a microcontroller, etc., as shown in fig. 5.
At least one memory cell is provided in the package, typically 3 memory cells can be used, the data in each memory cell is the same, and 3 memories form a triple modular redundancy mechanism:
when the controller unit performs a write operation on the memories, the identical data is written into the 3 memories; in the case of reading, a two-out-of-three voting mechanism is performed on the data from 3 memory cells, so that even if the stored data in 1 memory cell is wrong for some reason, the final voting result is still correct, thereby improving the reliability of the circuit.
In the memory in the package, the code matching data of the FPGA is stored. The package may store 1 configuration file (i.e., only 1 configuration version), or may store multiple versions of configuration files (i.e., multi-version configuration). When data access is carried out in the memory, the data segments with specific size are taken as basic storage units, and each stored code matching file consists of 1 or more data segments.
For a small-scale FPGA chip, the data quantity of the code matching file is smaller, the data section occupied by a single code matching is also fewer, and the number of code matching versions which can be stored in the storage space with the same capacity is more; for a large-scale FPGA chip, the data quantity of the code matching file is larger, the data section occupied by a single code matching is more, and the number of code matching versions which can be stored in the storage space with the same capacity is smaller.
Assuming that the storage capacity of the memory is 256Mbit, when only 1 version of the allocation code is stored, the data organization in the memory is shown in fig. 6. When multiple versions of the code are stored, the organization of the data in memory is shown in FIG. 7. The code matching scale of the XC2V1000 FPGA is smaller and is only smaller than 4Mbit, so that a plurality of versions of code matching can be stored in a 256Mbit memory space; the code allocation scale of the XC2V3000 FPGA is about 10Mbit, and the number of versions which can be stored in 256Mbit space is much smaller; for the XC5VFX200T FPGA, the code matching and matching will be approximately 70Mbit, so that at most 3 versions of code matching files can be placed in 256Mbit space.
In order to ensure the system to work stably and reliably and avoid the complete failure of the system caused by misoperation such as full-chip erasure, the matching code at the lowest address in the storage unit is used as a guide area (also called as a reference version), and a write protection attribute is set.
The data (reference edition matching code) in the guide area can only be read and cannot be erased and written; only other storage areas outside the boot area may be erased, written, etc. Therefore, even if serious misoperation such as full-chip erasure occurs, the reference edition code matching file in the guide area is still intact, the power-on loading of the FPGA can be finished by means of the reference edition code matching file, and the FPGA is guaranteed to finish basic tasks.
Of course, the above hardware structure should further include functional units such as a power supply unit (not shown), and those skilled in the art will understand that, according to the functional needs, corresponding functional units may be added by those skilled in the art, which is not described herein.
In a second exemplary embodiment of the present disclosure, a circuit for upgrading FPGA configuration data is provided. Fig. 8 is a schematic diagram of a circuit for upgrading FPGA configuration data according to the present embodiment. In this embodiment, the storage unit is an SPI Flash memory chip, and the reinjection data receiving and transmitting circuit in the controller unit is an SPI pass-through link, as shown in fig. 8, and an SPI controller outside the package may directly control the SPI Flash memory through an SPI pass-through logic and an SPI switching logic.
FIG. 9 illustrates a typical implementation architecture when used with an FPGA. FIG. 10 is a schematic diagram of a data link when used with an FPGA. As shown in fig. 10, several data stream links of the present embodiment include:
(1) The JTAG upper computer, JTAG download line, JTAG interface of the controller unit, memory control interface, memory, read, write, erase and the like are carried out on the memory from the upper computer through the JTAG download line;
(2) Memory-controller unit-FPGA;
(3) The upper computer-the FPGA-the reinjection data sending unit-the communication interface-the controller unit-the storage unit;
(4) The method comprises the steps of loading the FPGA, a version switching unit, a communication interface, a controller unit, a storage unit, a configuration unit and a storage unit, wherein the controller unit reads data in a designated address.
For the sake of brevity, any description of the technical features of embodiment 1 that can be applied identically is incorporated herein, and the same description is not repeated.
In a third exemplary embodiment of the present disclosure, a method for upgrading FPGA configuration data is provided, where a method for updating a configuration code includes the following steps:
step S0: the FPGA receives an instruction for determining to update the FPGA configuration code from the main control or the upper computer, erases the old configuration code to be replaced from the memory, and receives the configuration code data of the new version through the interface of the main control or the upper computer.
Step S1: the controller unit of the circuit for upgrading the FPGA configuration data receives new code matching data transmitted by an external controller through a communication interface;
step S2: after receiving the new configuration code data, the communication interface of the controller unit forwards the data to the memory control switching circuit;
step S3: the memory control switching circuit writes data to a target address in the memory.
If it is desired to continue the code matching version switch after the code matching update, the following steps are sequentially performed:
step 10: the version switching unit pulls down the configuration reset signal prog_b of the FPGA and keeps the configuration logic of the FPGA for a period of time, so that the configuration logic of the FPGA is reset by the configuration reset signal prog_b of the FPGA, and a new round of configuration process is restarted;
step 11: the controller unit receives the target code allocation address through the communication interface;
step 12: the controller unit reads the configuration code file according to the target configuration code address, and writes the configuration code file to the FPGA through the configuration interface, so that the FPGA completes configuration according to the re-injected new configuration code.
For the sake of brevity, any description of the features of the embodiments described above that may be used in the same way is incorporated herein by reference, and no repetition of the description is necessary.
Thus, embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It should be noted that, in the drawings or the text of the specification, implementations not shown or described are all forms known to those of ordinary skill in the art, and not described in detail. Furthermore, the above definitions of the elements and methods are not limited to the specific structures, shapes or modes mentioned in the embodiments, and may be modified or replaced simply by one skilled in the art, for example:
(1) The memory unit can be SPI Flash or parallel NOR Flash.
(2) The version switching unit and the reinjection data receiving and forwarding unit can be located inside the FPGA, or can be located in a CPLD or a singlechip or a microcontroller or another control FPGA outside the FPGA.
(3) The communication interface can be an SPI interface, a UART interface or an IIC interface.
Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
The use of ordinal numbers such as "first," "second," "third," etc., in the description and the claims to modify a corresponding element does not by itself connote any ordinal number of elements or the order of manufacturing or use of the ordinal numbers in a particular claim, merely for enabling an element having a particular name to be clearly distinguished from another element having the same name.
Furthermore, unless specifically described or steps must occur in sequence, the order of the above steps is not limited to the list above and may be changed or rearranged according to the desired design. In addition, the above embodiments may be mixed with each other or other embodiments based on design and reliability, i.e. the technical features of the different embodiments may be freely combined to form more embodiments.
The disclosure may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. Various component embodiments of the present disclosure may be implemented in hardware, or in software elements running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that some or all of the functions of some or all of the components in a related device according to embodiments of the present disclosure may be implemented in practice using a microprocessor or Digital Signal Processor (DSP). The present disclosure may also be embodied as a device or apparatus program (e.g., computer program and computer program product) for performing a portion or all of the methods described herein. Such a program embodying the present disclosure may be stored on a computer readable medium, or may have the form of one or more signals. Such signals may be downloaded from an internet website, provided on a carrier signal, or provided in any other form.
All of the elements of the embodiments of the present disclosure may be hardware structures, the physical implementation of which includes but is not limited to physical devices including but not limited to transistors, memristors, DNA computers
Those skilled in the art will appreciate that the elements of the apparatus of an embodiment may be adaptively changed and disposed in one or more apparatuses different from the embodiment. The units or components of the embodiments may be combined into one unit or component, and furthermore they may be divided into a plurality of sub-units or sub-components. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Also, in the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware.
Similarly, it should be appreciated that in the above description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.
While the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be understood that the foregoing embodiments are merely illustrative of the invention and are not intended to limit the invention, and that any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.
Claims (9)
1. A circuit for upgrading FPGA configuration data, comprising:
a package having at least one memory unit and a controller unit therein,
the controller unit is connected to the memory unit, comprising: JTAG processing circuit, memory control circuit, configuration control circuit, memory control switching circuit, version switching control circuit, and re-injection data receiving and transmitting circuit;
the memory control circuit is connected to the JTAG processing circuit and comprises a second operation data processing circuit, a first memory operation circuit, a first read data circuit and a first version switching selection circuit; wherein,
the second operation data processing circuit is connected to the first operation data processing circuit and comprises an operation instruction receiving sub-circuit, an operation target address receiving sub-circuit, an operation response handshake signal receiving sub-circuit and a second data input/output sub-circuit, and is used for receiving operation instructions and operation addresses and transmitting data;
the first memory operation circuit comprises a memory chip selection output sub-circuit, a memory working clock output sub-circuit and a memory read-write data sub-circuit, and is used for memory chip selection and data transmission with a memory;
the first read data circuit comprises a read data output sub-circuit and a read data request receiving sub-circuit and is used for outputting configuration data to be read;
the first version switching selection circuit comprises a switching version target address receiving sub-circuit and a switching version request receiving sub-circuit, and is used for receiving the switching version target address.
2. The circuit of claim 1, the JTAG processing circuitry comprising JTAG interface circuitry and first operational data processing circuitry, connected to a host through the JTAG interface circuitry;
the JTAG interface circuit comprises a JTAG clock interface, a JTAG mode interface and a plurality of interface circuits of a JTAG data input/output interface;
the first operation data processing circuit comprises an operation instruction detection extraction and output sub-circuit, an operation target address detection extraction and output sub-circuit, an operation response handshake signal output sub-circuit and a first data input and output sub-circuit.
3. The circuit of claim 1, the configuration control circuit being connected to a memory control circuit comprising a second read data circuit and an FPGA configuration circuit, wherein,
the second read data circuit is connected to the first read data circuit and comprises a read data receiving sub-circuit and a read data enabling sub-circuit;
the FPGA configuration circuit is connected to the FPGA configuration interface.
4. The circuit of claim 1, the versioning control circuit connected to the memory control circuit, comprising a second versioning selection circuit and a first versioning configuration circuit, wherein,
the second version switching selection circuit is connected to the first version switching selection circuit and comprises a switching version target address transmitting sub-circuit and a switching version enabling sub-circuit;
the version switching configuration circuit is connected to the communication interface and comprises a version switching chip selection sub-circuit, a version switching clock sub-circuit and a version switching read-write data sub-circuit.
5. The circuit of claim 1, the refill data receiving and transmitting circuit connected to a memory selection circuit and a communication interface of a memory control switching circuit, comprising a second memory operation circuit comprising a second memory chip selection sub-circuit, a second memory clock sub-circuit, and a second memory read-write data sub-circuit.
6. The circuit of claim 1, wherein the refill data receiving and transmitting circuit is an SPI pass-through circuit and the memory unit is an SPI Flash memory chip.
7. The circuit of claim 1, the memory control switching circuit connected to the memory control circuit and the at least one memory cell, comprising a memory select and read-write control circuit, a third memory operating circuit, and a fourth memory operating circuit corresponding to the at least one memory cell; wherein,
the memory selecting and reading-writing control circuit comprises a memory selecting circuit and at least one memory reading-writing control circuit, and the memory reading-writing control circuit corresponds to the memory units one by one;
the third memory operation circuit is connected to the first memory operation circuit of the memory control circuit and comprises a memory chip selection receiving sub-circuit, a memory working clock receiving sub-circuit and a memory read-write data sub-circuit;
the fourth memory operation circuit is connected to the second memory operation circuit of the re-injection data receiving and transmitting circuit, the first memory chip selection sub-circuit, the first memory clock sub-circuit, the first memory read-write data sub-circuit and the memory working mode switching sub-circuit.
8. A method of upgrading FPGA configuration data, wherein the step of updating a configuration code comprises:
step S0: the FPGA receives an instruction for determining to update the FPGA configuration code, erases the old configuration code to be replaced from a memory, and receives new-version configuration code data through a main control interface or an upper computer interface;
step S1: the controller unit of the circuit for upgrading the FPGA configuration data receives new code matching data transmitted by an external controller through a communication interface;
step S2: after receiving the new configuration code data, the communication interface of the controller unit forwards the data to the memory control switching circuit;
step S3: the memory control switching circuit writes data to a target address in the memory;
the memory control circuit is connected to the JTAG processing circuit and comprises a second operation data processing circuit, a first memory operation circuit, a first read data circuit and a first version switching selection circuit; wherein,
the second operation data processing circuit is connected to the first operation data processing circuit and comprises an operation instruction receiving sub-circuit, an operation target address receiving sub-circuit, an operation response handshake signal receiving sub-circuit and a second data input/output sub-circuit, and is used for receiving operation instructions and operation addresses and transmitting data;
the first memory operation circuit comprises a memory chip selection output sub-circuit, a memory working clock output sub-circuit and a memory read-write data sub-circuit, and is used for memory chip selection and data transmission with a memory;
the first read data circuit comprises a read data output sub-circuit and a read data request receiving sub-circuit and is used for outputting configuration data to be read;
the first version switching selection circuit comprises a switching version target address receiving sub-circuit and a switching version request receiving sub-circuit, and is used for receiving the switching version target address.
9. The method of claim 8, wherein the step of performing a code matching version switch comprises:
step 10: pulling down the FPGA configuration reset signal and keeping the FPGA configuration reset signal for a period of time, so that the configuration logic of the FPGA is reset by the FPGA configuration reset signal, and restarting a new round of configuration process;
step 11: the controller unit receives the target code allocation address through the communication interface;
step 12: the controller unit reads the configuration code file according to the target configuration code address, and writes the configuration code file to the FPGA through the configuration interface, so that the FPGA completes configuration according to the re-injected new configuration code.
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| CN111124459B (en) * | 2018-10-31 | 2023-04-07 | 阿里巴巴集团控股有限公司 | Method and device for updating service logic of FPGA cloud server |
| CN110413299A (en) * | 2019-07-26 | 2019-11-05 | 成都天锐星通科技有限公司 | A kind of FPGA built-in code version loading method and electronic equipment |
| CN111104362B (en) * | 2019-12-24 | 2021-09-10 | 海光信息技术股份有限公司 | Device and method for configuring field programmable gate array and field programmable gate array |
| CN112364393B (en) * | 2020-11-16 | 2024-02-02 | 深圳市安信智控科技有限公司 | Method and device for integrating security computing function of FLASH memory |
| CN113835770B (en) * | 2021-11-30 | 2022-02-18 | 四川华鲲振宇智能科技有限责任公司 | Online replacement method and system for server management module |
| CN114237122A (en) * | 2021-12-17 | 2022-03-25 | 合肥腾芯微电子有限公司 | Circuit for configuring, readback and refreshing SRAM type FPGA and operation method |
| CN117076365B (en) * | 2023-10-13 | 2024-01-30 | 成都申威科技有限责任公司 | Method and system for controlling data transmissible peripheral interface of computer |
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