CN108306538B - Improved carrier phase-shift modulation method suitable for hybrid cascaded H-bridge multi-level inverter - Google Patents
Improved carrier phase-shift modulation method suitable for hybrid cascaded H-bridge multi-level inverter Download PDFInfo
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Abstract
The invention discloses an improved carrier phase shift modulation method suitable for a mixed cascade H-bridge multi-level inverter with a voltage ratio of 1: 2, and belongs to the technical field of multi-level converter PWM. TheThe method firstly uses sine modulation wave vrefObtaining the absolute value of the modulated wave vmV modulated wave vmAnd a main triangular carrier vca、vcb、vccAnd secondary triangular carrier vcr1、vcr2、vcr3The comparison is carried out to obtain six logic pulse signals A, B, C, R1、R2、R3Sine modulated wave vrefComparing with zero voltage to obtain polarity pulse signal D. The six logic pulse signals and the polarity pulse signal are then passed through a drive logic operation circuit to generate an optimized PWM drive signal. The method can ensure that the auxiliary unit is added to increase the output level number and equivalent switching frequency of the inverter under the condition that the power of the main power unit is balanced and distributed, and improve the practicability of the inverter.
Description
Technical Field
The invention belongs to the technical field of multi-level converter PWM, and particularly relates to an improved carrier phase shift modulation method suitable for a mixed cascade H-bridge multi-level inverter with a voltage ratio of 1: 2.
Background
The traditional two-level power conversion technology is not suitable for high-voltage and high-power occasions due to the influences of voltage resistance of power devices, harmonic performance of output voltage and the like, and even the two-level high-voltage and high-power conversion technology adopting the direct serial connection of the power devices has a series of problems of static and dynamic voltage sharing and the like. The multi-level power conversion technology reduces the voltage stress of the power device, reduces the harmonic content of the output voltage, reduces the electromagnetic interference caused by dv/dt and becomes a research hotspot of the high-voltage high-power conversion technology under the condition of not solving the problems of series connection voltage-sharing and the like of the power device.
Common multilevel converters include diode clamp type, flying capacitor type, and cascade H-bridge type. The cascaded H-bridge inverter has no voltage unbalance problem, does not need a clamping diode or a flying capacitor, is one of multi-level inverters which output the same number of levels and needs the least devices, and has the characteristics of modularization, phase voltage redundancy and the like. However, a plurality of isolated direct current power supplies are needed, and the problem that the input direct current power supplies are required to be isolated is naturally solved in a high-power occasion of adopting a storage battery, a solar battery or a fuel cell to supply power, so that the method is a very suitable topology selection. Compared with an isobaric cascade H-bridge topology, the hybrid cascade H-bridge topology can output more levels with fewer power devices and direct-current power supplies, and has a greater application value and a wide development prospect in the field of high-voltage high-power conversion.
Because each cascade unit is independent, when the active power is transmitted, the power balance problem needs to be considered. The characteristics of the modulation method cause different output powers of all the cascade units, so that the charging and discharging of the battery are unbalanced, the voltage difference between input power supplies such as a storage battery and a solar battery is increased, the harmonic content of the output voltage of the inverter is increased, the service lives of all the unit batteries are different, and the maintenance cost of the system is increased, and therefore, the output powers of all the cascade units need to be balanced and controlled. Researches show that the carrier phase shift modulation can naturally realize power equalization, and is particularly suitable for isobaric cascade H-bridge topology, but for mixed cascade H-bridge topology, the method is difficult to directly adopt.
Fig. 1 shows a hybrid cascaded H-bridge multi-level inverter topology, which is different from the conventional isobaric cascaded H-bridge type topology in that n H-bridge units are cascaded, except for unit 1 (auxiliary unit), the dc sides of the other n-1 cascaded units (main power unit) are all voltage sources, and the voltages of the dc sides are equal, that is, Vdc2＝Vdc3＝…＝VdcnE; the DC side of the unit 1 is a capacitor, and the DC side voltage is only half of that of the rest units, i.e. Vdc10.5E. The modulation method can be realized on the basis of keeping the advantages of the isobaric cascade H-bridge topology: 1) the number of output levels increases. The output level number of the other n-1 main power units except the auxiliary unit is 2n-1, and after the auxiliary unit is added, the total output level number can reach 4 n-3. 2) The output equivalent switching frequency increases. By adopting the modulation method, the equivalent switching frequency of the output voltage of the n-1 main power units is n-1 times of the actual switching frequency of the switching tube, and after the auxiliary unit is added, the frequency multiplication of the output voltage of the inverter is realized on the basis, so that the equivalent switching frequency can reach 2(n-1) times. The modulation method of the invention uses the traditional carrierThe wave phase shift modulation is improved, so that the wave phase shift modulation can be well applied to a hybrid cascade H bridge multi-level inverter, the quality of the output voltage waveform is greatly improved, and the wave phase shift modulation has important theoretical and practical significance. The invention takes 4 cascade units as an example, and analyzes the improved carrier phase shift modulation principle and the realization method which are suitable for the topology in detail.
Disclosure of Invention
Object of the Invention
The invention aims to provide an improved carrier phase shift modulation method suitable for a mixed cascade H-bridge multi-level inverter with a voltage ratio of 1: 2, and under the condition of satisfying the power balance distribution of a main power unit, the addition of an auxiliary unit realizes the increase of the output level number and the output equivalent switching frequency of the inverter, so that the harmonic characteristic of the output voltage of a system is improved, and the practicability of the multi-level inverter is improved.
Technical scheme
The technical scheme of the invention is as follows:
(1) the hybrid cascade H-bridge multi-level inverter is formed by cascading n H-bridge units, wherein the unit 1 is an auxiliary unit, the direct current side of the auxiliary unit is a capacitor, and the voltage of the direct current side of the auxiliary unit is only half of the voltage of the direct current sides of the other units, namely Vdc10.5E; the other n-1 cascade units are main power units, the direct current sides are all voltage sources, and the voltages of the direct current sides are equal, namely Vdc2＝Vdc3＝…＝Vdcn＝E。
(2) The implementation circuit of the method comprises a logic pulse generation circuit and a driving logic operation circuit. The logic pulse generating circuit is composed of sine modulating wave (v)ref) Absolute value arithmetic circuit (Abs), and main triangular carrier wave (v)ca、vcb、vcc) Auxiliary triangular carrier (v)cr1、 vcr2、vcr3) And seven comparators (T)1～T7) Composition is carried out; the drive logic operation circuit comprises 20 NOT gates (X)1～X20) 19 double-input AND gates (Y)1～Y19) 2 three-input AND gates (Y)20～Y21) 5 double input OR gates (Z)1～Z5) And 6 three-input OR gates (Z)6～Z11) And (4) forming. Wherein, the main triangular carrier wave (v)ca、vcb、vcc) All frequencies are fcThe peak values are all 3E and are between 0 and 3E; auxiliary triangular carrier (v)cr1、vcr2、vcr3) All frequencies are 3fcThe peak value is E, and the auxiliary triangular carrier vcr1Between 0 and E, secondary triangular carrier vcr2Between E and 2E, secondary triangular carrier vcr3Between 2E and 3E. The main triangular carrier wave v is taken as a referencecaA main triangular carrier vcbAnd a main triangular carrier vccThe phase difference is 120 degrees; auxiliary triangular carrier vcr1The phase difference between the intersection point of the auxiliary triangular carrier and the zero reference line and the phase difference between the intersection points of the three main triangular carriers and the zero reference line are 60 degrees, and the phase difference between the auxiliary triangular carrier v and the zero reference line iscr3Phase of and auxiliary triangular carrier vcr1Are in the same phase, and auxiliary triangular carriers vcr2Phase of and auxiliary triangular carrier vcr1The phase difference of the three secondary triangular carriers is 60 degrees, namely, the three secondary triangular carriers are arranged in an alternate reverse stacking mode.
(3) In the logic pulse generating circuit: sine modulation wave vrefThe output signal of the absolute value arithmetic circuit Abs is a modulated wave v connected with the input end of the absolute value arithmetic circuit AbsmV modulated wave vmRespectively connected to comparators T1～T3、T5～T7Of the positive phase input terminal of, the main triangular carrier vcaIs connected with a comparator T1Of the inverting input terminal, the main triangular carrier vcbIs connected with a comparator T2Of the inverting input terminal, the main triangular carrier vccIs connected with a comparator T3Of the inverted input terminal, auxiliary triangular carrier vcr1Is connected with a comparator T5Of the inverted input terminal, auxiliary triangular carrier vcr2Is connected with a comparator T6Of the inverted input terminal, auxiliary triangular carrier vcr3Is connected with a comparator T7Of the sine-modulated wave vrefIs connected with a comparator T4Of the positive phase input terminal, comparator T4The inverting input terminal of the voltage regulator is connected with a zero reference potential.
(4) In the drive logic operation circuit: comparator T1The output end is connected with the NOT gate X1Post-sum comparator T4Output of (2) is connected with an OR gate Z1Two inputs of, or-gates Z1As the switching tube Q21Drive signal of, OR gate Z1The output end of the inverter is connected with a NOT gate X4The output signal is used as a switch tube Q22The drive signal of (1); comparator T1And comparator T4The output end of the voltage regulator is connected with an AND gate Y1Two input terminals of AND gate Y1As the switching tube Q24Of the driving signal AND-gate Y1The output end of the inverter is connected with a NOT gate X7The output signal is used as a switch tube Q23The drive signal of (1); comparator T2The output end is connected with the NOT gate X2Post-sum comparator T4Output of (2) is connected with an OR gate Z2Two inputs of, or-gates Z2As the switching tube Q31Drive signal of, OR gate Z2The output end of the inverter is connected with a NOT gate X5The output signal is used as a switch tube Q32The drive signal of (1); comparator T2And comparator T4The output end of the voltage regulator is connected with an AND gate Y2Two input terminals of AND gate Y2As the switching tube Q34Of the driving signal AND-gate Y2The output end of the inverter is connected with a NOT gate X8The output signal is used as a switch tube Q33The drive signal of (1); comparator T3The output end is connected with the NOT gate X3Post-sum comparator T4Output of (2) is connected with an OR gate Z3Two inputs of, or-gates Z3As the switching tube Q41Drive signal of, OR gate Z3The output end of the inverter is connected with a NOT gate X6The output signal is used as a switch tube Q42The drive signal of (1); comparator T3And comparator T4The output end of the voltage regulator is connected with an AND gate Y3Two input terminals of AND gate Y3As the switching tube Q44Of the driving signal AND-gate Y3The output end of the inverter is connected with a NOT gate X9The output signal is used as a switch tube Q43The drive signal of (1); comparator T1～T3、 T5～T7The output end of the auxiliary signal operation module is connected with the auxiliary signal operation module, and the output of the auxiliary signal operation module is a signal L1And L2Signal L1NOT gate X11Comparator T4The output end of the inverter is connected with a NOT gate X10NOT gate X11And not gate X10The output end of the voltage regulator is connected with an AND gate Y4Two input terminals of signal L1And a comparator T4The output end of the voltage regulator is connected with an AND gate Y6Two input terminals of AND gate Y4And AND gate Y6Output of (2) is connected with an OR gate Z4Two inputs of, or-gates Z4As the switching tube Q11Drive signal of, OR gate Z4The output end of the inverter is connected with a NOT gate X13The output signal is used as a switch tube Q12The drive signal of (1); signal L2NOT gate X12Comparator T4The output end of the inverter is connected with a NOT gate X10NOT gate X12And not gate X10The output end of the voltage regulator is connected with an AND gate Y5Two input terminals of signal L2And a comparator T4The output end of the voltage regulator is connected with an AND gate Y7Two input terminals of AND gate Y5And AND gate Y7Output of (2) is connected with an OR gate Z5Two inputs of, or-gates Z5As the switching tube Q13Drive signal of, OR gate Z5The output end of the inverter is connected with a NOT gate X14The output signal is used as a switch tube Q14The drive signal of (1).
In the auxiliary signal operation module: comparator T1The output end of the inverter is connected with a NOT gate X15Input terminal of, comparator T2The output end of the inverter is connected with a NOT gate X16Input terminal of, comparator T3The output end of the inverter is connected with a NOT gate X17Input terminal of, NOT-gate X15Output terminal of, not gate X16And not gate X17The output end of the voltage regulator is connected with an AND gate Y20Three input terminals of, not gate X15And not gate X16The output end of the voltage regulator is connected with an AND gate Y8Two input terminals of, NOT-gate X16And not gate X17The output end of the voltage regulator is connected with an AND gate Y9Two input terminals of, NOT-gate X17And not gate X15The output end of the voltage regulator is connected with an AND gate Y10Two input terminals of, NOT-gate X15Output terminal of, not gate X16And not gate X17Output of (2) is connected with an OR gate Z6And gate Y8Output terminal of and gate Y9And AND gate Y10Output of (2) is connected with an OR gate Z8And gate Y20And comparator T5The output end of the voltage regulator is connected with an AND gate Y14Two inputs of, or-gates Z8And comparator T6The output end of the voltage regulator is connected with an AND gate Y15Two inputs of, or-gates Z6And comparator T7The output end of the voltage regulator is connected with an AND gate Y16Two input terminals of AND gate Y14Output terminal of and gate Y15And AND gate Y16Output of (2) is connected with an OR gate Z10Three inputs of, or-gates Z10Is the signal L1(ii) a Comparator T1Output terminal of (1), comparator T2And comparator T3The output end of the voltage regulator is connected with an AND gate Y21Three input terminals of, comparator T1And comparator T2The output end of the voltage regulator is connected with an AND gate Y11Two input terminals of, comparator T2And comparator T3The output end of the voltage regulator is connected with an AND gate Y12Two input terminals of, comparator T3And comparator T1The output end of the voltage regulator is connected with an AND gate Y13Two input terminals of, comparator T1Output terminal of (1), comparator T2And comparator T3Output of (2) is connected with an OR gate Z7And gate Y11Output terminal of and gate Y12And AND gate Y13Output of (2) is connected with an OR gate Z9Three input terminals of, comparator T7Is output through NOT gate X20Back and gate Y21The output end of the voltage regulator is connected with an AND gate Y17Two input terminals of, comparator T6Is output through NOT gate X19Rear OR gate Z9The output end of the voltage regulator is connected with an AND gate Y18Two input terminals of, comparator T5Is output through NOT gate X18Rear OR gate Z7The output end of the voltage regulator is connected with an AND gate Y19Two input terminals of AND gate Y17Output terminal of and gate Y18And AND gate Y19Output of (2) is connected with an OR gate Z11Three inputs of, or-gates Z11Is the signal L2。
Advantageous effects
The method can ensure that the hybrid cascade H bridge multi-level inverter with the voltage ratio of 1: 2 adopts the auxiliary unit to realize the increase of the output level number and the output equivalent switching frequency of the inverter under the condition of meeting the balanced distribution of the power of the main power unit, thereby improving the output characteristic of the system and improving the practicability of the multi-level inverter.
Drawings
The invention is further illustrated by the following figures and examples.
Fig. 1 is a hybrid cascaded H-bridge multi-level inverter main circuit.
Fig. 2 is a schematic diagram of an improved carrier phase shift modulation scheme according to the present invention.
Fig. 3 is a schematic diagram of the improved carrier phase shift modulation method in region V (0.5-1).
FIG. 4 is an output region division of the main power unit within region V (0-1).
FIG. 5 is the output area division of the auxiliary unit within area V (0-1).
Fig. 6 is a schematic circuit implementation diagram of the improved carrier phase shift modulation method provided by the invention.
Fig. 7 shows the output voltage of the cascade unit, the total output voltage of the main power unit and the output voltage waveform of the cascade inverter after applying the improved carrier phase shift modulation method provided by the invention.
Fig. 8 is a frequency spectrum analysis of the total output voltage waveform of the main power unit after applying the improved carrier phase shift modulation method provided by the invention.
Fig. 9 is a frequency spectrum analysis of the output voltage waveform of the hybrid cascaded H-bridge inverter after applying the improved carrier phase shift modulation method provided by the present invention.
Fig. 10 shows the output power of the cascade unit and the output power waveform of the cascade inverter after applying the improved carrier phase shift modulation method provided by the present invention.
Detailed Description
Taking four H-bridge unit cascades as an example, the improved carrier phase shift modulation principle suitable for the hybrid cascade H-bridge multi-level inverter provided by the invention is analyzed. In this case, the topology comprises an auxiliary unit, i.e. unit 1, whose dc side is a capacitor and whose dc side voltage V is a voltagedc10.5E, the AC side output voltage is vo1(ii) a Three main power units, namely unit 2, unit 3 and unit 4, are all voltage sources on the direct current side, and the voltage V on the direct current sidedc2＝Vdc3＝Vdc4E, the ac side output voltages are each vo2、vo3And vo4. The three main power units can generate 7 different levels, the voltage difference between adjacent levels is E, after the auxiliary unit is added, the hybrid cascade inverter can generate 13 different levels, the voltage difference between adjacent levels is 0.5E, and the equivalent switching frequency of the output voltage of the inverter can be multiplied.
For the inverter topology, the modulation method of the present invention requires six triangular carriers in total: three main triangular carriers (v)ca、 vcb、vcc) And three secondary triangular carriers (v)cr1、vcr2、vcr3). Wherein, the main triangular carrier wave (v)ca、vcb、vcc) All frequencies are fcThe peak values are all 3E and are between 0 and 3E; auxiliary triangular carrier (v)cr1、vcr2、vcr3) All frequencies are 3fcThe peak value is E, and the auxiliary triangular carrier vcr1Between 0 and E, secondary triangular carrier vcr2Between E and 2E, secondary triangular carrier vcr3Between 2E and 3E. The main triangular carrier wave v is taken as a referencecaA main triangular carrier vcbAnd a main triangular carrier vccThe phase difference is 120 degrees; auxiliary triangular carrier vcr1The phase difference between the intersection point of the auxiliary triangular carrier and the zero reference line and the phase difference between the intersection points of the three main triangular carriers and the zero reference line are 60 degrees, and the phase difference between the auxiliary triangular carrier v and the zero reference line iscr3Phase of and auxiliary triangular carrier vcr1Are in the same phase, and auxiliary triangular carriers vcr2Phase of and auxiliary triangular carrier vcr1The phase difference of the three secondary triangular carriers is 60 degrees, namely, the three secondary triangular carriers are arranged in an alternate reverse stacking mode.
The three main triangular carriers equally divide the whole voltage plane into three areas in the vertical direction, and the three areas are V (0-1), V (1-2) and V (2-3) from bottom to top in sequence. After the auxiliary triangular carrier is introduced, the whole voltage plane is divided into six areas equally according to the vertical direction by the six carriers, and the six areas are V (0-0.5), V (0.5-1), V (1-1.5), V (1.5-2), V (2-2.5) and V (2.5-3) from bottom to top in sequence. Here, V (y-z) represents a sine-modulated wave VrefFalls in the voltage interval [ yE, zE]Where 0 < y < z < 3, y ∈ {0, 0.5, 1, 1.5, 2, 2.5}, z ∈ {0.5, 1, 1.5, 2, 2.5, 3 }. Carrier distribution and sinusoidal modulated wave vrefThe modulation principle in each region is shown in FIG. 2, and is explained in detail below with reference to region V (0-1).
For sine modulation wave vrefCarrying out absolute value calculation to obtain a modulated wave vmV modulated wave vmRespectively associated with the main triangular carrier vca、vcb、vccComparing to obtain logic pulse signals A, B and C; modulated wave vmRespectively associated with auxiliary triangular carriers vcr1、vcr2、vcr3Comparing to obtain logic pulse signal R1、R2And R3(ii) a Sine modulation wave vrefThe polarity pulse signal D is directly compared with the zero reference voltage, and the signal D is constantly at a high level in a positive half period and constantly at a zero level in a negative half period.
Figure 3 shows a sine-modulated wave vrefThe modulation principle falling in the region V (0.5-1).
1) Acquisition of main power unit drive logic signal
In the positive half period, the left bridge arm is used as a direction arm, and the switching tube Q21、Q31、Q41The driving logic signals are all D when the switch is switched on constantly; the right arm is used as chopper arm and switching tube Q24、Q34、Q44The drive signal of (a) is composed of a modulated wave vmWith three main triangular carriers vca、vcb、vccThe comparison results in that:
in order to balance the switching frequency of the left and right bridge arms of each unit, in the negative half period, the right bridge arm is used as a direction arm, and a switching tube Q23、Q33、 Q43Constantly on, with driving logic signals all
The left bridge arm is used as a chopper arm and a switching tube Q22、Q32、Q42The drive signal of (a) is composed of a modulated wave vmWith three main triangular carriers vca、vcb、vccThe comparison results in that:
the driving logic signals of the three main power unit switching tubes in the positive half period and the negative half period are shown in table 1.
TABLE 1 drive logic signals for main power unit switching tube
With reference to table 1, the driving logic signals in the positive and negative half periods are combined together to obtain the driving logic signals of the switching tubes of the three main power units in one whole period:
2) acquisition of auxiliary unit switching tube driving logic signal
In region V (0-1), a triangular carrier group (V)ca，vcb，vcc，vcr1) The modulation wave is divided into a plurality of triangular or rhombic areas, each area can be named by binary data of a four-digit number, if the modulation wave is larger than a corresponding carrier wave, the numerical value of the corresponding position is 1, otherwise, the numerical value of the corresponding position is 0. For example, (0000) means that the modulated waves are each less than fourA region of carriers; (0100) indicating that the modulated wave is smaller than the carrier wave vca、vccAnd vcr1And is greater than the carrier vcbThe area of (a).
As can be seen in connection with fig. 4, three main triangular carriers vca，vcb，vccThe region V (0-1) is divided into two parts, namely a part (000x) region in which the sum of the output voltages of the three main power units is constant 0, and a part (100x) ∪ (010x) ∪ (001x) region in which the sum of the output voltages of the three main power units is constant E, wherein x is a modulated wave VmAnd carrier vcr1The value of (3) is 1 or 0.
(1) (000x) region:
if x is 0 (v)m＜vcr1) When the expected output of the inverter is 0 level, the sum of the output voltages of the three main power units is 0 level, and therefore, the auxiliary unit needs to output 0 level;
if x is 1 (v)m＞vcr1) The desired output of the inverter is now at level 0.5E, while the sum of the three main power units output voltage is at 0 level, so the auxiliary unit needs to output level 0.5E.
(2) (100x) ∪ (010x) ∪ (001x) region:
if x is 0 (v)m＜vcr1) When the expected output of the inverter is level 0.5E, the sum of the output voltages of the three main power units is level E, and therefore, the auxiliary unit needs to output level-0.5E;
if x is 1 (v)m＞vcr1) At this time, the desired output of the inverter is level E, and the sum of the output voltages of the three main power units is level E, so that the auxiliary unit needs to output 0 level.
In summary, the auxiliary units output levels 0, 0.5E or-0.5E in different regions, respectively. The distribution of these regions is given in fig. 5. Wherein the region of the output level 0.5E is (0001), and the unified expression thereof is
The region of the output level-0.5E is (1000) ∪ (0100) ∪ (0010), which is uniformIs expressed as
The auxiliary unit outputs a 0 level in the remaining region. Therefore, in the region V (0-1), the drive logic expression of the auxiliary unit can be expressed as:
similarly, in the region V (1-2), the region of the auxiliary cell output level 0.5E is (0011) ∪ (1001) ∪ (0101), which is uniformly expressed as
The region of the output level-0.5E is (0110) ∪ (1010) ∪ (1100), whose unified expression is
The auxiliary unit outputs a 0 level in the remaining region. Therefore, in the region V (1-2), the drive logic expression of the auxiliary unit can be expressed as:
in the region V (2-3), the region of the auxiliary cell output level 0.5E is (0111) ∪ (1011) ∪ (1101), which is uniformly expressed as
The region of output level-0.5E is (1110), which is uniformly expressed as
The auxiliary unit outputs a 0 level in the remaining region. Therefore, in the region V (2-3), the drive logic expression of the auxiliary unit can be expressed as:
the drive logic expressions of the auxiliary units in the three areas are combined, and the drive logic expression of the switching tube of the auxiliary unit in the positive half period is obtained as follows:
similarly, in the negative half period, the driving logics of the other two switching tubes have the same rule:
the driving logic signals of the positive half period and the negative half period are combined, and the driving logic expression of the auxiliary unit in the whole period can be obtained as follows:
fig. 6 is a schematic diagram of a circuit implementation of the above improved carrier phase shift modulation principle, and the circuit implementation is composed of a logic pulse generating circuit and a driving logic operation circuit. Wherein the logic pulse generating circuit is composed of sine modulation wave (v)ref) Absolute value arithmetic circuit (Abs), and main triangular carrier wave (v)ca、vcb、vcc) Auxiliary triangular carrier (v)cr1、vcr2、vcr3) And seven comparators (T)1～T7) Is formed by modulating wave and carrier wave and comparing zero voltage to generate six logic pulse signals A, B, C, R1、R2、R3And a polarity pulse signal D. The drive logic operation circuit comprises 20 NOT gates (X)1～X20) 19 double-input AND gates (Y)1～Y19) 2 three-input AND gates (Y)20～Y21) 5 double input OR gates (Z)1～Z5) And 6 three-input OR gates (Z)6～Z11) The function of the composition is to realize the driving logic rule described by the unified mathematical logic expression. The implementation principle is described in detail as follows:
in logicIn the pulse generating circuit: sine modulation wave vrefThe output signal of the absolute value arithmetic circuit Abs is a modulated wave v connected with the input end of the absolute value arithmetic circuit AbsmV modulated wave vmRespectively connected to comparators T1～T3、T5～T7Of the positive phase input terminal of, the main triangular carrier vcaIs connected with a comparator T1Of the inverting input terminal, the main triangular carrier vcbIs connected with a comparator T2Of the inverting input terminal, the main triangular carrier vccIs connected with a comparator T3Of the inverted input terminal, auxiliary triangular carrier vcr1Is connected with a comparator T5Of the inverted input terminal, auxiliary triangular carrier vcr2Is connected with a comparator T6Of the inverted input terminal, auxiliary triangular carrier vcr3Is connected with a comparator T7Of the sine-modulated wave vrefIs connected with a comparator T4Of the positive phase input terminal, comparator T4The inverting input terminal of the voltage regulator is connected with a zero reference potential.
In the drive logic operation circuit: comparator T1The output end is connected with the NOT gate X1Post-sum comparator T4Output of (2) is connected with an OR gate Z1Two inputs of, or-gates Z1As the switching tube Q21Drive signal of, OR gate Z1The output end of the inverter is connected with a NOT gate X4The output signal is used as a switch tube Q22The drive signal of (1); comparator T1And comparator T4The output end of the voltage regulator is connected with an AND gate Y1Two input terminals of AND gate Y1As the switching tube Q24Of the driving signal AND-gate Y1The output end of the inverter is connected with a NOT gate X7The output signal is used as a switch tube Q23The drive signal of (1); comparator T2The output end is connected with the NOT gate X2Post-sum comparator T4Output of (2) is connected with an OR gate Z2Two inputs of, or-gates Z2As the switching tube Q31Drive signal of, OR gate Z2The output end of the inverter is connected with a NOT gate X5The output signal is used as a switch tube Q32The drive signal of (1); comparator T2And comparator T4The output end of the voltage regulator is connected with an AND gate Y2Two input terminals of, anddoor Y2As the switching tube Q34Of the driving signal AND-gate Y2The output end of the inverter is connected with a NOT gate X8The output signal is used as a switch tube Q33The drive signal of (1); comparator T3The output end is connected with the NOT gate X3Post-sum comparator T4Output of (2) is connected with an OR gate Z3Two inputs of, or-gates Z3As the switching tube Q41Drive signal of, OR gate Z3The output end of the inverter is connected with a NOT gate X6The output signal is used as a switch tube Q42The drive signal of (1); comparator T3And comparator T4The output end of the voltage regulator is connected with an AND gate Y3Two input terminals of AND gate Y3As the switching tube Q44Of the driving signal AND-gate Y3The output end of the inverter is connected with a NOT gate X9The output signal is used as a switch tube Q43The drive signal of (1); comparator T1～T3、T5～T7The output end of the auxiliary signal operation module is connected with the auxiliary signal operation module, and the output of the auxiliary signal operation module is a signal L1And L2Signal L1NOT gate X11Comparator T4The output end of the inverter is connected with a NOT gate X10NOT gate X11And not gate X10The output end of the voltage regulator is connected with an AND gate Y4Two input terminals of signal L1And a comparator T4The output end of the voltage regulator is connected with an AND gate Y6Two input terminals of AND gate Y4And AND gate Y6Output of (2) is connected with an OR gate Z4Two inputs of, or-gates Z4As the switching tube Q11Drive signal of, OR gate Z4The output end of the inverter is connected with a NOT gate X13The output signal is used as a switch tube Q12The drive signal of (1); signal L2NOT gate X12Comparator T4The output end of the inverter is connected with a NOT gate X10NOT gate X12And not gate X10The output end of the voltage regulator is connected with an AND gate Y5Two input terminals of signal L2And a comparator T4The output end of the voltage regulator is connected with an AND gate Y7Two input terminals of AND gate Y5And AND gate Y7Output of (2) is connected with an OR gate Z5Two inputs of, or-gates Z5As the switching tube Q13Drive signal of, OR gate Z5The output end of the inverter is connected with a NOT gate X14The output signal is used as a switch tube Q14The drive signal of (1).
In the auxiliary signal operation module: comparator T1The output end of the inverter is connected with a NOT gate X15Input terminal of, comparator T2The output end of the inverter is connected with a NOT gate X16Input terminal of, comparator T3The output end of the inverter is connected with a NOT gate X17Input terminal of, NOT-gate X15Output terminal of, not gate X16And not gate X17The output end of the voltage regulator is connected with an AND gate Y20Three input terminals of, not gate X15And not gate X16The output end of the voltage regulator is connected with an AND gate Y8Two input terminals of, NOT-gate X16And not gate X17The output end of the voltage regulator is connected with an AND gate Y9Two input terminals of, NOT-gate X17And not gate X15The output end of the voltage regulator is connected with an AND gate Y10Two input terminals of, NOT-gate X15Output terminal of, not gate X16And not gate X17Output of (2) is connected with an OR gate Z6And gate Y8Output terminal of and gate Y9And AND gate Y10Output of (2) is connected with an OR gate Z8And gate Y20And comparator T5The output end of the voltage regulator is connected with an AND gate Y14Two inputs of, or-gates Z8And comparator T6The output end of the voltage regulator is connected with an AND gate Y15Two inputs of, or-gates Z6And comparator T7The output end of the voltage regulator is connected with an AND gate Y16Two input terminals of AND gate Y14Output terminal of and gate Y15And AND gate Y16Output of (2) is connected with an OR gate Z10Three inputs of, or-gates Z10Is the signal L1(ii) a Comparator T1Output terminal of (1), comparator T2And comparator T3The output end of the voltage regulator is connected with an AND gate Y21Three input terminals of, comparator T1And comparator T2Is connected to the output terminalAnd gate Y11Two input terminals of, comparator T2And comparator T3The output end of the voltage regulator is connected with an AND gate Y12Two input terminals of, comparator T3And comparator T1The output end of the voltage regulator is connected with an AND gate Y13Two input terminals of, comparator T1Output terminal of (1), comparator T2And comparator T3Output of (2) is connected with an OR gate Z7And gate Y11Output terminal of and gate Y12And AND gate Y13Output of (2) is connected with an OR gate Z9Three input terminals of, comparator T7Is output through NOT gate X20Back and gate Y21The output end of the voltage regulator is connected with an AND gate Y17Two input terminals of, comparator T6Is output through NOT gate X19Rear OR gate Z9The output end of the voltage regulator is connected with an AND gate Y18Two input terminals of, comparator T5Is output through NOT gate X18Rear OR gate Z7The output end of the voltage regulator is connected with an AND gate Y19Two input terminals of AND gate Y17Output terminal of and gate Y18And AND gate Y19Output of (2) is connected with an OR gate Z11Three inputs of, or-gates Z11Is the signal L2。
Fig. 7 shows the output voltage of the cascade unit, the total output voltage of the main power unit and the total output voltage waveform of the cascade inverter of the hybrid cascade H-bridge inverter after applying the improved carrier phase shift modulation method provided by the present invention. It can be seen that, after the auxiliary unit is added, the number of inverter output levels is changed from the original 7 levels to 13 levels.
Fig. 8 is a frequency spectrum analysis of the total output voltage waveform of the main power unit of the hybrid cascade H-bridge inverter after applying the improved carrier phase shift modulation method provided by the invention, and fig. 9 is a frequency spectrum analysis of the total output voltage waveform of the hybrid cascade H-bridge inverter after adding the auxiliary unit. It can be seen that, after the auxiliary unit is added, the modulation method of the invention realizes frequency multiplication of the output voltage, and the high frequency harmonics of the output voltage are shifted to higher frequencies.
FIG. 10 shows an improved carrier phase shift modulator using the present inventionAfter the method, the output power of the cascade unit of the cascade H-bridge inverter and the output power waveform of the cascade inverter are mixed. Wherein, the active power output by the three main power units is Po2＝646W、Po3＝646W、Po4646W, the total output active power of the inverter is Po1938W. It can be seen that the active power output by the main power unit is evenly distributed, the sum of the output active power is equal to the total output active power of the inverter, and the auxiliary unit only compensates the high-frequency harmonic reactive power and does not participate in the transmission of the active energy.
Claims (2)
1. An improved carrier phase shift modulation method suitable for a hybrid cascade H bridge multi-level inverter is characterized by comprising the following steps:
the realization circuit of the method comprises a logic pulse generation circuit and a driving logic operation circuit, wherein the logic pulse generation circuit is composed of a sine modulation wave vrefAbsolute value arithmetic circuit Abs and main triangular carrier vcaA main triangular carrier vcbA main triangular carrier vccAuxiliary triangular carrier vcr1Auxiliary triangular carrier vcr2Auxiliary triangular carrier vcr3And seven comparators T1～T7Composition is carried out; the drive logic operation circuit consists of 20 NOT gates X1～X2019 double-input AND gates Y1～Y192 three-input AND gates Y20～Y215 double input OR gates Z1～Z5And 6 three-input OR gates Z6～Z11The components of the composition are as follows,
main triangular carrier vcaA main triangular carrier vcbAnd a main triangular carrier vccAre all at a frequency of fcThe peak value is 3E; auxiliary triangular carrier vcr1Auxiliary triangular carrier vcr2And secondary triangular carrier vcr3All have a frequency of 3fcThe peak value is E, wherein, the main triangular carrier vcaA main triangular carrier vcbAnd a main triangular carrier vccBoth between 0 and 3E; auxiliary triangular carrier vcr1Between 0 and E, secondary triangular carrier vcr2Between E and 2E, secondary triangular carrier vcr3Is between 2Between E and 3E, the main triangular carrier wave v is used as referencecaA main triangular carrier vcbAnd a main triangular carrier vccThe phase difference is 120 degrees; auxiliary triangular carrier vcr1The phase difference between the intersection point of the auxiliary triangular carrier and the zero reference line and the phase difference between the intersection points of the three main triangular carriers and the zero reference line are 60 degrees, and the phase difference between the auxiliary triangular carrier v and the zero reference line iscr3Phase of and auxiliary triangular carrier vcr1Are in the same phase, and auxiliary triangular carriers vcr2Phase of and auxiliary triangular carrier vcr1The phase difference of the three auxiliary triangular carriers is 60 degrees, namely the three auxiliary triangular carriers are arranged in an alternate reverse stacking manner,
sine modulation wave vrefThe output signal of the absolute value arithmetic circuit Abs is a modulated wave v connected with the input end of the absolute value arithmetic circuit AbsmV modulated wave vmRespectively connected to comparators T1～T3、T5～T7Of the positive phase input terminal of, the main triangular carrier vcaIs connected with a comparator T1Of the inverting input terminal, the main triangular carrier vcbIs connected with a comparator T2Of the inverting input terminal, the main triangular carrier vccIs connected with a comparator T3Of the inverted input terminal, auxiliary triangular carrier vcr1Is connected with a comparator T5Of the inverted input terminal, auxiliary triangular carrier vcr2Is connected with a comparator T6Of the inverted input terminal, auxiliary triangular carrier vcr3Is connected with a comparator T7Of the sine-modulated wave vrefIs connected with a comparator T4Of the positive phase input terminal, comparator T4The inverting input terminal of the voltage regulator is connected with a zero reference potential,
comparator T1The output end is connected with the NOT gate X1Post-sum comparator T4Output of (2) is connected with an OR gate Z1Two inputs of, or-gates Z1As the switching tube Q21Drive signal of, OR gate Z1The output end of the inverter is connected with a NOT gate X4The output signal is used as a switch tube Q22The drive signal of (1); comparator T1And comparator T4The output end of the voltage regulator is connected with an AND gate Y1Two input terminals of AND gate Y1As the switching tube Q24Of the driving signal AND-gate Y1The output end of the inverter is connected with a NOT gate X7The latter output letterHorn as switch tube Q23The drive signal of (1); comparator T2The output end is connected with the NOT gate X2Post-sum comparator T4Output of (2) is connected with an OR gate Z2Two inputs of, or-gates Z2As the switching tube Q31Drive signal of, OR gate Z2The output end of the inverter is connected with a NOT gate X5The output signal is used as a switch tube Q32The drive signal of (1); comparator T2And comparator T4The output end of the voltage regulator is connected with an AND gate Y2Two input terminals of AND gate Y2As the switching tube Q34Of the driving signal AND-gate Y2The output end of the inverter is connected with a NOT gate X8The output signal is used as a switch tube Q33The drive signal of (1); comparator T3The output end is connected with the NOT gate X3Post-sum comparator T4Output of (2) is connected with an OR gate Z3Two inputs of, or-gates Z3As the switching tube Q41Drive signal of, OR gate Z3The output end of the inverter is connected with a NOT gate X6The output signal is used as a switch tube Q42The drive signal of (1); comparator T3And comparator T4The output end of the voltage regulator is connected with an AND gate Y3Two input terminals of AND gate Y3As the switching tube Q44Of the driving signal AND-gate Y3The output end of the inverter is connected with a NOT gate X9The output signal is used as a switch tube Q43The drive signal of (1); comparator T1～T3、T5～T7The output end of the auxiliary signal operation module is connected with the auxiliary signal operation module, and the output of the auxiliary signal operation module is a signal L1And L2Signal L1NOT gate X11Comparator T4The output end of the inverter is connected with a NOT gate X10NOT gate X11And not gate X10The output end of the voltage regulator is connected with an AND gate Y4Two input terminals of signal L1And a comparator T4The output end of the voltage regulator is connected with an AND gate Y6Two input terminals of AND gate Y4And AND gate Y6Output of (2) is connected with an OR gate Z4Two inputs of, or-gates Z4As the switching tube Q11Drive signal of, OR gate Z4The output end of the inverter is connected with a NOT gate X13The output signal is used as a switch tube Q12The drive signal of (1); signal L2NOT gate X12Comparator T4The output end of the inverter is connected with a NOT gate X10NOT gate X12And not gate X10The output end of the voltage regulator is connected with an AND gate Y5Two input terminals of signal L2And a comparator T4The output end of the voltage regulator is connected with an AND gate Y7Two input terminals of AND gate Y5And AND gate Y7Output of (2) is connected with an OR gate Z5Two inputs of, or-gates Z5As the switching tube Q13Drive signal of, OR gate Z5The output end of the inverter is connected with a NOT gate X14The output signal is used as a switch tube Q14The drive signal of (a) is applied,
wherein, in the auxiliary signal operation module, the comparator T1The output end of the inverter is connected with a NOT gate X15Input terminal of, comparator T2The output end of the inverter is connected with a NOT gate X16Input terminal of, comparator T3The output end of the inverter is connected with a NOT gate X17Input terminal of, NOT-gate X15Output terminal of, not gate X16And not gate X17The output end of the voltage regulator is connected with an AND gate Y20Three input terminals of, not gate X15And not gate X16The output end of the voltage regulator is connected with an AND gate Y8Two input terminals of, NOT-gate X16And not gate X17The output end of the voltage regulator is connected with an AND gate Y9Two input terminals of, NOT-gate X17And not gate X15The output end of the voltage regulator is connected with an AND gate Y10Two input terminals of, NOT-gate X15Output terminal of, not gate X16And not gate X17Output of (2) is connected with an OR gate Z6And gate Y8Output terminal of and gate Y9And AND gate Y10Output of (2) is connected with an OR gate Z8And gate Y20And comparator T5The output end of the voltage regulator is connected with an AND gate Y14Two inputs of, or-gates Z8And comparator T6The output end of the voltage regulator is connected with an AND gate Y15Two inputs of, or-gates Z6Output end sum ratio ofComparator T7The output end of the voltage regulator is connected with an AND gate Y16Two input terminals of AND gate Y14Output terminal of and gate Y15And AND gate Y16Output of (2) is connected with an OR gate Z10Three inputs of, or-gates Z10Is the signal L1(ii) a Comparator T1Output terminal of (1), comparator T2And comparator T3The output end of the voltage regulator is connected with an AND gate Y21Three input terminals of, comparator T1And comparator T2The output end of the voltage regulator is connected with an AND gate Y11Two input terminals of, comparator T2And comparator T3The output end of the voltage regulator is connected with an AND gate Y12Two input terminals of, comparator T3And comparator T1The output end of the voltage regulator is connected with an AND gate Y13Two input terminals of, comparator T1Output terminal of (1), comparator T2And comparator T3Output of (2) is connected with an OR gate Z7And gate Y11Output terminal of and gate Y12And AND gate Y13Output of (2) is connected with an OR gate Z9Three input terminals of, comparator T7Is output through NOT gate X20Back and gate Y21The output end of the voltage regulator is connected with an AND gate Y17Two input terminals of, comparator T6Is output through NOT gate X19Rear OR gate Z9The output end of the voltage regulator is connected with an AND gate Y18Two input terminals of, comparator T5Is output through NOT gate X18Rear OR gate Z7The output end of the voltage regulator is connected with an AND gate Y19Two input terminals of AND gate Y17Output terminal of and gate Y18And AND gate Y19Output of (2) is connected with an OR gate Z11Three inputs of, or-gates Z11Is the signal L2。
2. The improved carrier phase shift modulation method of the hybrid cascaded H-bridge multilevel inverter according to claim 1, characterized in that: the improved carrier phase shift modulation method can be widely applied to a multi-level converter formed by cascading n H-bridge units, wherein the unit 1 is an auxiliary unitThe DC side is a capacitor, and the DC side voltage is only half of that of the rest units, i.e. Vdc10.5E; the other n-1 cascade units are main power units, the direct current sides are all voltage sources, and the voltages of the direct current sides are equal, namely Vdc2＝Vdc3＝…＝Vdcn＝E。
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