CN108281519B - light emitting diode epitaxial wafer and manufacturing method thereof - Google Patents
light emitting diode epitaxial wafer and manufacturing method thereof Download PDFInfo
- Publication number
- CN108281519B CN108281519B CN201810089267.0A CN201810089267A CN108281519B CN 108281519 B CN108281519 B CN 108281519B CN 201810089267 A CN201810089267 A CN 201810089267A CN 108281519 B CN108281519 B CN 108281519B
- Authority
- CN
- China
- Prior art keywords
- layer
- equal
- thickness
- quantum well
- electron blocking
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 230000000903 blocking effect Effects 0.000 claims abstract description 51
- 230000004888 barrier function Effects 0.000 claims abstract description 24
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 10
- 230000004913 activation Effects 0.000 abstract description 5
- 239000002131 composite material Substances 0.000 abstract 1
- 239000011777 magnesium Substances 0.000 description 24
- 239000013078 crystal Substances 0.000 description 6
- 229910052594 sapphire Inorganic materials 0.000 description 6
- 239000010980 sapphire Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 2
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 2
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010893 electron trap Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The epitaxial wafer comprises an electron blocking layer, the electron blocking layer is of a superlattice structure comprising N periods, the superlattice structure of each period comprises an In x Ga 1-x N layer and an Al y Ga 1-y N layer, the In x Ga 1-x N layer grows at 900-950 ℃, the lattice quality of a multi-quantum well layer and the composite light-emitting efficiency of electrons and holes In the multi-quantum well layer can be improved, meanwhile, the activation energy of Mg is reduced due to the existence of In, the hole concentration of a P layer is improved, the Al y Ga 1-y N layer grows at 950-980 ℃, the barrier height of the Al y Ga 1-y N layer is improved, the electrons are blocked from overflowing to the P layer, the content of Al is gradually reduced or gradually increased, the blocking effect on the holes is reduced, and the electrons are blocked from overflowing to the P layer, and the light-emitting efficiency of the diode is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a light-emitting diode epitaxial wafer and a manufacturing method thereof.
Background
An LED (Light Emitting Diode) is a semiconductor electronic component capable of Emitting Light. The GaN-based LED device is being widely used as a novel high-efficiency, environment-friendly and green solid-state lighting source, such as traffic signal lamps, outdoor full-color display screens, urban landscape lighting, automobile interior and exterior lamps, mobile phone backlight sources and the like.
The GaN-based LED epitaxial wafer is a main structure of a GaN-based LED device, and the structure of the GaN-based LED epitaxial wafer comprises: the GaN-based high-temperature light-emitting diode comprises a substrate, and a buffer layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer, a high-temperature P-type layer and a P-type contact layer which are arranged on the substrate in a laminated mode. The main reason for the low luminous efficiency of the GaN-based LED device is the low quantum efficiency in the GaN-based LED epitaxial wafer, and the main reasons for the low internal quantum efficiency include: the injection efficiency of the holes is low, and electrons overflowing from the multiple quantum well layer enter the P-type layer to be non-radiatively recombined with the holes. In order to solve the problem of low luminous efficiency of the LED device caused by non-radiative recombination of electrons overflowing from the multi-quantum well layer entering the P-type layer and holes, the GaN-based LED epitaxial wafer can further comprise an electron blocking layer arranged between the multi-quantum well layer and the P-type layer, and the electrons overflowing from the multi-quantum well layer are blocked from entering the P-type layer through the electron blocking layer.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
An electron blocking layer in a traditional GaN-based LED epitaxial wafer is an AlGaN layer which grows at a high temperature, the high Al content in the electron blocking layer can cause the quality difference of the grown epitaxial wafer crystal, and meanwhile, the high Al content can cause the high barrier height of the electron blocking layer, can block the injection of holes, and has a small effect of improving the internal quantum efficiency; and because the electron barrier layer is grown at the high temperature of 980 ℃, the high temperature can damage the crystal quality of the multiple quantum well layer, thereby influencing the performance of the LED epitaxial wafer.
Disclosure of Invention
in order to solve the problems that the internal quantum efficiency of an LED is low due to the fact that the content of Al in an electronic barrier layer is high and a multi-quantum well layer can be damaged due to the fact that the electronic barrier layer grows at a high temperature in the prior art, the embodiment of the invention provides an epitaxial wafer of a light emitting diode and a manufacturing method thereof. The technical scheme is as follows:
In one aspect, the invention provides a light emitting diode epitaxial wafer, which comprises a substrate, and a buffer layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer, an electron blocking layer, a high-temperature P-type layer and a P-type contact layer which are sequentially stacked on the substrate,
The electron blocking layer is of a superlattice structure comprising N periods, the superlattice structure of each period comprises an In x Ga 1-x N layer close to the multi-quantum well layer and an Al y Ga 1-y N layer far away from the multi-quantum well layer, x is more than or equal to 0.1 and less than or equal to 0.2, y is more than or equal to 0 and less than or equal to 0.2, the content of In the In x Ga 1-x N layer is less than that of In the multi-quantum well layer, the content of Al In the Al y Ga 1-y N layer is gradually reduced or gradually increased, the In x Ga 1-x N layer is grown at 900-950 ℃, the Al y Ga 1-y N layer is grown at 950-980 ℃, and N is more than or equal to 5 and less than or equal to 12;
The thickness of the electron blocking layer is 30-72 nm, the thickness of the In x Ga 1-x N layer is 2.5-3 nm, the thickness of the Al y Ga 1-y N layer is 2.5-3 nm, and the thickness of the In x Ga 1-x N layer is the same as that of the Al y Ga 1-y N layer.
Further, the In x Ga 1-x N layer was grown at 900 ℃ and the Al y Ga 1-y N layer was grown at 970 ℃.
furthermore, Mg is doped In both the In x Ga 1-x N layer and the Al y Ga 1-y N layer, and the doping concentration of Mg In both the In x Ga 1-x N layer and the Al y Ga 1-y N layer is 1 multiplied by 10 17 -1 multiplied by 10 18 cm -3.
in another aspect, the present invention provides a method for manufacturing an epitaxial wafer of a light emitting diode, the method comprising:
Providing a substrate;
Sequentially growing a buffer layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer, an electronic barrier layer, a high-temperature P-type layer and a P-type contact layer on the substrate;
wherein growing the electron blocking layer comprises: sequentially growing N periods of superlattice structures on the multi-quantum well layer, wherein N is more than or equal to 5 and less than or equal to 12; wherein the superlattice structure of each period grows in the following way:
Growing an In x Ga 1-x N layer under the condition that the growth temperature is 900-950 ℃, wherein x is more than or equal to 0.1 and less than or equal to 0.2, and the content of In the In x Ga 1-x N layer is less than that of In the multi-quantum well layer;
growing an Al y Ga 1-y N layer on the In x Ga 1-x N layer at the growth temperature of 950-980 ℃, wherein y is more than or equal to 0 and less than or equal to 0.2, and the content of Al In the Al y Ga 1-y N layer is gradually reduced or gradually increased;
The thickness of the electron blocking layer is 30-72 nm, the thickness of the In x Ga 1-x N layer is 2.5-3 nm, the thickness of the Al y Ga 1-y N layer is 2.5-3 nm, and the thickness of the In x Ga 1-x N layer is the same as that of the Al y Ga 1-y N layer.
Furthermore, the growth pressure of the In x Ga 1-x N layer and the growth pressure of the Al y Ga 1-y N layer are both 100-200 torr.
Further, the growth temperature of the In x Ga 1-x N layer is 900 ℃, and the growth temperature of the Al y Ga 1-y N layer is 970 ℃.
Further, the growing the electron blocking layer further includes:
and doping Mg during growing the In x Ga 1-x N layer and the Al y Ga 1-y N layer, wherein the doping concentration of the Mg In the In x Ga 1-x N layer and the Al y Ga 1-y N layer is 1 multiplied by 10 17 -1 multiplied by 10 18 cm -3.
the technical scheme provided by the embodiment of the invention has the following beneficial effects:
By providing electron blocking layers of a superlattice structure comprising N periods, the superlattice structure of each period comprising an In x Ga 1-x N layer close to the multiple quantum well layer and an Al y Ga 1-y N layer far from the multiple quantum well layer, 0.1 ≤ x ≤ 0.2, 0 ≤ y ≤ 0.2, wherein the In content In the In x Ga 1-x N layer is less than the In content In the multiple quantum well layer, ensuring that the barrier height In the In x Ga 5N layer is higher than the barrier height of the multiple quantum well layer 1-x 73 1-x to block the migration of electrons towards the high temperature P type layer, such that more electrons are accumulated In the multiple quantum well layer, the In x Ga 1-x N layer, such that the electron blocking layers can be lattice matched with the contact interface of the multiple quantum well layer, and at the same time the In can reduce the activation energy of Mg In the electron blocking layers, such that the activation of Mg is improved, such that the hole forbidden energy is increased, such that the hole forbidden energy is gradually reduced, the electron forbidden energy is gradually increased, the light emitting efficiency is increased when the well layer grows at a high well layer does not reach a high well temperature 1-y, the well layer x Ga 865-865 well layer, and the well layer growth temperature is increased, the well layer is increased, the well temperature is increased, the well layer is increased.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention;
Fig. 2 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Example one
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention, and as shown in fig. 1, the GaN-based led includes a substrate 1, and a buffer layer 2, an undoped GaN layer 3, an N-type layer 4, a multi-quantum well layer 5, an electron blocking layer 6, a high-temperature P-type layer 7, and a P-type contact layer 8, which are sequentially stacked on the substrate 1.
the electron blocking layer 6 is a superlattice structure comprising N periods, the superlattice structure of each period comprises an In x Ga 1-x N layer 61 close to the multi-quantum well layer and an Al y Ga 1-y N layer 62 far away from the multi-quantum well layer 5, x is more than or equal to 0.1 and less than or equal to 0.2, y is more than or equal to 0 and less than or equal to 0.2, the content of In the In x Ga 1-x N layer 61 is less than that of In the multi-quantum well layer 5, the content of Al In the Al y Ga 1-y N layer 62 is gradually reduced or gradually increased, the In x Ga 1-x N layer 61 is grown at 900-950 ℃, the Al y Ga 1-y N layer 62 is grown at 950-980 ℃, and N is more than or equal to 5 and less than or equal to 12.
The embodiment of the invention provides an electron barrier layer of a superlattice structure comprising N periods, wherein the superlattice structure of each period comprises an In x Ga 1-x N layer close to a multi-quantum well layer and an Al y Ga 1-y N layer far away from the multi-quantum well layer, x is more than or equal to 0.1 and less than or equal to 0.2, y is more than or equal to 0.1 and less than or equal to 0.2, wherein the content of In the In x Ga 1-x N layer is less than that of In the multi-quantum well layer, the barrier height In the In x Ga 1-x N layer is higher than that of the multi-quantum well layer, so that electrons are prevented from migrating to a high-temperature P type layer, more electrons are prevented from accumulating In the multi-quantum well layer, the content of Al In the In x Ga 1-x N layer is gradually reduced or gradually increased, the contact interface lattice of the electron barrier layer and the multi-quantum well layer is matched, the In x Ga 1-x N layer can be reduced, the activation energy of Mg In the electron barrier layer, the hole energy of the Mg is improved, the Mg activation capability of Mg is improved, the well layer is improved, the hole concentration of the Al y Ga 1-y N layer, the well layer is improved, the barrier layer grown at a higher temperature of the well layer grown by reducing or increasing the well layer grown In the well layer grown under x -well layer, the well layer grown at a higher electron barrier layer grown at a x temperature, the electron barrier layer grown at a x temperature, the electron trap temperature of the well layer grown at the x temperature of the well layer grown by the well layer grown at the x temperature, the x temperature of the x temperature, the well layer grown high-8427 temperature of the well layer grown high-P trap layer grown multi-P trap layer grown well layer grown multi-P well layer.
Preferably, x is 0.1, that is, the In content In the In x Ga 1-x N layer 61 is 0.1. if the In content is too high, the lattice quality of the grown electron blocking layer 6 is poor, and if the In content is too low, the lattice mismatch between the In x Ga 1-x N layer 61 and the multiple quantum well layer 5 is large.
Here, that the content of In the In x Ga 1-x N layer 61 is smaller than the content of In the multiple quantum well layer 6 means that the content of In the In x Ga 1-x N layer 61 is smaller than the average content of In the multiple quantum well layer 5.
Preferably, 7. ltoreq. N.ltoreq.12. If the value of N is greater than 12, the thickness of the electron blocking layer 6 is relatively thick, and the overall thickness of the epitaxial wafer is relatively large, so that the luminous efficiency of the LED is reduced, materials are wasted, and the growth time is increased. If the value of N is less than 7, the electron blocking layer 6 cannot play a role in blocking electrons from overflowing to the P-type layer.
further, the thickness of the electron blocking layer 6 is 30 to 72 nm. If the thickness of the electron blocking layer 6 is less than 30nm, the electron blocking layer 6 cannot play a role in blocking electrons from overflowing to the P-type layer, and if the thickness of the electron blocking layer 6 is greater than 72nm, the overall thickness of the epitaxial wafer is large, the luminous efficiency of the LED is reduced, materials are wasted, and the growth time is increased.
Further, the thickness of the In x Ga 1-x N layer 61 is 2-5 nm, and the thickness of the Al y Ga 1-y N layer 62 is 2-5 nm.
Alternatively, the thickness of the In x Ga 1-x N layer 61 is the same as the thickness of the Al y Ga 1-y N layer 62.
Preferably, the thickness of the electron blocking layer 6 is 50nm, wherein the thickness of the In x Ga 1-x N layer 61 is 5nm, the thickness of the Al y Ga 1-y N layer 62 is 5nm, and N is 5.
preferably, the In x Ga 1-x N layer 61 is grown at 900 ℃.
Preferably, the Al y Ga 1-y N layer 62 is grown at 970 ℃, if the growth temperature of the Al y Ga 1-y N layer 62 is higher than 970 ℃, the crystal quality of the grown electron blocking layer 6 is affected, if the growth temperature of the In x Ga 1-x N layer 61 is lower than 970 ℃, the doping of Al In the Al y Ga 1-y N layer 62 is not facilitated, the barrier of the Al y Ga 1-y N layer 62 is reduced, and the blocking effect of the Al y Ga 1-y N layer 62 on electrons is reduced.
Furthermore, Mg is doped In both the In x Ga 1-x N layer 61 and the Al y Ga 1-y N layer 62, and the doping concentration of Mg In the In x Ga 1-x N layer 61 and the Al y Ga 1-y N layer 62 is 1 multiplied by 10 17 to 1 multiplied by 10 18 cm -3.
Wherein, the doping concentrations of Mg In the In x Ga 1-x N layer 61 and the Al y Ga 1-y N layer 62 may be the same or different.
Optionally, the high-temperature P-type layer 7 is a Mg-doped GaN layer, the Mg doping concentration in the high-temperature P-type layer 7 is 1 × 10 19 -1 × 10 20 cm -3, and the thickness of the high-temperature P-type layer 7 is 20-30 nm.
Optionally, the buffer layer 2 is a GaN layer, and the thickness of the buffer layer is 20-30 nm.
optionally, the thickness of the undoped GaN layer 3 is 1-2 μm.
alternatively, the thickness of the N-type layer 4 is 1 to 5 μm, the N-type layer 4 is a GaN layer doped with Si, and the doping concentration of Si may be 1 × 10 18 to 1 × 10 19 cm -3.
Optionally, the multiple quantum well layer 5 is a superlattice structure including an InGaN well layer and a GaN barrier layer, and the number of cycles of the multiple quantum well layer 5 is 8-10. Wherein, the thickness of each InGaN potential well layer is 2-5 nm, and the thickness of each GaN barrier layer is 10-30 nm.
Optionally, the P-type contact layer 9 is a GaN layer doped with Mg, the doping concentration of Mg in the P-type contact layer 9 is 1 × 10 19 -1 × 10 20 cm -3, and the thickness of the P-type contact layer 9 is 5-300 nm.
Example two
An embodiment of the present invention provides a method for manufacturing an led epitaxial wafer, which is suitable for an led epitaxial wafer provided in the first embodiment of the present invention, and fig. 2 is a flowchart of a method for manufacturing an led epitaxial wafer provided in the first embodiment of the present invention, and as shown in fig. 2, the method includes:
Step 201, a substrate is provided.
specifically, the substrate is sapphire with a thickness of 630-650 μm.
In this example, a Veeco K465i or C4MOCVD (Metal Organic chemical vapor Deposition) apparatus was used to realize the growth method of the LED, high purity H 2 (hydrogen) or high purity N 2 (nitrogen) or a mixed gas of high purity H 2 and high purity N 2 was used as a carrier gas, high purity NH 3 was used as an N source, trimethylgallium (TMGa) and triethylgallium (TEGa) were used as gallium sources, trimethylindium (T min) was used as an indium source, silane (SiH4) was used as an N-type dopant, Trimethylaluminum (TMAL) was used as an aluminum source, and magnesium diclocene (CP 2 Mg) was used as a P-type dopant, the reaction chamber pressure was 100-600 torr.
Specifically, the step 201 includes:
and processing the sapphire substrate at a high temperature for 5-20 minutes in a hydrogen atmosphere. Wherein the temperature of the reaction chamber is 1000-1200 ℃, the pressure of the reaction chamber is controlled at 200-500torr, and the sapphire substrate is subjected to nitridation treatment.
Step 202, a buffer layer is grown on the substrate.
Specifically, after the sapphire substrate is subjected to high-temperature treatment, a GaN buffer layer grows on the sapphire substrate, the thickness of the GaN buffer layer is 20-30 nm, and the growth temperature can be 500-700 ℃.
further, after the GaN buffer layer is grown, the temperature of the reaction chamber is raised to 1000-1100 ℃, and the sapphire substrate plated with the buffer layer is annealed for 10-15 minutes.
Step 203, growing an undoped GaN layer on the buffer layer.
In the present embodiment, the thickness of the undoped GaN layer is 1 to 2 μm. When growing the undoped GaN layer, the temperature of the reaction chamber is 900-1200 ℃, and the pressure of the reaction chamber is controlled at 100-500 torr.
Step 204, an N-type layer is grown on the undoped GaN layer.
in the present embodiment, the N-type layer is a Si-doped GaN layer with a thickness of 1-5 μm, and the temperature of the reaction chamber is 900-1200 ℃ while the pressure of the reaction chamber is controlled at 100-500 torr during the growth of the N-type layer, wherein the doping concentration of Si is 1 × 10 18 -1 × 10 19 cm -3.
Step 205: and growing the multi-quantum well layer on the N-type layer.
The multi-quantum well layer is of a superlattice structure comprising an InGaN well layer and a GaN barrier layer, and the periodicity of the multi-quantum well layer is 8-10. Wherein the growth temperature of the InGaN well layer is 720-800 ℃, the growth pressure is 100-500 Torr, the thickness is 2-5 nm, the growth temperature of the GaN barrier layer is 850-950 ℃, the growth pressure is 100-500 Torr, and the thickness is 10-30 nm.
Step 206: and growing an electron barrier layer on the multi-quantum well layer.
Optionally, the electron blocking layer is a superlattice structure comprising N periods, the superlattice structure of each period comprises an In x Ga 1-x N layer close to the multiple quantum well layer and an Al y Ga 1-y N layer far away from the multiple quantum well layer, the In x Ga 1-x N layer is an In x Ga 1-x N layer, x is 0.1 or more and less than or equal to 0.2, y is 0 or more and less than or equal to 0.2, the In content In the In x Ga 1-x N layer is smaller than that In the multiple quantum well layer, the Al content In the Al y Ga 1-y N layer is gradually reduced or gradually increased, the growth temperature of the In x Ga 1-x N layer is 900-950 ℃, the growth temperature of the Al y Ga 1-y N layer is 950-980 ℃, and N is 5 or more and less than 12.
Preferably, x is 0.1, that is, the In content In the In x Ga 1-x N layer is 0.1. if the In content is too high, the lattice quality of the grown electron blocking layer is poor, and if the In content is too low, the lattice mismatch between the In x Ga 1-x N layer and the multiple quantum well layer is large.
Wherein the In content In the In x Ga 1-x N layer is less than the average In content In the multiple quantum well layer.
Preferably, 7. ltoreq. N.ltoreq.12. If the value of N is greater than 12, the thickness of the electron blocking layer is relatively thick, the overall thickness of the epitaxial wafer is relatively large, the light emitting efficiency of the LED is reduced, materials are wasted, and the growth time is increased. If the value of N is less than 7, the electron blocking layer cannot play a role in blocking electrons from overflowing to the P-type layer.
Further, the thickness of the electron blocking layer is 30-72 nm. If the thickness of the electron blocking layer is less than 30nm, the electron blocking layer cannot play a role in blocking electrons from overflowing to the P-type layer, and if the thickness of the electron blocking layer is greater than 72nm, the overall thickness of the epitaxial wafer is large, the luminous efficiency of the LED is reduced, materials are wasted, and the growth time is prolonged.
Furthermore, the thickness of the In x Ga 1-x N layer is 2-5 nm, and the thickness of the Al y Ga 1-y N layer is 2-5 nm.
Alternatively, the thickness of the In x Ga 1-x N layer is the same as the thickness of the Al y Ga 1-y N layer.
preferably, the thickness of the electron blocking layer is 50nm, wherein the thickness of the In x Ga 1-x N layer is 5nm, the thickness of the Al y Ga 1-y N layer is 5nm, and N is 5.
Preferably, the In x Ga 1-x N layer is grown at 900 ℃, the crystal quality of the multiple quantum well layer is destroyed if the growth temperature of the In x Ga 1-x N layer is higher than 900 ℃, and the crystal quality of the grown In x Ga 1- x N layer is poor if the growth temperature of the In x Ga 1-x N layer is lower than 900 ℃.
Preferably, the Al y Ga 1-y N layer grows at 970 ℃, if the growth temperature of the Al y Ga 1-y N layer is higher than 970 ℃, the crystal quality of the grown electron blocking layer is influenced, if the growth temperature of the In x Ga 1-x N layer is lower than 970 ℃, the doping of Al In the Al y Ga 1-y N layer is not facilitated, the barrier of the Al y Ga 1-y N layer is reduced, and the blocking effect of the Al y Ga 1-y N layer on electrons is reduced.
furthermore, the growth pressure of the In x Ga 1-x N layer and the growth pressure of the Al y Ga 1-y N layer are both 100-250 torr, wherein the growth pressure of the In x Ga 1-x N layer and the growth pressure of the Al y Ga 1-y N layer are equal, so that the growth pressure does not need to be switched In the growth process of the electron barrier layer, and the growth time is saved.
Further, step 206 further comprises:
Mg is doped when an In x Ga 1-x N layer and an Al y Ga 1-y N layer are grown, and the doping concentration of Mg In the In x Ga 1-x N layer and the Al y Ga 1-y N layer is 1 multiplied by 10 17 to 1 multiplied by 10 18 cm -3, so that the light-emitting efficiency of the recombination of electrons and holes is improved.
Step 207, a high temperature P-type layer is grown on the electron blocking layer.
Optionally, the high-temperature P-type layer is a GaN layer doped with Mg, the doping concentration of Mg in the high-temperature P-type layer is 1 × 10 19 -1 × 10 20 cm -3, the growth temperature is 900-1000 ℃, the growth pressure is 100-300Torr, and the thickness is 100-800 nm.
Step 208, a P-type contact layer is grown on the high temperature P-type layer.
Optionally, the P-type contact layer is a GaN layer doped with Mg, the doping concentration of Mg in the P-type contact layer is 1 × 10 19 -1 × 10 20 cm -3, the growth temperature is 850-1050 ℃, the growth pressure is 100-300Torr, and the thickness is 5-300 nm.
after the growth of the LED epitaxial wafer is finished, the temperature in the MOCVD equipment is reduced to 650-850 ℃, and the LED epitaxial wafer is annealed for 5-15 minutes in the nitrogen atmosphere. Then, the temperature was gradually decreased to room temperature.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent replacements, improvements, etc. within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A light-emitting diode epitaxial wafer comprises a substrate, and a buffer layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer, an electron blocking layer, a high-temperature P-type layer and a P-type contact layer which are sequentially stacked on the substrate,
The electron blocking layer is of a superlattice structure comprising N periods, the superlattice structure of each period comprises an In x Ga 1-x N layer close to the multi-quantum well layer and an Al y Ga 1-y N layer far away from the multi-quantum well layer, x is more than or equal to 0.1 and less than or equal to 0.2, y is more than or equal to 0 and less than or equal to 0.2, the content of In the In x Ga 1-x N layer is less than that of In the multi-quantum well layer, the content of Al In the Al y Ga 1-y N layer is gradually reduced or gradually increased, the In x Ga 1-x N layer is grown at 900-950 ℃, the Al y Ga 1-y N layer is grown at 950-980 ℃, and N is more than or equal to 5 and less than or equal to 12;
The thickness of the electron blocking layer is 30-72 nm, the thickness of the In x Ga 1-x N layer is 2.5-3 nm, the thickness of the Al y Ga 1-y N layer is 2.5-3 nm, and the thickness of the In x Ga 1-x N layer is the same as that of the Al y Ga 1-y N layer.
2. the light-emitting diode epitaxial wafer as claimed In claim 1, wherein the In x Ga 1-x N layer is grown at 900 ℃ and the Al y Ga 1-y N layer is grown at 970 ℃.
3. The light-emitting diode epitaxial wafer as claimed In claim 1, wherein Mg is doped In both the In x Ga 1-x N layer and the Al y Ga 1-y N layer, and the doping concentration of Mg In both the In x Ga 1-x N layer and the Al y Ga 1-y N layer is 1 × 10 17 -1 × 10 18 cm -3.
4. A manufacturing method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:
Providing a substrate;
Sequentially growing a buffer layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer, an electronic barrier layer, a high-temperature P-type layer and a P-type contact layer on the substrate;
Wherein growing the electron blocking layer comprises: sequentially growing N periods of superlattice structures on the multi-quantum well layer, wherein N is more than or equal to 5 and less than or equal to 12; wherein the superlattice structure of each period grows in the following way:
growing an In x Ga 1-x N layer under the condition that the growth temperature is 900-950 ℃, wherein x is more than or equal to 0.1 and less than or equal to 0.2, and the content of In the In x Ga 1-x N layer is less than that of In the multi-quantum well layer;
growing an Al y Ga 1-y N layer on the In x Ga 1-x N layer at the growth temperature of 950-980 ℃, wherein y is more than or equal to 0 and less than or equal to 0.2, and the content of Al In the Al y Ga 1-y N layer is gradually reduced or gradually increased;
The thickness of the electron blocking layer is 30-72 nm, the thickness of the In x Ga 1-x N layer is 2.5-3 nm, the thickness of the Al y Ga 1-y N layer is 2.5-3 nm, and the thickness of the In x Ga 1-x N layer is the same as that of the Al y Ga 1-y N layer.
5. The method of claim 4, wherein the growth pressure of the In x Ga 1-x N layer and the Al y Ga 1-y N layer is 100-250 torr.
6. The production method according to claim 4 or 5, wherein the growth temperature of the In x Ga 1-x N layer is 900 ℃ and the growth temperature of the Al y Ga 1-y N layer is 970 ℃.
7. The manufacturing method according to claim 4 or 5, wherein the growing the electron blocking layer further comprises:
And doping Mg during growing the In x Ga 1-x N layer and the Al y Ga 1-y N layer, wherein the doping concentration of the Mg In the In x Ga 1-x N layer and the Al y Ga 1-y N layer is 1 multiplied by 10 17 -1 multiplied by 10 18 cm -3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810089267.0A CN108281519B (en) | 2018-01-30 | 2018-01-30 | light emitting diode epitaxial wafer and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810089267.0A CN108281519B (en) | 2018-01-30 | 2018-01-30 | light emitting diode epitaxial wafer and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108281519A CN108281519A (en) | 2018-07-13 |
| CN108281519B true CN108281519B (en) | 2019-12-10 |
Family
ID=62805732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810089267.0A Active CN108281519B (en) | 2018-01-30 | 2018-01-30 | light emitting diode epitaxial wafer and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108281519B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110224047B (en) * | 2019-05-30 | 2022-08-12 | 西安电子科技大学 | Efficient light-emitting diode based on P-type doped AlScN/AlScN superlattice barrier layer and preparation method |
| CN111599902B (en) * | 2020-06-23 | 2022-02-11 | 东南大学 | Light-emitting diode with hole injection structure electron barrier layer |
| CN115663083B (en) * | 2021-12-30 | 2024-05-17 | 淮安澳洋顺昌光电技术有限公司 | Light-emitting diode and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103311394A (en) * | 2013-06-09 | 2013-09-18 | 东南大学 | GaN-based LED and epitaxial growth method thereof |
| CN105932130A (en) * | 2016-04-25 | 2016-09-07 | 东莞市中镓半导体科技有限公司 | A near-ultraviolet LED lamp with novel electron blocking layer, and preparation method thereof |
| CN106299038A (en) * | 2015-06-04 | 2017-01-04 | 东莞市中镓半导体科技有限公司 | A kind of method preparing the p-type AlGaN/AlInGaN electronic barrier layer near ultraviolet LED with doping content and Al component step variation |
-
2018
- 2018-01-30 CN CN201810089267.0A patent/CN108281519B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103311394A (en) * | 2013-06-09 | 2013-09-18 | 东南大学 | GaN-based LED and epitaxial growth method thereof |
| CN106299038A (en) * | 2015-06-04 | 2017-01-04 | 东莞市中镓半导体科技有限公司 | A kind of method preparing the p-type AlGaN/AlInGaN electronic barrier layer near ultraviolet LED with doping content and Al component step variation |
| CN105932130A (en) * | 2016-04-25 | 2016-09-07 | 东莞市中镓半导体科技有限公司 | A near-ultraviolet LED lamp with novel electron blocking layer, and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108281519A (en) | 2018-07-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108091740B (en) | Light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN109119515B (en) | Light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN110718612B (en) | Light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN108110098B (en) | Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN109950372B (en) | Light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN109216519B (en) | Light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN112366258B (en) | Ultraviolet light-emitting diode epitaxial wafer and manufacturing method thereof | |
| CN106611808B (en) | Growth method of light-emitting diode epitaxial wafer | |
| CN109545924B (en) | Light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN109346583B (en) | Light emitting diode epitaxial wafer and preparation method thereof | |
| CN107195739B (en) | Light emitting diode and manufacturing method thereof | |
| CN109524517B (en) | Light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN108831974B (en) | Light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN113206175B (en) | Light-emitting diode epitaxial wafer and preparation method thereof | |
| CN217641376U (en) | LED epitaxial wafer and LED chip | |
| CN112366256B (en) | Light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN109449264B (en) | Light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN108281519B (en) | light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN108550676B (en) | Light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN109301041B (en) | Light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN113161453B (en) | Light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN112259647B (en) | Preparation method of light-emitting diode epitaxial wafer and light-emitting diode epitaxial wafer | |
| CN110911529A (en) | Growth method of epitaxial structure of light-emitting diode | |
| CN110993753B (en) | Light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN109473520B (en) | Light emitting diode epitaxial wafer and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |