CN108281418A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN108281418A CN108281418A CN201710011951.2A CN201710011951A CN108281418A CN 108281418 A CN108281418 A CN 108281418A CN 201710011951 A CN201710011951 A CN 201710011951A CN 108281418 A CN108281418 A CN 108281418A
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- 238000002347 injection Methods 0.000 claims abstract description 67
- 239000007924 injection Substances 0.000 claims abstract description 67
- 230000008569 process Effects 0.000 claims abstract description 40
- 239000010410 layer Substances 0.000 claims description 301
- 239000000463 material Substances 0.000 claims description 93
- 150000002500 ions Chemical class 0.000 claims description 64
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 35
- 229920005591 polysilicon Polymers 0.000 claims description 31
- 238000000926 separation method Methods 0.000 claims description 30
- 238000000137 annealing Methods 0.000 claims description 28
- 238000002513 implantation Methods 0.000 claims description 16
- 230000005669 field effect Effects 0.000 claims description 13
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 8
- 239000002356 single layer Substances 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 6
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- 239000000243 solution Substances 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 22
- 229910052581 Si3N4 Inorganic materials 0.000 description 14
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 12
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- 239000002184 metal Substances 0.000 description 9
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 7
- 239000007789 gas Substances 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
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- 239000012212 insulator Substances 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
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- 229910003978 SiClx Inorganic materials 0.000 description 1
- RBFRSIRIVOFKDR-UHFFFAOYSA-N [C].[N].[O] Chemical compound [C].[N].[O] RBFRSIRIVOFKDR-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A kind of semiconductor structure and forming method thereof, forming method includes：Substrate is provided, the substrate includes the active region for being used to form active device and the passive area for being used to form passive device；Form the pseudo- grid structure being located on the active region substrate and the resistance elements on the passive area substrate；Source and drain doping area is formed on the substrate of dummy gate structure both sides；It is formed after source and drain doping area, forms dielectric layer on the substrate that dummy gate structure and the resistance elements are exposed, the dielectric layer exposes dummy gate structure and the resistance elements；Dummy gate structure is removed, gate openings are formed in the dielectric layer；High resistant injection is carried out to the resistance elements that the dielectric layer exposes, forms resistance；Gate structure is formed in the gate openings.Technical solution of the present invention can avoid the use of mask in high resistant injection process, to advantageously reduce process costs.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
The main semiconductor devices of integrated circuit especially super large-scale integration is Metal-oxide-semicondutor field effect
It should manage (MOS transistor).With the continuous development of production of integrated circuits technology, semiconductor device art node constantly reduces, and half
The geometric dimension of conductor device follows Moore's Law and constantly reduces.It is various when dimensions of semiconductor devices reduces to a certain extent
Because second-order effect occurs in succession caused by the physics limit of semiconductor devices, the characteristic size of semiconductor devices contracts in proportion
It is small to become more and more difficult.Wherein, in field of semiconductor manufacture, most challenging is how to solve semiconductor device creepage
Big problem.The leakage current of semiconductor devices is big, is mainly constantly reduced by traditional gate dielectric layer thickness caused.
The solution currently proposed is, using high-K gate dielectric material instead of traditional silicon dioxide gate dielectric material, and
Using metal as gate electrode, fermi level pinning effect occurs with conventional gate electrodes material to avoid hafnium and boron oozes
Penetration effect.The introducing of high-K metal gate reduces the leakage current of semiconductor devices.
On the other hand, in integrated circuits, polysilicon component (the non-silicide high of no silicide high value
Resistance ploy element) it is a kind of important passive device.High resistance polysilicon resistance has resistance value wide scope can
It adjusts, the advantages that area is small, linear properties are good.
But in the prior art, it forms the semiconductor structure with polysilicon resistance and high-K metal gate and often there is technique
The higher problem of cost.
Invention content
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, to reduce process costs.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：
Substrate is provided, the substrate includes being used to form the active region of active device and being used to form the passive of passive device
Area；Form the pseudo- grid structure being located on the active region substrate and the resistance elements on the passive area substrate；Institute
It states and forms source and drain doping area on the substrate of pseudo- grid structure both sides；It is formed after source and drain doping area, in dummy gate structure and described
Dielectric layer is formed on the substrate that resistance elements expose, the dielectric layer exposes dummy gate structure and the resistance elements；
Dummy gate structure is removed, gate openings are formed in the dielectric layer；The resistance elements that the dielectric layer exposes are carried out
High resistant injects, and forms resistance；Gate structure is formed in the gate openings.
Optionally, in the step of carrying out high resistant injection to the resistance elements that the dielectric layer exposes, technological parameter is：Note
It is B or BF to enter ion2, Implantation Energy is in 1KeV to 30KeV ranges, and implantation dosage is in 1.0E14atom/cm2It arrives
1.0E16atom/cm2；Alternatively, injection ion is As, in 5KeV to 50KeV ranges, implantation dosage exists Implantation Energy
1.0E14atom/cm2To 1.0E16atom/cm2.Optionally, in the step of forming the resistance elements, the resistance material
The material of layer is polysilicon or monocrystalline silicon；In the step of forming dummy gate structure, dummy gate structure is single layer structure, described
The material of pseudo- grid structure is polysilicon.Optionally, the step of high resistant injection being carried out to the resistance elements that the dielectric layer exposes
Including：After removing dummy gate structure, high resistant injection is carried out to the resistance elements that the dielectric layer exposes, forms resistance；
The forming method further includes：After removing dummy gate structure, high resistant is carried out to the resistance elements that the dielectric layer exposes
Before injection, filled layer is formed in the gate openings；It after carrying out high resistant injection, is formed before gate structure, removes institute
Filled layer is stated, the gate openings are exposed.Optionally, the material of the filled layer is organic matter.Optionally, the filled layer is
Bottom anti-reflection layer or organic dielectric layer.Optionally, the step of removing the filled layer include：It is gone by way of dry etching
Except the filled layer.Optionally, in the step of filled layer is removed by way of dry etching, technological parameter includes：Work(
Rate is in 1000W to 4700W ranges；Process gas includes：N2, flow is H in 500sccm to 4000sccm ranges2, flow is
In 200sccm to 1000sccm ranges；Process gas pressure is in 200mTorr to 2000mTorr ranges；Technological temperature is 200
DEG C within the scope of 300 DEG C.Optionally, the forming method further includes：After removing the filled layer, formed gate structure it
Before, the resistance and the source and drain doping area are made annealing treatment, to activate Doped ions.Optionally, to the resistance and
The step of source and drain doping area is made annealing treatment include：The annealing is carried out by way of spike annealing, is annealed
Temperature is within the scope of 950 DEG C to 1100 DEG C.Optionally, the step in source and drain doping area is formed on the substrate of dummy gate structure both sides
Suddenly include：Stressor layers are formed on the substrate of pseudo- grid structure both sides；Ion implanting is carried out to the stressor layers, forms the source and drain
Doped region.Optionally, in the step of providing substrate, the substrate of the active region includes the p type island region for being used to form p-type active device
With the N-type region for being used to form N-type active device；Include in the step of forming stressor layers on the substrate of pseudo- grid structure both sides：It is formed
The first stressor layers of pseudo- grid structure both sides on the substrate of p type island region；It is formed and is located at second of pseudo- grid structure both sides on N-type region substrate
Stressor layers；Carry out ion implanting the step of include：First ion implanting is carried out to first stressor layers, forms p type island region substrate
On source and drain doping area；Second ion implanting is carried out to second stressor layers, forms the source and drain doping area on N-type region substrate.
Optionally, the active region substrate is used to form fin formula field effect transistor；In the step of substrate is provided, the lining of the active region
There is fin on bottom, on the substrate that the fin exposes there is separation layer, the separation layer to cover the partial sidewall of the fin
Surface；In the step of forming dummy gate structure, dummy gate structure is located on the fin, across the fin and covering institute
State the surface of fin atop part and partial sidewall；In the step of forming resistance elements, the resistance elements are located at passive
On the separation layer in area；Formed source and drain doping area the step of include：The source and drain is formed in the fin of dummy gate structure both sides
Doped region；In the step of forming gate openings, the fin atop part and partial sidewall are exposed in the gate openings bottom
Surface.
Correspondingly, the present invention also provides a kind of semiconductor structures, including：
Substrate, the substrate include the active region for being used to form active device and the passive area for being used to form passive device；
Gate structure on the active region substrate；Source and drain doping area on the substrate of the gate structure both sides；Positioned at institute
State the resistance elements on the substrate of passive area；Expose the medium on substrate positioned at the gate structure and the resistance elements
Layer.
Optionally, the resistance elements are polysilicon layer；The gate structure is pseudo- grid structure, dummy gate structure
Material is polysilicon.Optionally, the source and drain doping area includes the stressor layers being located on the substrate of the gate structure both sides, described
There are Doped ions in stressor layers.Optionally, the substrate of the active region include be used to form p-type active device p type island region and
It is used to form the N-type region of N-type active device；The stressor layers include：The first of gate structure both sides answers on the substrate of p type island region
Power layer and on N-type region substrate gate structure both sides the second stressor layers, have in first stressor layers p-type adulterate from
Son, second stressor layers are interior to have n-type doping ion.Optionally, the dielectric layer exposes the gate structure and the electricity
Hinder material layer.
Compared with prior art, technical scheme of the present invention has the following advantages：
In technical solution of the present invention, source and drain doping area is formed before forming the dielectric layer；Forming the dielectric layer
High resistant injection is carried out to the resistance elements later.Dielectric layer progress later, institute are formed since the high resistant is infused in
Semiconductor structure on active region substrate can be protected in high resistant injection process by stating dielectric layer, reduced active region substrate upper half and led
Body structure is influenced by high resistant injection, the use of mask can be avoided in high resistant injection process, to advantageously reduce work
Skill cost.
In alternative of the present invention, after removing dummy gate structure, before carrying out high resistant injection, opened in the grid
Filled layer is formed by organic matter in mouthful；The filled layer can protect the gate openings to expose in high resistant injection process
Semiconductor structure is conducive to improve so as to reduce influence of the high resistant injection to active region substrate upper semiconductor structure
The performance of formed semiconductor structure；And the material of the filled layer is organic matter, therefore removed by wet etching mode
During the filled layer, technology difficulty is smaller, filled layer residual is less, advantageously reduces to form the semiconductor structure
Technology difficulty and the performance for improving the semiconductor structure.
In alternative of the present invention, before removing the filled layer, the resistance and the source and drain doping area are carried out
Annealing is to activate Doped ions.The annealing had both been used to activate the Doped ions injected in the resistance, was additionally operable to
The Doped ions in the source and drain doping area, this way are activated to advantageously reduce the heat budget to form the semiconductor structure,
Be conducive to improve the performance of formed semiconductor structure.
Description of the drawings
Fig. 1 to Fig. 3 is a kind of corresponding cross-sectional view of each step of method for forming semiconductor structure；
Fig. 4 to Figure 11 is the corresponding cross-section structure signal of each step of one embodiment of method for forming semiconductor structure of the present invention
Figure.
Specific implementation mode
By background technology it is found that in the prior art, it is past to form the semiconductor structure with polysilicon resistance and high-K metal gate
Toward there are the higher problems of process costs.The high problem of its process costs is analyzed in conjunction with a kind of forming method of semiconductor structure
Reason：
Referring to figs. 1 to Fig. 3, a kind of corresponding cross-section structure signal of each step of method for forming semiconductor structure is shown
Figure.
With reference to figure 1, substrate 10 is provided, the substrate 10 includes being used to form the active region 10a of active device and for shape
At the passive area 10b of passive device, there is fin 11 on the substrate 10 of the active region 10a；It is formed and is located on the fin 11
Pseudo- grid structure 12 and the polysilicon layer 13 on the passive area 10b substrates 10, dummy gate structure 12 is across the fin
Portion 11 and the surface of covering fin 11 atop part and partial sidewall；It is formed in the fin of 12 both sides of dummy gate structure
Stressor layers 14.
With reference to figure 2, source and drain injection 15 is carried out to the stressor layers 14, forms source and drain doping area；To the polysilicon layer 13
High resistant injection 16 is carried out, high resistance polysilicon 17 is formed；Later, with reference to figure 3, dummy gate structure 12 is removed, forms gate openings
(not indicated in figure)；Metal gate structure (not indicated in figure) is formed in the gate openings.
Since source and drain injection 15 is different with the injection technology of high resistant injection 16, in the process for carrying out source and drain injection 15
In, it needs to protect polysilicon layer 13 using the first mask 21, avoids the polysilicon layer 13 by the pollution of source and drain injection 15；
During carrying out high resistant injection 16, need, using the semiconductor structure on the second mask 22 protection active region 10a substrates 10, to keep away
Exempt from pollution of the semiconductor structure on active region 10a substrates 10 by high resistant injection 16.And hereafter, as shown in figure 3, removing
During dummy gate structure forms metal gate structure, need to protect the high resistance polysilicon 17 using third mask 23.
So during forming the high resistance polysilicon 17 and metal gate structure, need to use 3 masks.Mask
Be used for multiple times, increase the process costs to form the semiconductor structure.
To solve the technical problem, the present invention provides a kind of forming method of semiconductor structure, including：
Substrate is provided, the substrate includes being used to form the active region of active device and being used to form the passive of passive device
Area；Form the pseudo- grid structure being located on the active region substrate and the resistance elements on the passive area substrate；Institute
It states and forms source and drain doping area on the substrate of pseudo- grid structure both sides；It is formed after source and drain doping area, in dummy gate structure and described
Dielectric layer is formed on the substrate that resistance elements expose, the dielectric layer exposes dummy gate structure and the resistance elements；
Dummy gate structure is removed, gate openings are formed in the dielectric layer；The resistance elements that the dielectric layer exposes are carried out
High resistant injects, and forms resistance；Gate structure is formed in the gate openings.
In technical solution of the present invention, source and drain doping area is formed before forming the dielectric layer；Forming the dielectric layer
High resistant injection is carried out to the resistance elements later.Dielectric layer progress later, institute are formed since the high resistant is infused in
Semiconductor structure on active region substrate can be protected in high resistant injection process by stating dielectric layer, reduced active region substrate upper half and led
Body structure is influenced by high resistant injection, the use of mask can be avoided in high resistant injection process, to advantageously reduce work
Skill cost.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
With reference to figure 4 to Figure 11, shows that each step of one embodiment of method for forming semiconductor structure of the present invention is corresponding and cut open
Face structural schematic diagram.
With reference to figure 4, substrate 100 is provided, the substrate 100 includes being used to form the active region 100a of active device and being used for
Form the passive area 100b of passive device.
The substrate 100 is for providing technological operation platform.
Active device (active device), also referred to as active device, impose extraneous letter in analogy and digital circuit
Hao ﹐ can change the device of oneself fundamental characteristics itself.Active device be able to carry out data operation, processing element.Including each
The chip of formula various kinds, such as active crystal, integrated circuit, camera tube and display etc. in semiconductor element belong to active element
Part.
In the present embodiment, the substrate 100 of the active region 100a is used to form complementary mos device, i.e.,
Cmos device.The substrate 100 of the active region 100a includes being used to form the p type island region 100p of p-type active device and being used to form N
The N-type region of type active device.But in other embodiments of the invention, the active region substrate can also be only for forming p-type device
The substrate of part, i.e., the described active region only has p type island region；Alternatively, the active region substrate can also be only for forming N-type device,
The i.e. described active region substrate only has N-type region.
Passive device (passive device), also referred to as passive device, do not need the source of energy and realize its spy
The device of fixed function.From character of circuit, passive device itself does not consume electric energy, or electric energy is changed into various forms of
Other energy；And passive device only needs input signal, and not needing additional power source can work normally.So passive device is not
Influence signal essential characteristic, and only enable signal by by the circuit element that is not changed.Most common passive device have resistance,
Capacitance, inductance, Tao Zhen, crystal oscillator, transformer etc..
In the present embodiment, the substrate 100 of the passive area 100b is used to form resistance.Specifically, the passive area 100b
Substrate 100 is used to form polysilicon component (the non-silicide high resistance ploy of no silicide high value
Element), i.e. high resistance polysilicon resistance.
It should be noted that in the present embodiment, the active region 100a is disposed adjacent with the passive area 100b.The present invention
In other embodiment, the active region 100a can not also be disposed adjacent with the passive area 100b.Similar, active region 100a
The interior p type island region 100p and the N-type region 100n are disposed adjacent；In other embodiments of the invention, in active region the p type island region and
The N-type region can not also be disposed adjacent.
In the present embodiment, the material of the substrate 100 is monocrystalline silicon.In other embodiments of the invention, the substrate may be used also
Be multicrystalline silicon substrate, amorphous silicon substrate or germanium silicon substrate, carbon silicon substrate, silicon-on-insulator substrate, germanium substrate on insulator,
Glass substrate or III-V compound substrate, such as gallium nitride substrate or gallium arsenide substrate etc..The material of the substrate can
To choose the material for being suitable for process requirements or being easily integrated.
It should be noted that in the present embodiment, the active region 100a substrates 100 are used for fin formula field effect transistor, institute
As shown in figure 4, having fin 101 on the substrate 100 of the active region 100a, to have on the substrate 100 that the fin 101 exposes
There are separation layer 102, the separation layer 102 to cover the partial sidewall surface of the fin 101.
The fin 101 is used to provide the raceway groove of the fin formula field effect transistor.
In the present embodiment, the material identical of the material of the fin 101 and the substrate 100 is all monocrystalline silicon.The present invention
In other embodiment, the material of the fin can also be different from the material of the substrate, can be selected from germanium, germanium silicon, carbon silicon or
GaAs etc. is suitable for forming the material of fin.
Specifically, the substrate 100 and the fin 101 can be formed simultaneously.Form the substrate 100 and the fin
101 the step of includes：Initial substrate is provided；The first mask layer (not shown) is formed in the initial substrate surface；With institute
It is initial substrate described in mask etching to state the first mask layer, forms the substrate 100 and the fin on the substrate 100
101。
First mask layer is used to define size and the position of the fin 101.
The step of forming first mask layer include：Mask layer is formed in the initial substrate；It is covered described
Graph layer is formed in membrane layers；Using the graph layer as mask, the mask layer is etched, exposes the initial substrate,
To form first mask layer.
The graph layer is for being patterned the mask layer, to define size and the position of the fin.
In the present embodiment, the graph layer is patterned photoresist layer, can pass through coating process and photoetching process shape
At.In other embodiments of the invention, the graph layer can also be that multiple graphical masking process is formed by mask, to reduce
The distance between the characteristic size of fin and adjacent fin improve the integrated level of formed semiconductor structure.Wherein multigraph
Shape masking process includes：Self-alignment duplex pattern (Self-aligned Double Patterned, SaDP) technique, from
It is directed at triple graphical (Self-aligned Triple Patterned) techniques or the graphical (Self- of autoregistration quadruple
Aligned Double Double Patterned, SaDDP) technique.
It should be noted that in the present embodiment, is formed after the substrate 100 and the fin 101, retain the fin
First mask layer at 101 tops.The material of first mask layer is silicon nitride, for defining flat chemical industry in the subsequent process
The stop-layer position of skill, and play the role of protecting fin 101.
The separation layer 102 is for realizing the electric isolution between adjacent fin 101 and between adjacent semiconductor constructs.Tool
Body, in the present embodiment, in active region 100a, separation layer 102 is between adjacent fin 101, for realizing adjacent fin 101
Between electric isolution；In passive area 100b, separation layer 102 is located on substrate 100, for realizing the substrate 100 with formed
Electric isolution between passive device.
In the present embodiment, the material of the separation layer 102 is silica.In other embodiments of the invention, the separation layer
Material can also be the materials such as silicon nitride or silicon oxynitride.
The step of forming the separation layer 102 include：By chemical vapor deposition (such as：Fluid chemistry is vapor-deposited) etc.
Method is not being formed spacer material layer, the spacer material layer covering described first on substrate 100 that the fin 101 covers
Mask layer；The spacer material layer higher than first mask layer is removed by modes such as chemical mechanical grindings；By going back to the side carved
The segment thickness of the remaining spacer material layer of formula removal is to form separation layer.
It should be noted that being formed after the separation layer 102, the forming method further includes：Described first is removed to cover
Film layer, to expose the top surface of the fin 101, for providing Process ba- sis for subsequent technique.
With continued reference to Fig. 4, forms the pseudo- grid structure 120 being located on the active region 100a substrates 100 and be located at the quilt
Resistance elements 130 on dynamic area's 100b substrates 100.
Dummy gate structure 120 is used to take up space to be subsequently formed by gate structure；The resistance elements 130 are used
In formation resistance.Specifically, the active region 100a substrates 100 are used to form fin formula field effect transistor, on the substrate 100
With fin 101, so in the step of forming dummy gate structure 120, dummy gate structure 120 is located at 101 on the fin,
Across the surface of the fin 101 and covering fin 101 atop part and partial sidewall.
Dummy gate structure 120 is single layer structure, includes the dummy grid of polycrystalline silicon material.In other embodiments of the invention,
The material of the dummy grid can also be silica, silicon nitride, silicon oxynitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride or non-
The other materials such as brilliant carbon.In other of the invention embodiments, dummy gate structure can also be laminated construction, including dummy grid with
And the pseudo- oxide layer on the dummy grid, the material of the puppet oxide layer can be silica and silicon oxynitride.
In the present embodiment, the passive area 100b substrates 100 are used to form high resistance polysilicon resistance.So forming the electricity
In the step of hindering material layer 130, the material of the resistance elements 130 is polysilicon.In other embodiments of the invention, the electricity
The material for hindering material layer 130 can also be monocrystalline silicon.
In addition, also there is separation layer 102, so forming the step of resistance elements 130 on the passive area 100b substrates 100
In rapid, the resistance elements 130 are located on the separation layer 102 of passive area 100b.
It is all polysilicon due to the material identical of the material and the resistance elements 130 of dummy gate structure 120, institute
It can be formed by same technical process with dummy gate structure 120 and the resistance elements 130.
Specifically, the step of forming dummy gate structure 120 and the resistance elements 130 includes：In the substrate 100
The pseudo- gate material layer of upper formation；The second mask layer (not indicated in figure) is formed in the pseudo- gate material layer；With second mask
Layer is mask, etches the pseudo- gate material layer, forms dummy gate structure 120 and the resistance elements 130.
The puppet gate material layer is used to form dummy gate structure 120 and the resistance elements 130.Specifically, described
Pseudo- gate material layer is polysilicon layer.
Second mask layer is used to define size and the position of dummy gate structure 120 and the resistance elements 130.
In addition, in the present embodiment, second mask layer is additionally operable to play the role of etching stopping in the subsequent process, for protecting
State resistance elements 130.Specifically, the material of second mask layer is silicon nitride.
It should be noted that after forming dummy gate structure 120 and the resistance elements 130, also in the pseudo- grid knot
Side wall (not indicated in figure) is formed on the side wall of structure 120.The material of the side wall can be silica, silicon nitride, silicon carbide, carbon
Silicon nitride, carbon silicon oxynitride, silicon oxynitride, boron nitride or boron carbonitrides, the side wall can be single layer structure or laminated construction.
In the present embodiment, the side wall is single layer structure, and the material of the side wall is silicon nitride.
In conjunction with reference to figure 4 and Fig. 5, source and drain doping area is formed on the substrate 100 of 120 both sides of dummy gate structure.
The source and drain doping area 103 is used to form source region or the drain region of active device.
Specifically, the active region 100a substrates 100 are used to form fin formula field effect transistor, have on the substrate 100
There is fin 101, so the step of forming source and drain doping area includes：Institute is formed in the fin 101 of 120 both sides of dummy gate structure
State source and drain doping area.
Specifically, including the step of forming source and drain doping area on the substrate 100 of 120 both sides of dummy gate structure：Such as Fig. 4
It is shown, form stressor layers on the substrate 100 of 120 both sides of pseudo- grid structure；As shown in figure 5, carrying out ion note to the stressor layers
Enter, forms the source and drain doping area.
In the present embodiment, the substrate 100 of the active region 100a includes p type island region 100p and N-type region 100n.So in puppet
The step of formation stressor layers, includes on the substrate 100 of 120 both sides of grid structure：It is formed and is located at pseudo- grid knot on p type island region 100p substrates 100
First stressor layers 140p of 120 both sides of structure；Form the second stress for being located at 120 both sides of pseudo- grid structure on N-type region 100n substrates 100
Layer 140n.
The first stressor layers 140p is used to form the source and drain doping area of p-type active device, is used for p-type active device
Channel region applies compression.So in the present embodiment, the first stressor layers 140p is " ∑ " shape stressor layers of germanium silicon material.
The second stressor layers 140n is used to form the source and drain doping area of N-type active device, is used for N-type active device
Channel region applies tensile stress.So in the present embodiment, the second stressor layers 140n is " side " shape stressor layers of carbon silicon materials.
In the present embodiment, the active region 100a substrates 100 are used to form fin formula field effect transistor, so described in being formed
The step of first stressor layers 140p includes：It is formed on the N-type region 100n substrates 100 and the passive area 100b substrates 100
First cap layers, first cap layers expose the semiconductor structure on the p type island region 100p substrates 100；Remove the p type island region substrate
The some materials of 120 both sides fin 101 of pseudo- grid structure on 100, form " ∑ " shape opening in the fin 101；To described
Germanium silicon material is filled by way of epitaxial growth in " ∑ " shape opening, to form the first stressor layers 140p.
The step of forming the second stressor layers 140n include：In the p type island region 100p substrates 100 and the passive area
The second cap layers are formed on 100b substrates 100, second cap layers expose the semiconductor structure on the N-type region 100n substrates 100；
Remove some materials of 120 both sides fin 101 of pseudo- grid structure on the N-type region 100n substrates 100, the shape in the fin 101
It is open at " u "-shaped；Carbon silicon materials are filled by way of epitaxial growth into " u "-shaped opening, are answered with forming described second
Power layer 140n.
It should be noted that first cap layers and second cap layers are respectively used to define the first stressor layers 140p and the
The size of two stressor layers 140n and position.First cap layers and second cap layers are respectively positioned on the resistance of the passive area 100b
130 surface of material layer, during avoiding epitaxial growth Ge silicon materials or epitaxial growth carbon silicon materials, germanium silicon material or
Influence of the carbon silicon materials to resistance elements 130 on passive area 100b substrates 100.Positioned at 130 surface of the resistance elements
First cap layers and the second cap layers are used to form protective film (not indicated in figure), and the resistance elements are protected in technical process
130。
As shown in figure 5, the step of carrying out ion implanting includes：First ion implanting is carried out to the first stressor layers 140p
141p forms the source and drain doping area on p type island region 100p substrates 100；Second ion implanting is carried out to the second stressor layers 140n
141n forms the source and drain doping area on N-type region 100n substrates 100.
The first ion implanting 141p is used to inject Doped ions to the first stressor layers 140p, to form p-type actuator
The source and drain doping area of part.So the step of carrying out the first ion implanting 141p to the first stressor layers 140p includes：In the N
The first photoresist layer is formed on type area 100n substrates 100 and passive area 100b substrates 100, described in first photoresist layer exposes
First stressor layers 140p；Using first photoresist layer as mask, the first ion implanting 141p is carried out.
In the present embodiment, the technological parameter of the first ion implanting 141p includes：Injection ion is B, and Implantation Energy exists
In 1KeV to 5KeV ranges, implantation dosage is in 1.0E15atom/cm2To 4.0E15atom/cm2In range.
The second ion implanting 141n is used to inject Doped ions to the second stressor layers 140n, to form N-type actuator
The source and drain doping area of part.So the step of carrying out the second ion implanting 141n to the second stressor layers 140n includes：In the P
The second photoresist layer is formed on type area 100p substrates 100 and passive area 100b substrates 100, described in second photoresist layer exposes
Second stressor layers 140n；Using second photoresist layer as mask, the second ion implanting 141n is carried out.
In the present embodiment, the technological parameter of the second ion implanting 141n includes：Injection ion is As, and Implantation Energy exists
In 2KeV to 10KeV ranges, implantation dosage is in 1.0E15atom/cm2To 4.0E15atom/cm2In range.
In the step of carrying out the first ion implanting 141p and during carrying out the second ion implanting 141n,
The passive area 100b substrates 100 have been respectively formed on photoresist layer.The photoresist layer can effectively prevent source and drain doping area
Resistance elements 130 on the ionic soil passive area 100b substrates 100 of interior injection.
It with reference to figure 6, is formed after source and drain doping area, is exposed in dummy gate structure 120 and the resistance elements 130
Dielectric layer 170 is formed on substrate 100, the dielectric layer 170 exposes dummy gate structure 120 and the resistance elements 130.
The dielectric layer 170 is interlayer dielectric layer, for realizing the electric isolution between semiconductor structure, after being also used for definition
Continue size and the position of formed gate structure.In the present embodiment, the material of the dielectric layer 170 is silica.The present invention its
In his embodiment, the material of the dielectric layer is also selected from other medium materials such as silicon nitride, silicon oxynitride or carbon silicon oxynitride
Material.
Specifically, having fin 101 and separation layer 102 on the substrate 100.So the dielectric layer 170 is positioned at described
On substrate 100, the fin 101 and the separation layer 102.The dielectric layer 170 exposes dummy gate structure 120 and described
Resistance elements 130, the formation for formation and resistance for subsequent gate structure provide Process ba- sis.
The step of forming the dielectric layer 170 include：By chemical vapor deposition (such as：Fluid chemistry is vapor-deposited) etc.
Method forms layer of dielectric material on the substrate 100 that dummy gate structure 120 and the resistance elements 130 are exposed, and is given an account of
The material bed of material covers dummy gate structure 120 and the resistance elements 130；It is removed and is higher than by modes such as chemical mechanical grindings
The layer of dielectric material of dummy gate structure 120 and the resistance elements 130 exposes dummy gate structure 120 and the resistance
Material layer 130 forms the dielectric layer 170.
It should be noted that being removed higher than dummy gate structure 120 and the resistance by modes such as chemical mechanical grindings
During the layer of dielectric material of material layer 130, using second mask layer as etching stop layer；And it is higher than the puppet in removal
During grid structure 120 and the layer of dielectric material of the resistance elements 130, second mask layer is removed.
With reference to figure 7 to Fig. 9, as shown in fig. 7, dummy gate structure 120 (as shown in Figure 6) is removed, in the dielectric layer 170
Interior formation gate openings 150；As shown in figure 9, carrying out high resistant injection to the resistance elements 130 that the dielectric layer 170 exposes
161, form resistance 160.
Since high resistant injection 161 carries out after forming the dielectric layer 170, the dielectric layer 170 can be in height
Semiconductor structure during resistance injection 161 on protection active region 100a substrates 100 reduces 100 upper half of active region 100a substrates
Conductor structure is influenced by high resistant injection 161, the use of mask can be avoided during high resistant injects 160, to advantageous
In reduction process costs.
As shown in fig. 7, the gate openings 150 are used to provide state space for the formation of gate structure.
In the present embodiment, the active region 100a substrates 100 are used to form fin formula field effect transistor, so forming grid
Be open 150 the step of in, the surface of the fin 101 atop part and partial sidewall is exposed in 150 bottom of the gate openings.Tool
Body, the step of forming the gate openings 150 includes：Dummy gate structure 120 is removed, 101 part of fin top is exposed
The surface in portion and partial sidewall forms the gate openings 150.
Since the material of the resistance elements 130 and the material of dummy gate structure 120 are all polysilicon.So removal
The step of dummy gate structure 120 includes：Protection photoresist layer, the protection photoetching are formed on passive area 100b substrates 100
Glue-line exposes dummy gate structure 120；Dummy gate structure 120 is removed by way of dry etching.
Specifically, in the step of removal dummy gate structure 120, process gas includes：HBr, flow are arrived in 150sccm
Within the scope of 1000sccm, He, flow is in 100sccm to 800sccm ranges；Process gas pressure is in 3mTorr to 100mTorr
In range；Pole plate power is in 200W to 1000W ranges, and radio-frequency power is in 10W to 200W ranges；Technological temperature is arrived at 50 DEG C
Within the scope of 100 DEG C.
As shown in figure 9, the high resistant injection 161 is used to inject Doped ions into the resistance elements 130, for adjusting
The resistance value for saving the resistance elements 130, to form resistance 160.
Specifically, injecting the difference of 161 injected ionic types according to high resistant, the resistance 160 can be the electricity of p-type
Resistance, can also be the resistance of N-type.So in the present embodiment, the step of high resistant injection 161 in, when the resistance 160 is P
When type resistance, the technological parameter of the high resistant injection 161 is：Injection ion is B or BF2, Implantation Energy is in 1KeV to 30KeV models
In enclosing, implantation dosage is in 1.0E14atom/cm2To 1.0E16atom/cm2；When the resistance 160 is N-type resistance, the height
Resistance injection 161 technological parameter be：Injection ion is As, and in 5KeV to 50KeV ranges, implantation dosage exists Implantation Energy
1.0E14atom/cm2To 1.0E16atom/cm2。
It should be noted that the injection ion pair puppet grid structure 120 for injecting 161 (as shown in Figure 9) in order to reduce high resistant is gone
The influence removed, reduces the technology difficulty that pseudo- grid structure 120 removes, and the resistance elements 130 exposed to the dielectric layer 170 carry out
High resistant injection 161 (as shown in Figure 9) the step of include：After removing dummy gate structure 120 (as shown in Figure 6), to being given an account of
The resistance elements 130 that matter layer 170 exposes carry out high resistant injection, form resistance 160.
After removal dummy gate structure 120, it is formed by 150 bottom of gate openings and exposes the active device
Channel region.So in order to avoid the channel region that high resistant injection 161 influences active device, the forming method is also wrapped
It includes：As shown in figure 8, after removal dummy gate structure 120, the resistance elements 130 exposed to the dielectric layer 170 carry out height
Before resistance injection 161, filled layer 151 is formed in the gate openings 150.
The filled layer 151 is used to protect the channel region of the active device during high resistant injection 161, reduces
High resistant injects the influence of 161 pairs of active device channel regions.
In the present embodiment, the material of the filled layer 151 is organic matter.The material of the filled layer 151 is provided with
The way of machine object can effectively improve the blocking capability that filled layer 151 injects high resistant injection 161 in ion, can be effective
The influence that high resistant injects 161 pairs of active device channel regions is reduced, the performance for improving formed active device is conducive to；And have
The filled layer 151 of machine object material can remove subsequently through the mode of wet etching, can reduce and subsequently remove the filled layer
151 technology difficulty reduces the remnants of the filled layer 151, advantageously reduces the formation difficulty of the gate structure, is conducive to
Improve the performance of formed gate structure.Specifically, the filled layer 151 can be bottom anti-reflection layer (Bottom Anti-
Reflect Coating, BARC) or organic dielectric layer (Organic Dielectric Layer, ODL).
Specifically, the step of forming the filled layer 151 includes：The filling filling layer material into the gate openings 150,
It fills layer material and covers the dielectric layer 170；The filling layer material on the dielectric layer 170 is removed, is formed and is located at the grid
The filled layer 151 of (as shown in Figure 7) in opening 150.
With reference to figure 10 and Figure 11, gate structure 180 (as shown in figure 11) is formed in the gate openings 150.
The gate structure 180 is used to control the conducting of formed active device raceway groove and block.It is described in the present embodiment
Gate structure 180 is metal gate structure, including：Grid oxide layer, work-function layer and metal gate.Form the gate structure 180
Technical solution it is same as the prior art, the present invention details are not described herein.
Due to being formed with filled layer 151 in the gate openings 150, so the forming method further includes：Carry out high resistant
It injects after 161 (as shown in Figure 9), is formed before gate structure 180, remove the filled layer 151 (as shown in Figure 9), expose
The gate openings 150.
In the present embodiment, since the material of the filled layer 150 is organic matter, so removing the step of the filled layer 151
Suddenly include：The filled layer 151 is removed by way of dry etching.Specifically, being removed by way of dry etching described
In the step of filled layer 151, technological parameter includes：Power is in 1000W to 4700W ranges；Process gas includes：N2, flow
For in 500sccm to 4000sccm ranges, H2, flow is in 200sccm to 1000sccm ranges；Process gas pressure exists
In 200mTorr to 2000mTorr ranges；Technological temperature is within the scope of 200 DEG C to 300 DEG C.
It should be noted that as shown in Figure 10, after removing the filled layer 151, formed before gate structure 180, it is right
The resistance 160 and the source and drain doping area carry out annealing 162, to activate Doped ions.
The annealing 162 is injected by high resistant in the resistance 160 of 161 injections (as shown in Figure 9) for making
Doped ions relaxation is to the position of lattice, to realize activation；It is additionally operable to make the source and drain doping area by source and drain injection injection
Interior Doped ions relaxation is to the position of lattice, to realize activation.The annealing 162 both was used to activate to note in the resistance
The Doped ions entered, are additionally operable to activate the Doped ions in the source and drain doping area, this way advantageously reduce to be formed it is described
The heat budget of semiconductor structure is conducive to the performance for improving formed semiconductor structure.
Specifically, the step of carrying out annealing 162 to the resistance 160 and the source and drain doping area includes：Pass through point
The mode of peak annealing carries out the annealing 162.
It should be noted that in the step of carrying out the annealing 162 by way of spike annealing, annealing temperature is not
Preferably it is too high also should not be too low.
If annealing temperature is too low, the annealing 162 can not make in the resistance 160 and the source and drain doping area
Doped ions relaxation to the position of lattice, the annealing 161 can be influenced and activate the resistance 160 and the source and drain doping
The effect of Doped ions in area；If annealing temperature is too high, unnecessary process risk may be caused, and institute can be made
The Doped ions diffusion in resistance 160 and the source and drain doping area is stated, to influence the performance of formed semiconductor structure.So
In the present embodiment, to the resistance 160 and the source and drain doping area carry out annealing 162 the step of include：It is moved back by spike
The mode of fire carries out the annealing 162, and annealing temperature is within the scope of 950 DEG C to 1100 DEG C.
It should be noted that in the present embodiment, the high resistant injection 161 is first carried out to form resistance 160, forms institute later
State gate structure 180.This way is only an example, in other embodiments of the invention, can also use and be initially formed gate structure
The way of the high resistant injection is carried out again.It is previously formed in the technical solution that gate structure carries out high resistant injection again, the annealing
The technique needs of processing optimize, to reduce influence of the annealing to the gate structure.
Correspondingly, the present invention also provides a kind of semiconductor structures.
With reference to figure 6, the cross-sectional view of one embodiment of semiconductor structure of the present invention is shown.
Substrate 100, the substrate 100 include being used to form the active region 100a of active device and being used to form passive device
Passive area 100b；Gate structure on the active region 100a substrates 100；Positioned at gate structure both sides substrate
Source and drain doping area on 100；Resistance elements 130 on the passive area 100b substrates 100；Positioned at the gate structure
Expose the dielectric layer 170 on substrate 100 with the resistance elements 130.
The substrate 100 is for providing technological operation platform.Active device (active device), it is also referred to as active
Device, outer sector signal ﹐ is imposed in analogy and digital circuit can change the device of oneself fundamental characteristics itself.Active device energy
Enough execute data operation, processing element.Active crystal, product body including miscellaneous chip, such as in semiconductor element
Circuit, camera tube and display etc. belong to active member.
In the present embodiment, the substrate 100 of the active region 100a is used to form complementary mos device, i.e.,
Cmos device.The substrate 100 of the active region 100a includes being used to form the p type island region 100p of p-type active device and being used to form N
The N-type region of type active device.But in other embodiments of the invention, the active region substrate can also be only for forming p-type device
The substrate of part, i.e., the described active region only has p type island region；Alternatively, the active region substrate can also be only for forming N-type device,
The i.e. described active region substrate only has N-type region.
Passive device (passive device), also referred to as passive device, do not need the source of energy and realize its spy
The device of fixed function.From character of circuit, passive device itself does not consume electric energy, or electric energy is changed into various forms of
Other energy；And passive device only needs input signal, and not needing additional power source can work normally.So passive device is not
Influence signal essential characteristic, and only enable signal by by the circuit element that is not changed.Most common passive device have resistance,
Capacitance, inductance, Tao Zhen, crystal oscillator, transformer etc..
In the present embodiment, the substrate 100 of the passive area 100b is used to form resistance.Specifically, the passive area 100b
Substrate 100 is used to form polysilicon component (the non-silicide high resistance ploy of no silicide high value
Element), i.e. high resistance polysilicon resistance.
It should be noted that in the present embodiment, the active region 100a is disposed adjacent with the passive area 100b.The present invention
In other embodiment, the active region can not also be disposed adjacent with the passive area.Similar, the P in active region 100a
Type area 100p and the N-type region 100n are disposed adjacent；In other embodiments of the invention, the p type island region and the N-type in active region
Area can not also be disposed adjacent.
In the present embodiment, the material of the substrate 100 is monocrystalline silicon.In other embodiments of the invention, the substrate may be used also
Be multicrystalline silicon substrate, amorphous silicon substrate or germanium silicon substrate, carbon silicon substrate, silicon-on-insulator substrate, germanium substrate on insulator,
Glass substrate or III-V compound substrate, such as gallium nitride substrate or gallium arsenide substrate etc..The material of the substrate can
To choose the material for being suitable for process requirements or being easily integrated.
It should be noted that in the present embodiment, the active region 100a substrates 100 are used for fin formula field effect transistor, institute
As shown in figure 4, having fin 101 on the substrate 100 of the active region 100a, to have on the substrate 100 that the fin 101 exposes
There are separation layer 102, the separation layer 102 to cover the partial sidewall surface of the fin 101.
The fin 101 is used to provide the raceway groove of the fin formula field effect transistor.In the present embodiment, the fin 101
Material and the substrate 100 material identical, be all monocrystalline silicon.In other embodiments of the invention, the material of the fin
Can be different from the material of the substrate, germanium, germanium silicon, carbon silicon or GaAs etc. can be selected from and be suitable for forming the material of fin.
The separation layer 102 is for realizing the electric isolution between adjacent fin 101 and between adjacent semiconductor constructs.Tool
Body, in the present embodiment, in active region 100a, separation layer 102 is between adjacent fin 101, for realizing adjacent fin 101
Between electric isolution；In passive area 100b, separation layer 102 is located on substrate 100, for realizing the substrate 100 with formed
Electric isolution between passive device.In the present embodiment, the material of the separation layer 102 is silica.Other embodiments of the invention
In, the material of the separation layer can also be the materials such as silicon nitride or silicon oxynitride.
The gate structure is for avoiding formed source and drain doping area hypotelorism.In the present embodiment, the gate structure
For pseudo- grid structure 120, so dummy gate structure 120 is used to be formed by gate structure to be follow-up and take up space；The resistance
Material layer 130 is used to form resistance.
Specifically, the active region 100a substrates 100 are used to form fin formula field effect transistor, have on the substrate 100
There is fin 101, so dummy gate structure 120 is located at 101 on the fin, across the fin 101 and the covering fin
The surface of 101 atop parts and partial sidewall.
Dummy gate structure 120 is single layer structure, includes the dummy grid of polycrystalline silicon material.In other embodiments of the invention,
The material of the dummy grid can also be silica, silicon nitride, silicon oxynitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride or non-
The other materials such as brilliant carbon.In other of the invention embodiments, dummy gate structure can also be laminated construction, including dummy grid with
And the pseudo- oxide layer on the dummy grid, the material of the puppet oxide layer can be silica and silicon oxynitride.
In the present embodiment, the passive area 100b substrates 100 are used to form high resistance polysilicon resistance.So the resistance material
The material of the bed of material 130 is polysilicon.In other embodiments of the invention, the material of the resistance elements can also be monocrystalline silicon.
In addition, also there is separation layer 102, so the resistance elements 130 are located on the passive area 100b substrates 100
On the separation layer 102 of passive area 100b.Due to the material phase of the material and the resistance elements 130 of dummy gate structure 120
Together, it is all polysilicon, so dummy gate structure 120 and the resistance elements 130 can be formed by same technical process
To achieve the purpose that simplified processing step.
It should be noted that in the present embodiment, the semiconductor structure further includes：Positioned at 120 side wall of dummy gate structure
On side wall (not indicated in figure).The material of the side wall can be silica, silicon nitride, silicon carbide, carbonitride of silicium, carbon nitrogen oxygen
SiClx, silicon oxynitride, boron nitride or boron carbonitrides, the side wall can be single layer structure or laminated construction.In the present embodiment, institute
It is single layer structure to state side wall, and the material of the side wall is silicon nitride.
The source and drain doping area 103 is used to form source region or the drain region of active device.Specifically, the active region 100a linings
Bottom 100 is used to form fin formula field effect transistor, has fin 101 on the substrate 100, so the source and drain doping area is located at
In the fin of 120 both sides of dummy gate structure.
The source and drain doping area includes the stressor layers being located on the substrate of the gate structure both sides, is had in the stressor layers
Doped ions.In the present embodiment, the substrate 100 of the active region 100a includes p type island region 100p and N-type region 100n.So described
Stressor layers include：First stressor layers 140p of pseudo- 120 both sides of grid structure and it is located at N-type region on p type island region 100p substrates 100
Second stressor layers 140n of 120 both sides of pseudo- grid structure on 100n substrates 100.
The first stressor layers 140p is used to form the source and drain doping area of p-type active device, is used for p-type active device
Channel region applies compression.In the present embodiment, the first stressor layers 140p is " ∑ " shape stressor layers of germanium silicon material.It is described
There are p-type Doped ions, such as B ions, Ga ions or In ions, ion doping concentration exist in first stressor layers 140p
1.0E20atom/cm3To 1.0E22atom/cm3In range.
The second stressor layers 140n is used to form the source and drain doping area of N-type active device, is used for N-type active device
Channel region applies tensile stress.In the present embodiment, the second stressor layers 140n is the rectangular stressor layers of carbon silicon materials.Described
There is n-type doping ion, such as P ion, As ions or Sb ions, ion doping concentration exist in two stressor layers 140n
1.0E20atom/cm3To 1.0E22atom/cm3In range.
It should be noted that in the present embodiment, the semiconductor structure further includes：Positioned at 130 surface of resistance elements
Protective film (does not indicate) in figure.The material of the protective film is silicon nitride, for protecting institute in the stress layer formation process
Resistance elements 130 are stated, influence of the stressor layers formation process to the resistance elements 130 is reduced.
The dielectric layer 170 is interlayer dielectric layer, for realizing the electric isolution between semiconductor structure.In the present embodiment,
The gate structure is pseudo- grid structure 120, so the dielectric layer 170 is also used for defining the size of follow-up formed gate structure
The position and.
In the present embodiment, the material of the dielectric layer 170 is silica.In other embodiments of the invention, the dielectric layer
Material be also selected from other dielectric materials such as silicon nitride, silicon oxynitride or carbon silicon oxynitride.
Specifically, having fin 101 and separation layer 102 on the substrate 100.So the dielectric layer 170 is positioned at described
On substrate 100, the fin 101 and the separation layer 102.The dielectric layer 170 exposes dummy gate structure 120 and described
Resistance elements 130, the formation for formation and resistance for subsequent gate structure provide Process ba- sis.
It should be noted that in the present embodiment, high resistant injection subsequently is carried out to the resistance elements 130, to the electricity
It hinders and injects Doped ions, the resistance value for adjusting the resistance elements 130, to form resistance 160 in material layer 130.
When being carried out due to high resistant injection 161, dielectric layer 170, the medium are formed on active region 100a substrates 100
Layer 170 can protect the semiconductor structure on active region 100a substrates 100 during high resistant injects 161, reduce active region
100 upper semiconductor structure of 100a substrates is influenced by high resistant injection 161, can avoid mask during high resistant injects 160
Use, to advantageously reduce process costs.
It needs to remove the puppet after forming dielectric layer 170 further, since the gate structure is pseudo- grid structure 120
Grid structure 120 forms gate openings and forms gate structure in the gate openings.
To sum up, in technical solution of the present invention, source and drain doping area is formed before forming the dielectric layer；It is given an account of being formed
High resistant injection is carried out to the resistance elements after matter layer.The laggard of the dielectric layer is formed since the high resistant is infused in
Row, the dielectric layer can protect the semiconductor structure on active region substrate in high resistant injection process, reduce active region substrate
Upper semiconductor structure is influenced by high resistant injection, the use of mask can be avoided in high resistant injection process, to be conducive to
Reduce process costs.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (18)
1. a kind of forming method of semiconductor structure, which is characterized in that including：
Substrate is provided, the substrate includes the active region for being used to form active device and the passive area for being used to form passive device；
Form the pseudo- grid structure being located on the active region substrate and the resistance elements on the passive area substrate；
Source and drain doping area is formed on the substrate of dummy gate structure both sides；
It is formed after source and drain doping area, dielectric layer is formed on the substrate that dummy gate structure and the resistance elements are exposed,
The dielectric layer exposes dummy gate structure and the resistance elements；
Dummy gate structure is removed, gate openings are formed in the dielectric layer；
High resistant injection is carried out to the resistance elements that the dielectric layer exposes, forms resistance；
Gate structure is formed in the gate openings.
2. forming method as described in claim 1, which is characterized in that carried out to the resistance elements that the dielectric layer exposes high
In the step of resistance injection, technological parameter is：
Injection ion is B or BF2, Implantation Energy is in 1KeV to 30KeV ranges, and implantation dosage is in 1.0E14atom/cm2It arrives
1.0E16atom/cm2；
Alternatively, injection ion is As, Implantation Energy is in 5KeV to 50KeV ranges, and implantation dosage is in 1.0E14atom/cm2It arrives
1.0E16atom/cm2。
3. forming method as described in claim 1, which is characterized in that in the step of forming the resistance elements, the electricity
The material for hindering material layer is polysilicon or monocrystalline silicon；In the step of forming dummy gate structure, dummy gate structure is single layer knot
The material of structure, dummy gate structure is polysilicon.
4. forming method as described in claim 1, which is characterized in that carried out to the resistance elements that the dielectric layer exposes high
Hindering the step of injecting includes：After removing dummy gate structure, high resistant note is carried out to the resistance elements that the dielectric layer exposes
Enter, forms resistance；
The forming method further includes：
After removing dummy gate structure, before carrying out high resistant injection to the resistance elements that the dielectric layer exposes, described
Filled layer is formed in gate openings；
After carrying out high resistant injection, is formed before gate structure, remove the filled layer, expose the gate openings.
5. forming method as claimed in claim 4, which is characterized in that the material of the filled layer is organic matter.
6. forming method as described in claim 4 or 5, which is characterized in that the filled layer is bottom anti-reflection layer or organic
Dielectric layer.
7. forming method as described in claim 4 or 5, which is characterized in that the step of removing the filled layer include：By dry
The mode of method etching removes the filled layer.
8. forming method as claimed in claim 7, which is characterized in that remove the filled layer by way of dry etching
In step, technological parameter includes：Power is in 1000W to 4700W ranges；Process gas includes：N2, flow arrives for 500sccm
Within the scope of 4000sccm, H2, flow is in 200sccm to 1000sccm ranges；Process gas pressure is arrived in 200mTorr
Within the scope of 2000mTorr；Technological temperature is within the scope of 200 DEG C to 300 DEG C.
9. forming method as claimed in claim 7, which is characterized in that the forming method further includes：Remove the filled layer
Later, it is formed before gate structure, the resistance and the source and drain doping area is made annealing treatment, to activate Doped ions.
10. forming method as claimed in claim 9, which is characterized in that moved back to the resistance and the source and drain doping area
Fire processing the step of include：The annealing is carried out by way of spike annealing, annealing temperature is in 950 DEG C to 1100 DEG C models
In enclosing.
11. forming method as described in claim 1, which is characterized in that form source on the substrate of dummy gate structure both sides
Leak doped region the step of include：
Stressor layers are formed on the substrate of pseudo- grid structure both sides；
Ion implanting is carried out to the stressor layers, forms the source and drain doping area.
12. forming method as claimed in claim 11, which is characterized in that in the step of substrate is provided, the lining of the active region
Bottom includes the p type island region for being used to form p-type active device and the N-type region for being used to form N-type active device；
Include in the step of forming stressor layers on the substrate of pseudo- grid structure both sides：It is formed and is located at pseudo- grid structure two on the substrate of p type island region
First stressor layers of side；Form the second stressor layers for being located at pseudo- grid structure both sides on N-type region substrate；
Carry out ion implanting the step of include：First ion implanting is carried out to first stressor layers, is formed on the substrate of p type island region
Source and drain doping area；Second ion implanting is carried out to second stressor layers, forms the source and drain doping area on N-type region substrate.
13. forming method as described in claim 1, which is characterized in that the active region substrate is used to form fin field effect
Transistor；
In the step of substrate is provided, there is fin on the substrate of the active region, there is isolation on the substrate that the fin exposes
Layer, the separation layer cover the partial sidewall surface of the fin；
In the step of forming dummy gate structure, dummy gate structure is located on the fin, across the fin and covering institute
State the surface of fin atop part and partial sidewall；
In the step of forming resistance elements, the resistance elements are located on the separation layer of passive area；
Formed source and drain doping area the step of include：The source and drain doping area is formed in the fin of dummy gate structure both sides；
In the step of forming gate openings, the table of the fin atop part and partial sidewall is exposed in the gate openings bottom
Face.
14. a kind of semiconductor structure, which is characterized in that including：
Substrate, the substrate include the active region for being used to form active device and the passive area for being used to form passive device；
Gate structure on the active region substrate；
Source and drain doping area on the substrate of the gate structure both sides；
Resistance elements on the passive area substrate；
Expose the dielectric layer on substrate positioned at the gate structure and the resistance elements.
15. semiconductor structure as claimed in claim 14, which is characterized in that the resistance elements are polysilicon layer；It is described
Gate structure is pseudo- grid structure, and the material of dummy gate structure is polysilicon.
16. semiconductor structure as claimed in claim 14, which is characterized in that the source and drain doping area includes being located at the grid
Stressor layers on the substrate of structure both sides, the stressor layers are interior to have Doped ions.
17. semiconductor structure as claimed in claim 16, which is characterized in that the substrate of the active region includes being used to form P
The p type island region of type active device and the N-type region for being used to form N-type active device；
The stressor layers include：Positioned at the first stressor layers of gate structure both sides on the substrate of p type island region and positioned at grid on N-type region substrate
Second stressor layers of pole structure both sides, first stressor layers are interior to have p-type Doped ions, has N in second stressor layers
Type Doped ions.
18. semiconductor structure as claimed in claim 14, which is characterized in that the dielectric layer exposes the gate structure and institute
State resistance elements.
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