CN108280981B - Wireless control system of micro unmanned aerial vehicle - Google Patents
Wireless control system of micro unmanned aerial vehicle Download PDFInfo
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- CN108280981B CN108280981B CN201810170053.6A CN201810170053A CN108280981B CN 108280981 B CN108280981 B CN 108280981B CN 201810170053 A CN201810170053 A CN 201810170053A CN 108280981 B CN108280981 B CN 108280981B
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- G08—SIGNALLING
- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
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- G08C17/02—Arrangements for transmitting signals characterised by the use of a wireless electrical link using a radio link
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Abstract
In order to reduce the communication circuit cost of unmanned aerial vehicle signal transmission equipment on the premise of ensuring stable communication quality, the invention provides a wireless control system of a micro unmanned aerial vehicle, which comprises a control unit, an instruction input unit, a signal transceiving module and a power module, wherein the control unit receives a wireless control instruction input by the instruction input unit and controls the signal transceiving module to transmit and receive data and instructions, the power module supplies power to the control unit, the instruction input unit and the signal transceiving module, the control unit receives the wireless control instruction input by the instruction input unit and controls the signal transceiving module to transmit and receive data and instructions, and the power module supplies power to the control unit, the instruction input unit and the signal transceiving module. The invention greatly reduces the influence of data error or signal distortion caused by temperature drift on the communication unit.
Description
Technical Field
The invention belongs to the technical field of environmental monitoring, and particularly relates to a wireless control system of a micro unmanned aerial vehicle.
Background
Four rotor unmanned vehicles are the novel unmanned vehicles who is researched and manufactured in recent years, can take off and land perpendicularly, regard four rotors as power device's aircraft, have hover, fly backward, survey the ability of flying, the screw is little, flight safety, simple structure, and control is nimble, to advantages such as wireless interference is less strong. The method can be used as a carrier for data transmission between a server and a network node in a remote area, and the problem of data transmission in the remote area is solved.
However, the range of the unmanned aerial vehicle in the prior art is limited, and especially the communication circuit is easy to cause temperature drift under the influence of the flying height and the environment. The prior art has dealt with this situation mostly by using current mirrors or multiple differential amplifiers, but this approach is very costly.
Disclosure of Invention
In order to reduce the communication circuit cost of unmanned aerial vehicle signal transmission equipment on the premise of ensuring stable communication quality, the invention provides a wireless control system of a micro unmanned aerial vehicle, which comprises a control unit, a command input unit, a signal transceiving module and a power supply module.
Furthermore, the signal transceiver module includes a data interface, a digital signal processor, a modulation/demodulation circuit, a storage unit, a signal preprocessing module, and a microstrip antenna array, the data interface is used to connect an external data source for debugging, the digital signal processor is connected to the modulation/demodulation circuit, the storage unit, and the signal preprocessing module, the modulation/demodulation circuit, the signal preprocessing module, and the microstrip antenna array are connected in sequence, and the storage unit is connected to an output end of the modulation/demodulation circuit.
Further, the data interface is an IEEE1394 interface.
Further, the modulation/demodulation circuit comprises a modulation/demodulation module in a phase modulation mode.
Furthermore, the microstrip antenna is provided with a first substrate and a second substrate, the first substrate and the second substrate are arranged opposite to each other, and conductor materials are coated on the upper surface of the first substrate and the upper surface and the lower surface of the second substrate; an inverted L-shaped patch is arranged on the upper surface of the first substrate, the length of the short side is 0.03-0.1 mm, the length of the long side is 0.06-0.15 mm, and the corner is an obtuse angle; an annular gap is arranged at the center of the inverted L-shaped patch by taking a diagonal line as an axis, the length of the gap is 0.08-0.2 mm, and the width of the gap is 0.06-0.17 mm; a circular gap is formed inwards in the middle point of the four sides of the inverted L-shaped patch, and the radius of the gap is 0.05-0.08 mm; the upper surface of the second substrate is provided with an inverted T-shaped patch with a slot and a chamfer, the middle point of four sides of the inverted T-shaped patch is provided with an inward rectangular slot, the length of the slot is 0.02-0.04 mm, and the width of the slot is 0.01-0.02 mm.
Further, the dielectric constant of the first substrate and the second substrate is 18.
Further, the conductor material is silver.
Further, the thickness of the first substrate and the second substrate is 1.8-3 mm.
Further, the signal preprocessing module comprises: a first power supply VDD, a second power supply VCC, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a fifth triode T5-a seventh triode T7, a twelfth transistor T12-a nineteenth triode T29, a current source, an amplifier a1, a first comparator C _1, a second comparator C _2, a first D flip-flop Q1, a second D flip-flop Q2, a third D flip-flop Q3, a fourth D flip-flop Q4, a first signal terminal G (n), a second signal terminal G (n-1), a third signal terminal G (n +1), a signal input terminal Vin, a signal output terminal Vout, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, a capacitor 1, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, a third inverter, a fourth inverter, a seventh inverter, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4; an input terminal of the first inverter is connected to a first signal terminal G (n), a base of a thirteenth transistor T13 and a base of a seventh transistor T7, an output terminal of the first inverter is connected to a base of a sixth transistor T6, a second signal terminal G (n-1) is connected to a collector of the sixth transistor T6 and a collector of the seventh transistor T7, an emitter of the sixth transistor T6 and an emitter of the seventh transistor T7 are connected to a collector of a twelfth transistor T12, a base of a fourteenth transistor T14 and one end of a first capacitor C1, an emitter of the twelfth transistor T12 is connected to the other end of the first capacitor C1 and to ground, a base of the twelfth transistor T12 is connected to a first signal terminal G (n), a collector of the thirteenth transistor T13 is connected to an input signal Vin, an emitter of the thirteenth transistor T13 is connected to an emitter of a fifteenth transistor T15 and one end of the second capacitor C2, the other end of the second capacitor C2 is connected to the collector of a fourteenth transistor T14, the emitter of the fourteenth transistor T14 is connected to the emitter of a fifteenth transistor T15, the collector of a fifth transistor T5, the collector of a seventeenth transistor T17 and the collector of a nineteenth transistor T19, the base of the fifth transistor T5 is connected to the collector of a sixth transistor T6 via a seventh resistor R7, the base of the fifteenth transistor T15 is connected to the second signal terminal G (n-1), the collector of the eighteenth transistor T18 is connected to the signal input terminal Vin, the base of the eighteenth transistor T18 is connected to the second signal terminal G (n-1) and the base of the seventeenth transistor T17, the base of the nineteenth transistor T19 is connected to the base of the twentieth transistor T20, the second signal terminal G (n-1) and the base of the twenty-fifth transistor T25, the emitter of the nineteenth transistor T19 is connected to the emitter of the twentieth transistor T20, An input terminal of a second comparator C _2 and one terminal of a second resistor R2, the other terminal of the second resistor R2 is connected to one terminal of a fifth resistor R5, a collector of a twenty-fifth transistor T25 and a collector of a twenty-fourth transistor T24, an emitter of an eighteenth transistor T18 is connected to a collector of a twentieth transistor T20 and a positive input terminal of an amplifier a1, a negative input terminal of an amplifier a1 is connected to an emitter of a twenty-first transistor T21 and one terminal of a third resistor R3 via a fourth capacitor C4, an output terminal of an amplifier a1 is connected to a base of the twenty-first transistor T21, a collector of the twenty-first transistor T21 is connected to a second power source VCC, the third resistor R3, the fourth resistor R4 and the fifth resistor R5 are connected in series, the other terminal of the third resistor R3 is connected to one terminal of the fourth resistor R4 and one terminal of the collector of the twenty-second transistor T22, the base of the twenty-second transistor T22 and the collector of the twenty-, the other end of the fourth resistor R4d is connected to the collector of the twenty-fourth transistor T24, the other end of the fifth resistor R5 is grounded, the first signal terminal G (n) is connected to the base of the twenty-fourth transistor T24 via the second inverter, the first signal terminal G (n) is connected to the base of the twenty-third transistor T23, the emitter of the twenty-second transistor T22 and the emitter of the twenty-third transistor T23 are both connected to the emitter of the twenty-fourth transistor T24 and the emitter of the twenty-fifth transistor T25, and the other end of the second comparator C _2 is also connected to the collector of the twenty-sixth transistor T26 and the collector of the twenty-seventh transistor T27, the base of the twenty-sixth transistor T26 is connected to the third signal terminal G (n +1), the second signal terminal G (n-1) is connected to the base of the twenty-seventh transistor T27 via the third inverter, and the emitter of the twenty-sixth transistor T26 and the emitter of the seventh transistor T27 are both connected to the first end of the first capacitor C3 One end of the comparator C _1, an emitter of a seventeenth transistor T17 is connected to the other end of the first comparator C _1 through an eighth resistor R8, the other end of the third capacitor C3 is grounded, an emitter of a fifth transistor T5 is connected to one input end of a first or operator, an output end of the second comparator C _2 is connected to the other input end of the first or operator, an output end of the first comparator C _1 is connected to an R end of the first D flip-flop Q1 through a fifth inverter, a second signal end G (n-1) is connected to a clock end of the first D flip-flop Q1 through a fourth inverter, and a D end of the first D flip-flop Q1 is connected to a second power source VCC; a D end of the second D trigger Q2 is connected with a second power supply VCC, a clock end is connected with an output end of the OR gate, an R end is connected with a first signal end G (n), a Q end is connected with one input end of the AND gate through a sixth inverter, and the other input end of the AND gate is connected with a second signal end G (n-1); a Q terminal of the first D flip-flop Q1 is connected to a collector of the twenty-eighth transistor T28 and a collector of the twenty-ninth transistor T29, and a base of the twenty-ninth transistor T29 and a base of the twenty-eighth transistor T28 are connected to the third signal terminal G (n + 1); a D end of the third D flip-flop Q3 is connected with an emitter of a twenty-ninth transistor T29, a clock end is connected with an output end of an AND gate, an R end is connected with a third signal end G (n +1), a D end is connected with a D end of the fourth D flip-flop Q4 through a seventh inverter, an emitter of the twenty-eighth transistor T28 is connected with an R end of the fourth D flip-flop Q4, a clock end of the fourth D flip-flop Q4 is connected with a first signal end G (n), and a D end of the fourth D flip-flop Q4 is connected with a signal output end Vout; the signal of the signal input end Vin comes from the output signal of the detection device; the first signal terminal g (n) is obtained by an output signal of a second or operator, wherein: a crystal oscillator signal CLK of the signal preprocessing unit is used as an input signal of a second OR operator, and an early warning signal generated by the image processing unit according to a preset mode is used as another input signal of the second OR operator; the signal of the second signal end G (n-1) has the same amplitude and frequency as the first signal end G (n) but a phase delayed by one period of the crystal oscillator signal CLK, and the signal of the third signal end G (n +1) has the same amplitude and frequency as the first signal end G (n) but a phase delayed by one period of the crystal oscillator signal CLK.
The technical scheme of the invention has the following advantages:
the monitoring system can condition signals by a periodic forward-push mode and a periodic backward-push mode through the unique microstrip antenna and the signal preprocessing module matched with the microstrip antenna, and the influence of data errors or signal distortion caused by temperature drift on the communication unit is greatly reduced. Through tests, compared with the signal of the communication module which is not preprocessed, the preprocessing of the invention can improve the temperature stability between minus 29 ℃ and plus 85 ℃ by more than 70 percent, thereby greatly facilitating the data acquisition accuracy of the monitoring terminal and the effectiveness of analysis statistics.
Drawings
Fig. 1 shows a block diagram of the components of a signal transmission device according to the invention.
Fig. 2 shows a circuit diagram of the signal preprocessing module of the present invention.
Detailed Description
As shown in figure 1, a wireless control system of micro unmanned aerial vehicle, including the control unit, instruction input unit, signal transceiver module and power module, the control unit receives the wireless control instruction of instruction input unit input to control signal transceiver module carries out the receiving and dispatching of data and instruction, power module does the control unit, instruction input unit and the power supply of signal transceiver module.
Furthermore, the signal transceiver module includes a data interface, a digital signal processor, a modulation/demodulation circuit, a storage unit, a signal preprocessing module, and a microstrip antenna array, the data interface is used to connect an external data source for debugging, the digital signal processor is connected to the modulation/demodulation circuit, the storage unit, and the signal preprocessing module, the modulation/demodulation circuit, the signal preprocessing module, and the microstrip antenna array are connected in sequence, and the storage unit is connected to an output end of the modulation/demodulation circuit.
Further, the data interface is an IEEE1394 interface.
Further, the modulation/demodulation circuit comprises a modulation/demodulation module in a phase modulation mode.
Furthermore, the microstrip antenna is provided with a first substrate and a second substrate, the first substrate and the second substrate are arranged opposite to each other, and conductor materials are coated on the upper surface of the first substrate and the upper surface and the lower surface of the second substrate; an inverted L-shaped patch is arranged on the upper surface of the first substrate, the length of the short side is 0.03-0.1 mm, the length of the long side is 0.06-0.15 mm, and the corner is an obtuse angle; an annular gap is arranged at the center of the inverted L-shaped patch by taking a diagonal line as an axis, the length of the gap is 0.08-0.2 mm, and the width of the gap is 0.06-0.17 mm; a circular gap is formed inwards in the middle point of the four sides of the inverted L-shaped patch, and the radius of the gap is 0.05-0.08 mm; the upper surface of the second substrate is provided with an inverted T-shaped patch with a slot and a chamfer, the middle point of four sides of the inverted T-shaped patch is provided with an inward rectangular slot, the length of the slot is 0.02-0.04 mm, and the width of the slot is 0.01-0.02 mm.
Further, the dielectric constant of the first substrate and the second substrate is 18.
Further, the conductor material is silver.
Further, the thickness of the first substrate and the second substrate is 1.8-3 mm.
Further, the signal preprocessing module comprises: a first power supply VDD, a second power supply VCC, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a fifth triode T5-a seventh triode T7, a twelfth transistor T12-a nineteenth triode T29, a current source, an amplifier a1, a first comparator C _1, a second comparator C _2, a first D flip-flop Q1, a second D flip-flop Q2, a third D flip-flop Q3, a fourth D flip-flop Q4, a first signal terminal G (n), a second signal terminal G (n-1), a third signal terminal G (n +1), a signal input terminal Vin, a signal output terminal Vout, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, a capacitor 1, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, a third inverter, a fourth inverter, a seventh inverter, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4; an input terminal of the first inverter is connected to a first signal terminal G (n), a base of a thirteenth transistor T13 and a base of a seventh transistor T7, an output terminal of the first inverter is connected to a base of a sixth transistor T6, a second signal terminal G (n-1) is connected to a collector of the sixth transistor T6 and a collector of the seventh transistor T7, an emitter of the sixth transistor T6 and an emitter of the seventh transistor T7 are connected to a collector of a twelfth transistor T12, a base of a fourteenth transistor T14 and one end of a first capacitor C1, an emitter of the twelfth transistor T12 is connected to the other end of the first capacitor C1 and to ground, a base of the twelfth transistor T12 is connected to a first signal terminal G (n), a collector of the thirteenth transistor T13 is connected to an input signal Vin, an emitter of the thirteenth transistor T13 is connected to an emitter of a fifteenth transistor T15 and one end of the second capacitor C2, the other end of the second capacitor C2 is connected to the collector of a fourteenth transistor T14, the emitter of the fourteenth transistor T14 is connected to the emitter of a fifteenth transistor T15, the collector of a fifth transistor T5, the collector of a seventeenth transistor T17 and the collector of a nineteenth transistor T19, the base of the fifth transistor T5 is connected to the collector of a sixth transistor T6 via a seventh resistor R7, the base of the fifteenth transistor T15 is connected to the second signal terminal G (n-1), the collector of the eighteenth transistor T18 is connected to the signal input terminal Vin, the base of the eighteenth transistor T18 is connected to the second signal terminal G (n-1) and the base of the seventeenth transistor T17, the base of the nineteenth transistor T19 is connected to the base of the twentieth transistor T20, the second signal terminal G (n-1) and the base of the twenty-fifth transistor T25, the emitter of the nineteenth transistor T19 is connected to the emitter of the twentieth transistor T20, An input terminal of a second comparator C _2 and one terminal of a second resistor R2, the other terminal of the second resistor R2 is connected to one terminal of a fifth resistor R5, a collector of a twenty-fifth transistor T25 and a collector of a twenty-fourth transistor T24, an emitter of an eighteenth transistor T18 is connected to a collector of a twentieth transistor T20 and a positive input terminal of an amplifier a1, a negative input terminal of an amplifier a1 is connected to an emitter of a twenty-first transistor T21 and one terminal of a third resistor R3 via a fourth capacitor C4, an output terminal of an amplifier a1 is connected to a base of the twenty-first transistor T21, a collector of the twenty-first transistor T21 is connected to a second power source VCC, the third resistor R3, the fourth resistor R4 and the fifth resistor R5 are connected in series, the other terminal of the third resistor R3 is connected to one terminal of the fourth resistor R4 and one terminal of the collector of the twenty-second transistor T22, the base of the twenty-second transistor T22 and the collector of the twenty-, the other end of the fourth resistor R4d is connected to the collector of the twenty-fourth transistor T24, the other end of the fifth resistor R5 is grounded, the first signal terminal G (n) is connected to the base of the twenty-fourth transistor T24 via the second inverter, the first signal terminal G (n) is connected to the base of the twenty-third transistor T23, the emitter of the twenty-second transistor T22 and the emitter of the twenty-third transistor T23 are both connected to the emitter of the twenty-fourth transistor T24 and the emitter of the twenty-fifth transistor T25, and the other end of the second comparator C _2 is also connected to the collector of the twenty-sixth transistor T26 and the collector of the twenty-seventh transistor T27, the base of the twenty-sixth transistor T26 is connected to the third signal terminal G (n +1), the second signal terminal G (n-1) is connected to the base of the twenty-seventh transistor T27 via the third inverter, and the emitter of the twenty-sixth transistor T26 and the emitter of the seventh transistor T27 are both connected to the first end of the first capacitor C3 One end of the comparator C _1, an emitter of a seventeenth transistor T17 is connected to the other end of the first comparator C _1 through an eighth resistor R8, the other end of the third capacitor C3 is grounded, an emitter of a fifth transistor T5 is connected to one input end of a first or operator, an output end of the second comparator C _2 is connected to the other input end of the first or operator, an output end of the first comparator C _1 is connected to an R end of the first D flip-flop Q1 through a fifth inverter, a second signal end G (n-1) is connected to a clock end of the first D flip-flop Q1 through a fourth inverter, and a D end of the first D flip-flop Q1 is connected to a second power source VCC; a D end of the second D trigger Q2 is connected with a second power supply VCC, a clock end is connected with an output end of the OR gate, an R end is connected with a first signal end G (n), a Q end is connected with one input end of the AND gate through a sixth inverter, and the other input end of the AND gate is connected with a second signal end G (n-1); a Q terminal of the first D flip-flop Q1 is connected to a collector of the twenty-eighth transistor T28 and a collector of the twenty-ninth transistor T29, and a base of the twenty-ninth transistor T29 and a base of the twenty-eighth transistor T28 are connected to the third signal terminal G (n + 1); a D end of the third D flip-flop Q3 is connected with an emitter of a twenty-ninth transistor T29, a clock end is connected with an output end of an AND gate, an R end is connected with a third signal end G (n +1), a D end is connected with a D end of the fourth D flip-flop Q4 through a seventh inverter, an emitter of the twenty-eighth transistor T28 is connected with an R end of the fourth D flip-flop Q4, a clock end of the fourth D flip-flop Q4 is connected with a first signal end G (n), and a D end of the fourth D flip-flop Q4 is connected with a signal output end Vout; the signal of the signal input end Vin comes from the output signal of the detection device; the first signal terminal g (n) is obtained by an output signal of a second or operator, wherein: a crystal oscillator signal CLK of the signal preprocessing unit is used as an input signal of a second OR operator, and an early warning signal generated by the image processing unit according to a preset mode is used as another input signal of the second OR operator; the signal of the second signal end G (n-1) has the same amplitude and frequency as the first signal end G (n) but a phase delayed by one period of the crystal oscillator signal CLK, and the signal of the third signal end G (n +1) has the same amplitude and frequency as the first signal end G (n) but a phase delayed by one period of the crystal oscillator signal CLK.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (1)
1. A wireless control system of a micro unmanned aerial vehicle comprises a control unit, an instruction input unit, a signal transceiving module and a power module, wherein the control unit receives a wireless control instruction input by the instruction input unit and controls the signal transceiving module to transmit and receive data and instructions, and the power module supplies power to the control unit, the instruction input unit and the signal transceiving module;
the signal receiving and transmitting module comprises a data interface, a digital signal processor, a modulation/demodulation circuit, a storage unit, a signal preprocessing module and a microstrip antenna array, wherein the data interface is used for connecting an external data source for debugging, the digital signal processor is connected with the modulation/demodulation circuit, the storage unit and the signal preprocessing module, the modulation/demodulation circuit, the signal preprocessing module and the microstrip antenna array are sequentially connected, and the storage unit is connected with the output end of the modulation/demodulation circuit;
the data interface is an IEEE1394 interface;
the modulation/demodulation circuit comprises a modulation/demodulation module of a phase modulation mode;
the microstrip antenna is characterized in that the microstrip antenna is provided with a first substrate and a second substrate, the first substrate and the second substrate are arranged oppositely, and conductor materials are coated on the upper surface of the first substrate and the upper surface and the lower surface of the second substrate; an inverted L-shaped patch is arranged on the upper surface of the first substrate, the length of the short side is 0.03-0.1 mm, the length of the long side is 0.06-0.15 mm, and the corner is an obtuse angle; an annular gap is arranged at the center of the inverted L-shaped patch by taking a diagonal line as an axis, the length of the gap is 0.08-0.2 mm, and the width of the gap is 0.06-0.17 mm; a circular gap is formed inwards in the middle point of the four sides of the inverted L-shaped patch, and the radius of the gap is 0.05-0.08 mm; an inverted T-shaped patch with a slot and a chamfer is arranged on the upper surface of the second substrate, an inward rectangular slot is arranged at the midpoint of the four sides of the inverted T-shaped patch, the slot has the length of 0.02-0.04 mm and the width of 0.01-0.02 mm;
the dielectric constant of the first substrate and the second substrate is 18;
the conductor material is silver;
the thickness of the first substrate and the second substrate is 1.8-3 mm;
the signal preprocessing module comprises: a first power supply VDD, a second power supply VCC, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a fifth triode T5-a seventh triode T7, a twelfth transistor T12-a nineteenth triode T29, a current source, an amplifier a1, a first comparator C _1, a second comparator C _2, a first D flip-flop Q1, a second D flip-flop Q2, a third D flip-flop Q3, a fourth D flip-flop Q4, a first signal terminal G (n), a second signal terminal G (n-1), a third signal terminal G (n +1), a signal input terminal Vin, a signal output terminal Vout, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, a capacitor 1, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, a third inverter, a fourth inverter, a seventh inverter, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4; an input terminal of the first inverter is connected to a first signal terminal G (n), a base of a thirteenth transistor T13 and a base of a seventh transistor T7, an output terminal of the first inverter is connected to a base of a sixth transistor T6, a second signal terminal G (n-1) is connected to a collector of the sixth transistor T6 and a collector of the seventh transistor T7, an emitter of the sixth transistor T6 and an emitter of the seventh transistor T7 are connected to a collector of a twelfth transistor T12, a base of a fourteenth transistor T14 and one end of a first capacitor C1, an emitter of the twelfth transistor T12 is connected to the other end of the first capacitor C1 and to ground, a base of the twelfth transistor T12 is connected to a first signal terminal G (n), a collector of the thirteenth transistor T13 is connected to an input signal Vin, an emitter of the thirteenth transistor T13 is connected to an emitter of a fifteenth transistor T15 and one end of the second capacitor C2, the other end of the second capacitor C2 is connected to the collector of a fourteenth transistor T14, the emitter of the fourteenth transistor T14 is connected to the emitter of a fifteenth transistor T15, the collector of a fifth transistor T5, the collector of a seventeenth transistor T17 and the collector of a nineteenth transistor T19, the base of the fifth transistor T5 is connected to the collector of a sixth transistor T6 via a seventh resistor R7, the base of the fifteenth transistor T15 is connected to the second signal terminal G (n-1), the collector of the eighteenth transistor T18 is connected to the signal input terminal Vin, the base of the eighteenth transistor T18 is connected to the second signal terminal G (n-1) and the base of the seventeenth transistor T17, the base of the nineteenth transistor T19 is connected to the base of the twentieth transistor T20, the second signal terminal G (n-1) and the base of the twenty-fifth transistor T25, the emitter of the nineteenth transistor T19 is connected to the emitter of the twentieth transistor T20, An input terminal of a second comparator C _2 and one terminal of a second resistor R2, the other terminal of the second resistor R2 is connected to one terminal of a fifth resistor R5, a collector of a twenty-fifth transistor T25 and a collector of a twenty-fourth transistor T24, an emitter of an eighteenth transistor T18 is connected to a collector of a twentieth transistor T20 and a positive input terminal of an amplifier a1, a negative input terminal of an amplifier a1 is connected to an emitter of a twenty-first transistor T21 and one terminal of a third resistor R3 via a fourth capacitor C4, an output terminal of an amplifier a1 is connected to a base of the twenty-first transistor T21, a collector of the twenty-first transistor T21 is connected to a second power source VCC, the third resistor R3, the fourth resistor R4 and the fifth resistor R5 are connected in series, the other terminal of the third resistor R3 is connected to one terminal of the fourth resistor R4 and one terminal of the collector of the twenty-second transistor T22, the base of the twenty-second transistor T22 and the collector of the twenty-, the other end of the fourth resistor R4d is connected to the collector of a twenty-fourth transistor T24, the other end of the fifth resistor R5 is grounded, the first signal terminal G (n) is connected to the base of a twenty-fourth transistor T22 via a second inverter, the first signal terminal G (n) is connected to the base of a twenty-third transistor T23, the emitter of the twenty-second transistor T22 and the emitter of a twenty-third transistor T23 are both connected to the emitter of the twenty-fourth transistor T24 and the emitter of the twenty-fifth transistor T25, and the other end of the second comparator C _2 and further to the collector of a twenty-sixth transistor T26 and the collector of a twenty-seventh transistor T27, the base of the twenty-sixth transistor T26 is connected to the third signal terminal G (n +1), the second signal terminal G (n-1) is connected to the base of a twenty-seventh transistor T27 via a third inverter, the emitter of the twenty-sixth transistor T26 and the emitter of the twenty-seventh transistor T27 are both connected to the first end of the third capacitor C35 and the first comparator C3 One end of the comparator C _1, an emitter of the seventeenth transistor T17 is connected to the other end of the first comparator C _1 through the eighth resistor R8, the other end of the third capacitor C3 is grounded, an emitter of the fifth transistor T5 is connected to one input terminal of the first or operator, an output terminal of the second comparator C _2 is connected to the other input terminal of the first or operator, an output terminal of the first comparator C _1 is connected to the R terminal of the first D flip-flop Q1 through the fifth inverter, the second signal terminal G (n-1) is connected to the clock terminal of the first D flip-flop Q1 through the fourth inverter, and the D terminal of the first D flip-flop Q1 is connected to the second power source VCC; a D end of the second D trigger Q2 is connected with a second power supply VCC, a clock end is connected with an output end of the OR gate, an R end is connected with a first signal end G (n), a Q end is connected with one input end of the AND gate through a sixth inverter, and the other input end of the AND gate is connected with a second signal end G (n-1); a Q terminal of the first D flip-flop Q1 is connected to a collector of the twenty-eighth transistor T28 and a collector of the twenty-ninth transistor T29, and a base of the twenty-ninth transistor T29 and a base of the twenty-eighth transistor T28 are connected to the third signal terminal G (n + 1); a D end of the third D flip-flop Q3 is connected with an emitter of a twenty-ninth transistor T29, a clock end is connected with an output end of an AND gate, an R end is connected with a third signal end G (n +1), a D end is connected with a D end of the fourth D flip-flop Q4 through a seventh inverter, an emitter of the twenty-eighth transistor T28 is connected with an R end of the fourth D flip-flop Q4, a clock end of the fourth D flip-flop Q4 is connected with a first signal end G (n), and a D end of the fourth D flip-flop Q4 is connected with a signal output end Vout; the signal of the signal input end Vin comes from the output signal of the detection device; the first signal terminal g (n) is obtained by an output signal of a second or operator, wherein: a crystal oscillator signal CLK of the signal preprocessing module is used as an input signal of a second OR operator, and an early warning signal generated by the image processing unit according to a preset mode is used as another input signal of the second OR operator; the signal of the second signal end G (n-1) has the same amplitude and frequency as the first signal end G (n) but a phase delayed by one period of the crystal oscillator signal CLK, and the signal of the third signal end G (n +1) has the same amplitude and frequency as the first signal end G (n) but a phase delayed by one period of the crystal oscillator signal CLK.
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| CN108280981B true CN108280981B (en) | 2020-12-04 |
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| US7551989B2 (en) * | 2006-06-21 | 2009-06-23 | Calspan Corporation | Autonomous outer loop control of man-rated fly-by-wire aircraft |
| CN204857944U (en) * | 2015-05-25 | 2015-12-09 | 深圳光启高等理工研究院 | Antenna |
| CN105141924B (en) * | 2015-09-17 | 2018-03-30 | 成都时代星光科技有限公司 | Wireless image monitoring system based on 4G technologies |
| CN205311921U (en) * | 2015-11-25 | 2016-06-15 | 深圳市大疆创新科技有限公司 | Take photo by plane with burnt control system and aircraft |
| CN205721375U (en) * | 2016-02-19 | 2016-11-23 | 深圳供电局有限公司 | Many rotor unmanned aerial vehicle communication and safety monitoring system |
| CN205610628U (en) * | 2016-05-10 | 2016-09-28 | 深圳市智璟科技有限公司 | A signal transceiver circuits for flight controller |
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