CN108270406B

CN108270406B - Power synthesis circuit based on-chip transformer

Info

Publication number: CN108270406B
Application number: CN201810071114.3A
Authority: CN
Inventors: 任江川; 戴若凡; 何军
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2018-01-25
Filing date: 2018-01-25
Publication date: 2022-01-14
Anticipated expiration: 2038-01-25
Also published as: CN108270406A

Abstract

The invention discloses a power synthesis circuit based on an on-chip transformer, which comprises: an on-chip transformer composed of a plurality of primary coils and a secondary coil; the secondary coil is composed of a plurality of annular turns formed by surrounding the same layer of planar metal wires, each primary coil is also composed of corresponding annular turns formed by surrounding the same layer of planar metal wires, and the number of the annular turns of each primary coil is respectively smaller than that of the annular turns of the secondary coil; the metal level of the planar metal wire of the annular turn of each primary coil is higher or lower than that of the planar metal wire of the annular turn of the corresponding secondary coil; in the longitudinal direction, the planar wires of the loop turns of each primary coil are perfectly aligned with the planar wires of the corresponding loop turns of the secondary coil, and the perfectly aligned structure allows for an increased coupling area of the primary and secondary coils. The invention can reduce the area of the circuit, improve the coupling factor between the primary coil and the secondary coil and improve the efficiency of the transformer.

Description

Power synthesis circuit based on-chip transformer

Technical Field

The present invention relates to a semiconductor integrated circuit, and more particularly, to a power combining circuit based on an on-chip transformer.

Background

As shown in fig. 1, is a circuit diagram of a power combining circuit of an on-chip transformer; the on-chip transformer 101 in fig. 1 includes 2 primary coils and a secondary coil Ls, the two primary coils are respectively denoted by Lp101 and Lp102, the parameters of the primary coils Lp101 and Lp102 are the same, and the turns ratio of the primary coil Ls to the secondary coil Ls is 1:2, so the on-chip transformer 101 shown in fig. 1 is a 2-by-1: 2 transformer, i.e., a 2 × 1:2 transformer; the input sections of the primary coils Lp101 and Lp102 are respectively connected with power input signals amplified by a Power Arrester (PA)102, the two power input signals are power-combined by an on-chip transformer 101 to provide power output signals, and the output end of the secondary coil Ls in fig. 1 is connected with a load RL.

As shown in fig. 2A, it is a layout of a power combining circuit based on an on-chip transformer in the prior art; FIG. 2B is a first exploded view of FIG. 2A; FIG. 2C is a second exploded view of FIG. 2A; fig. 2A mainly illustrates the layout of the corresponding on-chip transformer 101 in fig. 1, where coil 201 connects 2 turns of a layer to form secondary coil Ls shown in fig. 1, having two output ports labeled P3+ and P3 "; coil 202 connects the layer 1 annular turns to form primary coil Lp101 shown in fig. 1, with two corresponding output ports labeled P1+ and P1-; coil 203 connects the layer 1 annular turns to form primary coil Lp102 shown in fig. 1, with two corresponding output ports labeled P2+ and P2-. It can be seen that the major planar wires of the

coils

201, 202 and 203 are all located on the same layer of metal, and that the planar wires on the same plane are laterally offset from each other, the connection lines between the inner and outer turns of the coils are present in the areas corresponding to the

dashed boxes

204 and 205, and the vias and planar wires formed on the underlying metal layer are present in the areas of the

dashed boxes

204 and 205.

From fig. 2A, the sizes of the regions surrounded by the coil 201 and the

coils

202 and 203 are not completely overlapped, there is a deviation in the area of the surrounded region due to the lateral arrangement between the planar metal wires of the coils, and the region surrounded by the coil 201 and the

coils

202 and 203 is not overlapped may cause a certain magnetic flux leakage, which not only increases the area of the circuit, but also reduces the coupling factor between the secondary coil Ls and the primary coils Lp101 and Lp 102.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a power synthesis circuit based on an on-chip transformer, which can reduce the area of the circuit, improve the coupling factor between a primary coil and a secondary coil and improve the efficiency of the transformer.

In order to solve the above technical problem, the power combining circuit based on the on-chip transformer provided by the invention comprises:

the on-chip transformer comprises a plurality of primary coils and a secondary coil, wherein each primary coil inputs a power input signal, and the power input signals of the primary coils are combined in the secondary coil to form a power output signal.

The secondary coil forms a semiconductor substrate and is plane helical structure, the secondary coil includes first signal output end and second signal output end, the secondary coil comprises a plurality of loop that the planar wire of one deck encloses, the internal diameter of the loop of secondary coil reduces in proper order, each loop of secondary coil is provided with two subordinate's tie points or two higher level's tie points that correspond.

The first signal output end and the second signal output end are composed of two mutually disconnected superior connection points of the outermost annular turn of the secondary coil.

The connection structure of each annular turn of the secondary coil is as follows: when the current-level annular turn is provided with a lower-level annular turn, two lower-level connection points of the current-level annular turn are disconnected, two upper-level connection points of the lower-level annular turn are disconnected, a first lower-level connection point of the current-level annular turn is connected with a second upper-level connection point of the lower-level annular turn through the same layer of planar metal wire, and the second lower-level connection point of the current-level annular turn is connected with the first upper-level connection point of the lower-level annular turn through the through hole and the adjacent layer of planar metal wire; when the current level turn does not have a next level turn, the two next level connection points of the current level turn are connected together.

Each primary coil is also respectively composed of corresponding annular turns formed by winding the planar metal wire on the same layer, and the number of the annular turns of each primary coil is respectively smaller than that of the annular turns of the secondary coil; the metal level of the planar metal wire of the annular turn of each primary coil is higher or lower than the metal level of the planar metal wire of the annular turn of the corresponding secondary coil.

In the longitudinal direction, the planar wires of the loop turns of each primary coil and the corresponding planar wires of the loop turns of the secondary coil are completely aligned, and the completely aligned structure increases the coupling area of the primary coil and the secondary coil; the annular turns of the primary coils of the same layer have an overlapping region, in the overlapping region, the annular turns of the inner and outer rings of one primary coil are directly connected through the planar metal wire of the same layer, and the annular turns of the inner and outer rings of the other primary coil are connected through the through holes and the planar metal wire of the adjacent layer.

In a further improvement, the number of the primary coils is 2.

In a further improvement, the number of the loop turns of the secondary coil is 2, and the number of the loop turns of each of the primary coils is 1.

In a further refinement, the annular turn of the secondary coil is rectangular in shape.

In a further improvement, the outermost annular turn of the secondary coil comprises two superior connection points and two inferior connection points, and the innermost annular turn of the secondary coil comprises two superior connection points; the upper connection points of the outermost annular turns of the secondary coil are arranged on one side of the rectangle and the lower connection points are arranged on the other side of the rectangle.

In a further improvement, the annular turn of each primary coil is formed by half of the inner loop planar wire and half of the outer loop planar wire, the outer loop planar wire of the annular turn of each primary coil is aligned with a corresponding half of the outermost annular turn of the secondary coil, and the inner loop planar wire of the annular turn of each primary coil is aligned with a corresponding half of the innermost annular turn of the secondary coil.

In a further improvement, the annular turn of each primary coil includes a pair of superior connection points, and the pair of superior connection points of each primary coil are used as the corresponding first power input signal terminal and the second power signal input terminal.

In a further improvement, a pair of superior connection points of each of the primary coils is disposed on a corresponding rectangular side of the outer coil planar wire.

In a further improvement, the rectangular sides corresponding to a pair of superior connection points of each of the primary coils are different from the rectangular sides of the first and second signal output terminals of the secondary coil.

In a further improvement, corresponding rectangular sides of a pair of superior connecting points of the two primary coils are the same.

In a further improvement, the positions of the pair of upper connecting points of the two primary coils on the corresponding sides of the rectangle are different.

In a further improvement, the rectangular sides corresponding to a pair of superior connection points of the two primary coils are different.

In a further improvement, the on-chip transformer comprises 3 metal layers.

Each planar metal wire of each annular turn of the secondary coil is positioned on the third metal layer, and a part of the planar metal wire positioned on the second metal layer at the bottom is positioned at the connecting position of the front and rear annular turns.

Each planar wire of the loop turns of each primary coil is located on the second metal layer, and there is a portion of the planar wire located on the bottom first metal layer in the overlap region of the loop turns of each primary coil.

In a further improvement, the on-chip transformer comprises 4 metal layers.

Each planar wire of the loop turn of each primary coil is located on the second metal layer, and a portion of the planar wire located on the bottom first metal layer and a portion of the planar wire located on the 0 th metal layer are located on the bottom first metal layer in the overlap region of the loop turn of each primary coil.

In a further improvement, each of the power input signals is amplified by a power amplifier and then connected to a power signal input terminal of each of the primary coils.

The invention makes special arrangement for the structure of the planar metal wires corresponding to the primary coil and the secondary coil of the on-chip transformer, realizes the connection of the metal wires in the overlapping area by increasing the metal layers and arranging the through holes, can realize that the main body planar metal wires corresponding to the secondary coil are all placed on the same metal layer and the main body planar metal wires of the primary coil are all placed on the metal layers of other layers, such as the adjacent upper layer or the adjacent lower layer, and can completely align the planar metal wires of the annular turns of each primary coil and the planar metal wires of the annular turns of the corresponding secondary coil by the longitudinal arrangement of the upper metal layer and the lower metal layer, thus not only reducing the occupied area of the whole on-chip transformer, but also increasing the coupling area of the primary coil and the secondary coil simultaneously, thereby improving the coupling factor between the primary coil and the secondary coil, the efficiency of the transformer is improved.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

FIG. 1 is a circuit diagram of an on-chip transformer based power combining circuit;

FIG. 2A is a layout of a conventional on-chip transformer-based power combining circuit;

FIG. 2B is a first exploded view of FIG. 2A;

FIG. 2C is a second exploded view of FIG. 2A;

FIG. 3A is a layout of a power combining circuit based on an on-chip transformer according to a first embodiment of the present invention;

FIG. 3B is a first exploded view of FIG. 3A;

FIG. 3C is a second exploded view of FIG. 3A;

FIG. 4A is a perspective view of the layout corresponding to FIG. 3A;

FIG. 4B is a first exploded view of FIG. 4A;

FIG. 4C is a second exploded view of FIG. 4A;

FIG. 5A is a layout of a power combining circuit based on an on-chip transformer according to a second embodiment of the present invention;

FIG. 5B is a first exploded view of FIG. 5A;

FIG. 5C is a second exploded view of FIG. 5A;

FIG. 6A is a perspective view of the layout corresponding to FIG. 5A;

FIG. 6B is a first exploded view of FIG. 6A;

FIG. 6C is a second exploded view of FIG. 6A;

fig. 7 is a simulation plot of transformer efficiency and frequency for a second embodiment of the present invention.

Detailed Description

As shown in fig. 3A, it is a layout of a power combining circuit based on an on-chip transformer 101 according to a first embodiment of the present invention; FIG. 3B is a first exploded view of FIG. 3A; FIG. 3C is a second exploded view of FIG. 3A; FIG. 4A is a perspective view of the layout corresponding to FIG. 3A; FIG. 4B is a first exploded view of FIG. 4A; FIG. 4C is a second exploded view of FIG. 4A; referring to fig. 1, a circuit diagram corresponding to a power combining circuit based on an on-chip transformer 101 according to a first embodiment of the present invention is shown, where the on-chip transformer 101 has a 2 × 1:2 structure, each of the power input signals is amplified by a power amplifier 102 and then connected to a power signal input end of each of the primary coils Lp101 and Lp102, the two power input signals are power combined by the on-chip transformer 101 to provide a power output signal, and an output end of a secondary coil Ls in fig. 1 is connected to a load RL.

The power synthesis circuit based on the on-chip transformer 101 according to the first embodiment of the present invention includes:

an on-chip transformer 101 composed of a plurality of primary coils and one secondary coil 301; one power input signal is input to each of the primary coils, and the power input signals of the plurality of primary coils are combined in the secondary coil 301 to form one power output signal.

The secondary coil 301 is formed on a semiconductor substrate and has a planar spiral structure, and the secondary coil 301 is composed of a plurality of annular turns formed by winding planar metal wires on the same layer. The inner diameters of the annular turns of the secondary coil 301 are sequentially reduced, and each annular turn of the secondary coil 301 is provided with two corresponding lower-level connection points or two corresponding upper-level connection points.

The first signal output terminal S + and the second signal output terminal S-are composed of two mutually disconnected upper connection points of the outermost annular turn of the secondary coil 301.

The connection structure of each annular turn of the secondary coil 301 is as follows: when the current-level annular turn is provided with a lower-level annular turn, two lower-level connection points of the current-level annular turn are disconnected, two upper-level connection points of the lower-level annular turn are disconnected, a first lower-level connection point of the current-level annular turn is connected with a second upper-level connection point of the lower-level annular turn through a same layer of planar metal wire, the second lower-level connection point of the current-level annular turn is connected with the first upper-level connection point of the lower-level annular turn through a through hole and an adjacent layer of planar metal wire, and the adjacent layer of planar metal wire can be an adjacent upper layer or a lower layer or an adjacent upper layer or a lower layer and needs to be set according to actual conditions; when the current level turn does not have a next level turn, the two next level connection points of the current level turn are connected together. That is, when the previous-stage loop turn has a next-stage loop turn, the previous-stage loop turn is connected to two previous-stage connection points of the next-stage loop turn through the two next-stage connection points, so that an overlap region exists, and a connection structure of a through hole and a planar metal wire of an adjacent layer is added to avoid a short circuit in the overlap region.

Each primary coil is also respectively composed of corresponding annular turns formed by winding the planar metal wire on the same layer, and the number of the annular turns of each primary coil is respectively smaller than that of the annular turns of the secondary coil 301; the metal level of the planar metal wire of the loop turn of each primary coil is higher or lower than the metal layer of the planar metal wire of the corresponding loop turn of the secondary coil 301, that is, the metal level of the planar metal wire of the loop turn of the primary coil is placed above or below the metal layer of the planar metal wire of the loop turn of the secondary coil 301, and the arrangement of different metal levels can ensure that the planar metal wire of the loop turn of each primary coil described later is completely aligned with the planar metal wire of the loop turn of the corresponding secondary coil 301.

In the longitudinal direction, the planar wires of the annular turns of each primary coil are perfectly aligned with the corresponding planar wires of the annular turns of the secondary coil 301, the perfectly aligned structure providing an increased coupling area of the primary coil and the secondary coil 301; the annular turns of the primary coils on the same layer are provided with an overlapping area, in the overlapping area, the annular turns of the inner and outer rings of one primary coil are directly connected through the planar metal wire on the same layer, the annular turns of the inner and outer rings of the other primary coil are connected with the planar metal wire of the adjacent layer through the through holes, and the planar metal wire of the adjacent layer connected with the through holes can be the adjacent upper layer or the adjacent lower layer, and can also be the adjacent upper layer or the adjacent lower layer, and the arrangement is required according to the actual situation.

In a first embodiment of the invention, the primary coil of fig. 3A includes two primary coils, which are respectively designated by

reference numerals

302 and 303 and which respectively correspond to the primary coils Lp101 and Lp102 of fig. 1; secondary winding 301 corresponds to secondary winding Ls in fig. 1. In the first embodiment of the present invention, the power output signal and the power input signal are both differential signals, and there are two corresponding ports, for example, the ports of the power output signal are S + and S-respectively, i.e. the subsequent first signal output terminal S + and the second signal output terminal S-, the ports of the power input signal of the primary coil 302 are P1+ and P1-, and the ports of the power input signal of the primary coil 303 are P2+ and P2-.

The number of the loop turns of the secondary coil 301 is 2, and the number of the loop turns of each of the primary coils is 1.

The shape around which the annular turns of the secondary coil 301 are wrapped is rectangular.

The outermost annular turn of the secondary coil 301 comprises two superior connection points and two inferior connection points, and the outermost annular turn of the secondary coil 301 comprises two superior connection points corresponding to the first signal output terminal S + and the second signal output terminal S-; the outermost two lower connection points of the secondary coil 301 are located at the position of the broken line 304. The innermost annular turn of the secondary coil 301 comprises two superior connection points. The two upper level connection points of the innermost loop turn of the secondary coil 301 are located at the position of the dashed line 304. Each superior connection point of the outermost loop turn of the secondary coil 301 is disposed on one side of the rectangle and each inferior connection point is disposed on the other side of the rectangle, and the two sides in fig. 3A are two parallel sides of the rectangle.

The annular turn of each primary coil is formed by winding half of the inner ring plane wire and half of the outer ring plane wire, the outer ring plane wire of the annular turn of each primary coil is aligned with the corresponding half of the outermost annular turn of the secondary coil 301, and the inner ring plane wire of the annular turn of each primary coil is aligned with the corresponding half of the innermost annular turn of the secondary coil 301. Reference may be made in detail to the layout of the

primary coils

302 and 303 shown in fig. 3B.

The annular turn of each primary coil comprises a pair of superior connection points, and the pair of superior connection points of each primary coil are used as a corresponding first power input signal end and a corresponding second power signal input end. The first and second power signal input terminals correspond to ports P1+ and P1-of the power input signal of the primary coil 302 and ports P2+ and P2-of the power input signal of the primary coil 303.

And a pair of upper-stage connecting points of each primary coil are arranged on the corresponding rectangular edge of the outer ring plane metal wire.

The rectangular sides corresponding to a pair of upper connection points of each primary coil are different from the rectangular sides of the first signal output terminal S + and the second signal output terminal S-of the secondary coil 301. And the corresponding rectangular sides of the pair of superior connecting points of the two primary coils are the same. The positions of a pair of upper-stage connecting points of the two primary coils on the corresponding sides of the rectangle are different. As shown in fig. 3A, the upper connection points of the

primary coils

302 and 303 are disposed on the corresponding rectangular sides of the dashed box 304.

The on-chip transformer 101 comprises 4 metal layers.

Referring to the corresponding perspective views of fig. 4A to 4C, the planar wires of the annular turns of the secondary winding 301 are located on the third metal layer, and a part of the planar wires located on the second metal layer at the bottom is located at the connection position of the front and rear annular turns. As can be seen from fig. 4C, there are portions of the secondary winding 301 that need to be cross-connected between 2 annular turns at the positions corresponding to the dashed boxes 304, where one connection is realized by the planar wire 301a of the same layer, the other connection is realized by the through hole 3061 and the planar wire 301b of the bottom layer, and the cross-connection of the outer and inner turns of the annular turns is realized by the

planar wires

301a and 301 b.

Each planar wire of the loop turn of each primary coil is located on the second metal layer, and a portion of the planar wire located on the bottom first metal layer and a portion of the planar wire located on the 0 th metal layer are located on the bottom first metal layer in the overlap region of the loop turn of each primary coil. As can be seen from fig. 4B, the

primary coils

302 and 303 are located on the second metal layer, and cross-connection needs to be implemented at the positions corresponding to the dashed

boxes

304 and 305. In dashed box 304, the primary coil 302 is connected at the intersection location by via 3062 and planar metal line 302a on the first level metal layer; in the dashed box 305, the primary coil 302 is connected at the crossing location by a planar metal line 302b on the second metal layer. In dashed box 304, the primary coil 303 is connected at the intersection by

vias

3062 and 3063 and planar metal line 303a on layer 0 metal layer; in the dashed box 305, the primary coil 303 is connected at the intersection by a via 3062 and a planar metal line 303b on the first level metal layer. As can be seen from fig. 4A, at the dashed box 304, there are 4 layers of metal, and three layers of through holes are needed in the longitudinal direction, namely through

holes

3061, 3062, and 3063, respectively.

As can be seen from comparing fig. 2A and fig. 3A, the primary coil and the secondary coil of the first embodiment of the present invention are completely overlapped in the transverse direction, which not only saves the area, but also increases the coupling between the primary coil and the secondary coil and reduces the leakage of the magnetic flux; for the on-chip structure, all elements in the circuit are integrated on the same chip, so that the cost of the chip of the on-chip structure can be reduced after the area is reduced; increasing the coupling between the primary and secondary windings and reducing the leakage of magnetic flux increases the efficiency of the transformer.

As shown in fig. 5A, it is a layout of a power combining circuit based on an on-chip transformer 101 according to a second embodiment of the present invention; FIG. 5B is a first exploded view of FIG. 5A; FIG. 5C is a second exploded view of FIG. 5A; FIG. 6A is a perspective view of the layout corresponding to FIG. 5A; FIG. 6B is a first exploded view of FIG. 6A; FIG. 6C is a second exploded view of FIG. 6A; referring to fig. 1, a circuit diagram corresponding to a power combining circuit based on an on-chip transformer 101 according to a second embodiment of the present invention is shown, where the on-chip transformer 101 has a 2 × 1:2 structure, each of the power input signals is amplified by a power amplifier 102 and then connected to a power signal input end of each of the primary coils Lp101 and Lp102, the two power input signals are power combined by the on-chip transformer 101 to provide a power output signal, and an output end of a secondary coil Ls in fig. 1 is connected to a load RL.

The second embodiment of the present invention is a power combining circuit based on an on-chip transformer 101, including:

an on-chip transformer 101 composed of a plurality of primary coils and one secondary coil 401; one power input signal is input to each of the primary coils, and the power input signals of the plurality of primary coils are combined in the secondary coil 401 to form one power output signal.

The secondary coil 401 forms a semiconductor substrate and is in a planar spiral structure, and the secondary coil 401 is composed of annular turns formed by a plurality of planar metal wires on the same layer in a surrounding mode. The inner diameters of the annular turns of the secondary coil 401 are sequentially reduced, and each annular turn of the secondary coil 401 is provided with two corresponding lower-level connection points or two corresponding upper-level connection points.

The first signal output terminal S + and the second signal output terminal S-are composed of two mutually disconnected upper connection points of the outermost annular turn of the secondary coil 401.

The connection structure of each annular turn of the secondary coil 401 is as follows: when the current-level annular turn is provided with a lower-level annular turn, two lower-level connection points of the current-level annular turn are disconnected, two upper-level connection points of the lower-level annular turn are disconnected, a first lower-level connection point of the current-level annular turn is connected with a second upper-level connection point of the lower-level annular turn through the same layer of planar metal wire, and the second lower-level connection point of the current-level annular turn is connected with the first upper-level connection point of the lower-level annular turn through the through hole and the lower layer of planar metal wire; when the current level turn does not have a next level turn, the two next level connection points of the current level turn are connected together.

Each primary coil is also respectively composed of corresponding annular turns formed by winding the planar metal wire on the same layer, and the number of the annular turns of each primary coil is respectively smaller than that of the annular turns of the secondary coil 401; the metal level of the planar metal wire of the loop turn of each primary coil is lower than the metal level of the planar metal wire of the corresponding loop turn of the secondary coil 401.

In the longitudinal direction, the planar wires of the loop turns of each primary coil and the corresponding planar wires of the loop turns of the secondary coil 401 are perfectly aligned, and the perfectly aligned structure increases the coupling area of the primary coil and the secondary coil 401; the annular turns of the primary coils on the same layer are provided with an overlapping area, in the overlapping area, the annular turns of the inner and outer rings of one primary coil are directly connected through the planar metal wire on the same layer, and the annular turns of the inner and outer rings of the other primary coil are connected through the through holes and the planar metal wire on the bottom layer.

In a second embodiment of the invention, the primary coil of fig. 5A includes two coils, which are respectively labeled with

reference numbers

402 and 403 and respectively correspond to the primary coils Lp101 and Lp102 of fig. 1; secondary coil 401 corresponds to secondary coil Ls in fig. 1. In the second embodiment of the present invention, the power output signal and the power input signal are both differential signals, and there are two corresponding ports, for example, the ports of the power output signal are S + and S-respectively, i.e. the subsequent first signal output terminal S + and the second signal output terminal S-, the ports of the power input signal of the primary coil 402 are P1+ and P1-, and the ports of the power input signal of the primary coil 403 are P2+ and P2-.

The number of the loop turns of the secondary coil 401 is 2, and the number of the loop turns of each of the primary coils is 1.

The shape of the annular turn of the secondary coil 401 is rectangular.

The outermost annular turn of the secondary coil 401 includes two superior connection points and two inferior connection points, and the outermost annular turn of the secondary coil 401 includes two superior connection points corresponding to the first signal output terminal S + and the second signal output terminal S-; the outermost two inferior connection points of the secondary coil 401 are located at the position of the dashed line 404. The innermost annular turn of the secondary coil 401 comprises two superior connection points. The two upper level connection points of the innermost loop turn of the secondary coil 401 are located at the position of the dashed line 404. Each superior connection point of the outermost loop turn of the secondary coil 401 is disposed on one side of the rectangle and each inferior connection point is disposed on the other side of the rectangle, and the two sides in fig. 5A are two parallel sides of the rectangle.

The annular turn of each primary coil is formed by winding half of the inner ring plane wire and half of the outer ring plane wire, the outer ring plane wire of the annular turn of each primary coil is aligned with the corresponding half of the outermost annular turn of the secondary coil 401, and the inner ring plane wire of the annular turn of each primary coil is aligned with the corresponding half of the innermost annular turn of the secondary coil 401. Reference may be made in detail to the layout of the

primary coils

402 and 403 shown in fig. 5B.

The annular turn of each primary coil comprises a pair of superior connection points, and the pair of superior connection points of each primary coil are used as a corresponding first power input signal end and a corresponding second power signal input end. The first and second power signal inputs correspond to ports P1+ and P1-of the power input signal of primary coil 402 and ports P2+ and P2-of the power input signal of primary coil 403.

The rectangular sides corresponding to a pair of upper connection points of each primary coil are different from the rectangular sides of the first signal output terminal S + and the second signal output terminal S-of the secondary coil 401. The rectangular sides corresponding to a pair of superior connection points of the two primary coils are different. As shown in fig. 5A, the upper connection points of the primary winding 402, i.e., the ports P1+ and P1-, are disposed on the corresponding rectangular sides of the dashed box 404; as shown in fig. 5B, the upper connection points of the primary winding 403, i.e., the ports P2+ and P2-, are disposed on the corresponding rectangular sides of the dashed box 406.

The on-chip transformer 101 comprises 3 metal layers.

Referring to the corresponding perspective views of fig. 6A to 6C, the planar wires of the annular turns of the secondary coil 401 are located on the third metal layer, and a part of the planar wires located on the second metal layer at the bottom is located at the connection position of the front and rear annular turns. As can be seen from fig. 6C, there are portions to be cross-connected between 2 annular turns of the secondary winding 401 at positions corresponding to the dashed boxes 404, where one connection is realized by the planar metal wire 401a of the same layer, the other connection is realized by the via 3071 and the planar metal wire 401b of the bottom layer, and the cross-connection of the outer and inner turns of the annular turns is realized by the

planar metal wires

401a and 401 b.

Each planar wire of the loop turns of each primary coil is located on the second metal layer, and there is a portion of the planar wire located on the bottom first metal layer in the overlap region of the loop turns of each primary coil. As can be seen from fig. 6B, the

primary coils

402 and 403 are both located on the second metal layer, and cross-connection needs to be implemented at the positions corresponding to the dashed

boxes

404 and 405. In a dashed box 404, the primary coil 402 is connected at the crossing location by a via 3072 and a planar metal line 402a on the first metal layer; in the dashed box 405, the primary coil 402 is connected at the crossing location by a planar metal line 402b on the second metal layer. In a dashed box 404, the primary coil 403 is connected at the crossing location by a via 4072 and a planar metal line 403a on the first metal layer; in the dashed box 405, the primary coil 403 is connected at the crossing position by a via 4072 and a planar metal line 403b on the first metal layer. As can be seen in fig. 6A, at dashed box 404, there are 3 layers of metal, and two layers of vias are needed in the longitudinal direction,

vias

4071 and 4072, respectively.

As can be seen from comparing fig. 2A and fig. 5A, the primary coil and the secondary coil of the second embodiment of the present invention are completely overlapped in the transverse direction, which not only saves the area, but also increases the coupling between the primary coil and the secondary coil and reduces the leakage of the magnetic flux; for the on-chip structure, all elements in the circuit are integrated on the same chip, so that the cost of the chip of the on-chip structure can be reduced after the area is reduced; increasing the coupling between the primary and secondary windings and reducing the leakage of magnetic flux increases the efficiency of the transformer.

Watch 1

As shown in table one, in order to compare the simulation results of the conventional device corresponding to fig. 2A and the device according to the second embodiment of the present invention corresponding to fig. 5A under the power signal with a plane of 1.8GHz, it can be seen that the quality factor of the device according to the second embodiment of the present invention is improved; the actual turn ratio is the actual effective turn ratio, and it can be seen that the actual turn ratio of the second embodiment of the present invention is also improved, the area is reduced, the mutual inductance is enhanced, and the coupling coefficient and the transformer efficiency are improved.

As shown in fig. 7, it is a simulation curve of the efficiency and frequency of the transformer according to the second embodiment of the present invention, and the curve 401 is a simulation curve of the efficiency and frequency of the transformer according to the second embodiment of the present invention; fig. 7 also shows a simulation curve 402 of the transformer efficiency and the frequency of the conventional device corresponding to fig. 2A, and it can be seen that the transformer device of the second embodiment of the present invention has higher efficiency than the conventional device under various frequency conditions.

The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims

1. A power combining circuit based on an on-chip transformer, comprising:

the on-chip transformer comprises a plurality of primary coils and a secondary coil, wherein each primary coil inputs a power input signal, and the power input signals of the primary coils are combined in the secondary coil to form a power output signal;

the secondary coil forms a semiconductor substrate and is of a planar spiral structure, the secondary coil comprises a first signal output end and a second signal output end, the secondary coil is composed of annular turns formed by surrounding a plurality of planar metal wires on the same layer, the inner diameters of the annular turns of the secondary coil are sequentially reduced, and each annular turn of the secondary coil is provided with two corresponding lower-level connection points or two corresponding upper-level connection points;

the first signal output end and the second signal output end are composed of two mutually disconnected superior connection points of the annular turn at the outermost side of the secondary coil;

the connection structure of each annular turn of the secondary coil is as follows: when the current-level annular turn is provided with a lower-level annular turn, two lower-level connection points of the current-level annular turn are disconnected, two upper-level connection points of the lower-level annular turn are disconnected, a first lower-level connection point of the current-level annular turn is connected with a second upper-level connection point of the lower-level annular turn through the same layer of planar metal wire, and the second lower-level connection point of the current-level annular turn is connected with the first upper-level connection point of the lower-level annular turn through the through hole and the adjacent layer of planar metal wire; when the current-stage annular turn does not have a lower-stage annular turn, two lower-stage connection points of the current-stage annular turn are connected together;

each primary coil is also respectively composed of corresponding annular turns formed by winding the planar metal wire on the same layer, and the number of the annular turns of each primary coil is respectively smaller than that of the annular turns of the secondary coil; the metal level of the planar metal wire of the annular turn of each primary coil is higher or lower than that of the planar metal wire of the annular turn of the corresponding secondary coil;

2. The on-chip transformer based power combining circuit of claim 1, wherein: the number of the primary coils is 2.

3. The on-chip transformer based power combining circuit of claim 2, wherein: the number of the loop turns of the secondary coil is 2, and the number of the loop turns of each primary coil is 1.

4. The on-chip transformer based power combining circuit of claim 3, wherein: the shape of the annular turn of the secondary coil is rectangular.

5. The on-chip transformer based power combining circuit of claim 4, wherein: the outermost annular turn of the secondary coil comprises two superior connection points and two inferior connection points, and the innermost annular turn of the secondary coil comprises two superior connection points; the upper connection points of the outermost annular turns of the secondary coil are arranged on one side of the rectangle and the lower connection points are arranged on the other side of the rectangle.

6. The on-chip transformer based power combining circuit of claim 5, wherein: the annular turn of each primary coil is formed by winding half of the inner ring plane metal wire and half of the outer ring plane metal wire, the outer ring plane metal wire of the annular turn of each primary coil is aligned with the corresponding half turn of the outermost annular turn of the secondary coil, and the inner ring plane metal wire of the annular turn of each primary coil is aligned with the corresponding half turn of the innermost annular turn of the secondary coil.

7. The on-chip transformer based power combining circuit of claim 6, wherein: the annular turn of each primary coil comprises a pair of superior connection points, and the pair of superior connection points of each primary coil are used as a corresponding first power input signal end and a corresponding second power signal input end.

8. The on-chip transformer based power combining circuit of claim 7, wherein: and a pair of upper-stage connecting points of each primary coil are arranged on the corresponding rectangular edge of the outer ring plane metal wire.

9. The on-chip transformer based power combining circuit of claim 8, wherein: the rectangular sides corresponding to a pair of superior connection points of each of the primary coils are different from the rectangular sides of the first signal output terminal and the second signal output terminal of the secondary coil.

10. The on-chip transformer based power combining circuit of claim 9, wherein: and the corresponding rectangular sides of the pair of superior connecting points of the two primary coils are the same.

11. The on-chip transformer based power combining circuit of claim 10, wherein: the positions of a pair of upper-stage connecting points of the two primary coils on the corresponding sides of the rectangle are different.

12. The on-chip transformer based power combining circuit of claim 9, wherein: the rectangular sides corresponding to a pair of superior connection points of the two primary coils are different.

13. The on-chip transformer based power combining circuit of claim 3, wherein: the on-chip transformer comprises 3 metal layers;

each plane metal wire of each annular turn of the secondary coil is positioned on the third metal layer, and a part of plane metal wire positioned on the second metal layer at the bottom is arranged at the connecting position of the front and rear annular turns;

14. The on-chip transformer based power combining circuit of claim 3, wherein: the on-chip transformer comprises 4 metal layers;

15. The on-chip transformer based power combining circuit of claim 1, wherein: each power input signal is amplified by a power amplifier and then connected to a power signal input end of each primary coil.