CN108267697A - A kind of bank base power supply output transient state monitoring system for water quality online observation net - Google Patents

A kind of bank base power supply output transient state monitoring system for water quality online observation net Download PDF

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Publication number
CN108267697A
CN108267697A CN201810193779.1A CN201810193779A CN108267697A CN 108267697 A CN108267697 A CN 108267697A CN 201810193779 A CN201810193779 A CN 201810193779A CN 108267697 A CN108267697 A CN 108267697A
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China
Prior art keywords
power supply
water quality
monitoring system
supply output
transient state
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CN201810193779.1A
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Chinese (zh)
Inventor
金波
高柳
杨灿军
李德骏
陈燕虎
张锋
张志峰
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Zhongtian Technology Marine Systems Co ltd
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Zhejiang University ZJU
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Priority to CN201810193779.1A priority Critical patent/CN108267697A/en
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/40Testing power supplies

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Remote Monitoring And Control Of Power-Distribution Networks (AREA)

Abstract

The invention discloses a kind of bank base power supply output transient state monitoring system for water quality online observation net, including front-end sampling module, AD conversion module, FPGA, SDRAM, MCU, communication module and host computer;The output voltage and electric current of front-end sampling module opposite bank reference power supply are sampled and are improved, and are then input to AD conversion module;AD conversion module is input to FPGA after sampled signal is converted to digital signal;FPGA the digital signal of input is carried out it is abnormal in real time judge, and by data buffer storage to SDRAM, when FPGA have found input signal exception, the data before and after the abnormal point of the caching in SDRAM are read, are sent to MCU;MCU sends data to host computer by communication module.Using the present invention, can the functions such as fault warning, fault in-situ reservation and failure reason analysis be realized with opposite bank reference power supply progress monitoring in real time at a high speed.

Description

A kind of bank base power supply output transient state monitoring system for water quality online observation net
Technical field
The invention belongs to power supply transient state monitoring field more particularly to a kind of bank base power supply for water quality online observation net are defeated Go out transient state monitoring system.
Background technology
Water quality online observation net is a kind of water quality monitoring mode emerging in recent years, it be by submarine observation network development and The methods of coming, distinguishing traditional water quality monitoring technology such as manual sampling detection, buoy water quality monitoring station, by " bank base station- The structure of optoelectronic composite cable-box-water quality sensor of plugging under water " is realized to the long-term, real-time of water quality, in-situ monitoring.Water quality Online observation host's body portion is run under water, easily by various damages, such as fisherman's operation damages optoelectronic composite cable and plugs into Box, underwater equipment seal failure, the water inlet of equipment humidity etc..Since underwater equipment maintenance and maintenance are not easy, it is therefore desirable to which failure is examined It is monitored disconnected system in real time and accident analysis, so as to the positioning failure reason after failure occurs, formulates scientific and reasonable Maintenance program, and improved for failure cause making.
Monitoring can effectively find failure and analyzing failure cause to the high speed of opposite bank reference power supply output voltage and electric current in real time.It is existing The voltage and current monitoring mode for having water quality online observation net opposite bank reference power supply is that periodical low speed monitors, and measurement such as per second is primary Voltage and current value, this monitoring mode can not capture submerged cable or moment caused by box short circuit of plugging into is vibrated, it is impossible to identify Failure is to be caused by bank base power supply or caused by submerged cable or box short circuit of plugging into, can not the intact retention fault moment bank Reference power supply exports transient waveform, is analyzed for subsequent artefacts.
Invention content
The present invention provides a kind of bank base power supply output transient state monitoring system for water quality online observation net, opposite bank reference power supply Progress monitoring in real time at a high speed, realizes the functions such as fault warning, fault in-situ reservation and failure reason analysis.
A kind of bank base power supply output transient state monitoring system for water quality online observation net, including front-end sampling module, AD Modular converter, FPGA, SDRAM, MCU, communication module and host computer;The output voltage of the front-end sampling module opposite bank reference power supply It is sampled and is improved with electric current, be then input to AD conversion module;Sampled signal is converted to number by the AD conversion module FPGA is input to after signal;The FPGA carries out abnormal judgement, and by data buffer storage extremely in real time to the digital signal of input SDRAM when FPGA has found input signal exception, the data before and after the abnormal point of the caching in SDRAM is read, are sent to MCU;The MCU sends data to host computer by communication module.
It is realized preferably, the voltage sample of front-end sampling module is divided by parallel resistance, current sample is sampled by series connection Resistance realizes that rear end increases RC filter circuits, half of the filter cutoff frequency for sample frequency or so, can not completely be adopted to filter out The high-frequency signal of sample.
Preferably, the conversion frequency of the AD conversion module is not less than 50MSPS.When short trouble occurs under water, foot Enough high sample frequencys can just collect the concussion waveform of short-circuit moment Microsecond grade.
Preferably, the abnormal judgement includes:Whether judge voltage, electric current, voltage change ratio and current changing rate In normal range (NR).For abnormal determination, Exception Type includes that over-pressed, under-voltage, overcurrent, voltage change ratio be excessive and current changing rate Excessive 5 type.For under-voltage, power on and lower electric process can trigger under-voltage exception, thus can record power on and under The Wave data of electricity;It is excessive excessive with current changing rate for voltage change ratio, show submerged cable or box of plugging into has occurred Short trouble causes instantaneous electricity to vibrate.
Preferably, SDRAM's is respectively buffered when being buffered in write-in and reading by an asynchronous FIFO.Write-in buffering FIFO is used to adjust sample frequency and SDRAM write frequencies are inconsistent, and playback buffer FIFO is used to adjust MCU read data rates It is inconsistent with SDRAM read frequencies.Asynchronous FIFO inside FGPA by logic by being generated.Preferably, SDRAM is using cycle The cache way of write-in, i.e., last address continue to be written from first address after writing, and are all newest to keep all data in SDRAM 's.And it is written and read by the way of writing by page and being read by page, to improve the read-write efficiency of SDRAM.
Preferably, MCU uses STM32 series monolithics, adopting for FPGA transmissions is read by included FSMC controllers Sample data.
Preferably, MCU is communicated with host computer by the way of high speed USB 2.0 or 100 m ethernet, a large amount of numbers are realized According to fast and reliable transmission.
Preferably, MCU sets the parameter of abnormal determination by serial ports to FPGA, FPGA is sent different by serial ports to MCU Normal type.
Preferably, when FPGA is not detected abnormal, MCU periodically reads current sample magnitude, and is sent to Host computer, the data of reading are transmitted by parallel data channels.
Preferably, MCU and FPGA subsidiary communications in a manner that I/O port is connected directly.MCU exports low and high level to show Meaning FPGA oneself needs to read the unusual waveforms data cached in present sample numerical value or SDRAM;FPGA passes through another I/O port Send whether low and high level signal MCU oneself detects exception.
Preferably, when host computer receives abnormal, event is made according to Exception Type and abnormal front and rear voltage and current numerical value Hinder type to judge.When voltage change ratio or excessive current changing rate, show that short trouble occurs under water causes bank base power supply defeated Go out concussion;When Exception Type is under-voltage, abnormal preceding voltage is 0 or close to 0, and voltage is operating voltage after exception, then shows bank Reference power supply powers on;When Exception Type is under-voltage, abnormal preceding voltage is operating voltage, and voltage is 0 or close to 0 after exception, shows bank Electricity or the power down when abnormal electrical power supply, humidity are when reasons self-protection under reference power supply.
The present invention by carrying out real-time high speed detection to the bank base power supply of water quality online observation net, identification output voltage and The abnormal conditions of electric current are analyzed failure cause, and retain exception according to Exception Type and abnormal front and rear output numerical value The Wave data at moment, so as to effectively differentiate underwater short trouble and bank base power supply faults itself and retention fault moment Wave data, for manually being analysed in depth.
Description of the drawings
Fig. 1 is bank base power failure diagnosing system module partition of the present invention and flow diagram;
Fig. 2 is the caching of data of the present invention and abnormal determination process flow schematic diagram.
Specific embodiment
In order to more specifically describe the present invention, below in conjunction with the accompanying drawings and specific embodiment is to technical scheme of the present invention It is described in detail.
As shown in Figure 1, a kind of bank base power supply output transient state monitoring system for water quality online observation net, is adopted including front end Egf block, AD conversion module, FPGA, SDRAM, MCU, communication module and host computer.
Front-end sampling module, voltage sample are divided by parallel resistance and realized, current sample is realized by series connection sampling resistor, Rear end increases RC filter circuits, and filter cutoff frequency is the half of sample frequency.AD conversion module is using AD9226 as digital-to-analogue Converter, sample rate 65MSPS.Add circuit is built before signal input by amplifier to boost to signal, to meet input Area requirement.
The result of AD conversion is input to FPGA, copies as the processing of 3 tunnels, and the first via is input to SDRAM and caches and (need to first pass through FIFO is buffered), the second tunnel enters abnormal determination module and does abnormal determination, third road deposit register, and MCU reads current sample values Shi Ze sends the data by parallel communication interface.
SDRAM cachings are buffered using double-FIFO, that is, respectively there are one FIFO when being written and reading to buffer, and is denoted as Input FIFO and Output FIFO.Data are read in from A/D module with the rate of 65MHz, and Input equally is written with the rate of 65MHz FIFO.It is 133MHz always from the Input FIFO rates read and the rate of write-in SDRAM.When data are read, from SDRAM Output FIFO are read out to the rate of 133MHz, Output FIFO are read again for MCU.
The processing procedure of FPGA and SDRAM module is as shown in Fig. 2, the data buffer storage mode of SDRAM is write for recurrent wrIting It to the last one address, comes back to initial address and continues to write to, be newest forever to keep data cached.Sentence when extremely After cover half block notes abnormalities, note abnormal point is A, continues that data are written into sampling and SDRAM at this time, writing reaches 3/ Stop write-in during 4SDRAM total capacities, remember that it is B to stop write-in point, then A to B is the data after abnormal point at this time, and B to A is different The often data before point.Then data are read since B points to upload, read and terminate when coming back to B, it is complete before and after abnormal point Data are all read.
MCU uses STM32 series monolithics, and the sampled data of FPGA transmissions is read by included FSMC controllers;It is logical It crosses serial ports and sends critical parameter to the abnormal determination module of FPGA;Sending low and high level by I/O port illustrates FPGA oneself to need to read What is taken is data cached in present sample data or SDRAM.When FPGA is not detected abnormal, MCU, which is periodically read, to be worked as Preceding sample magnitude, and send supreme position machine.When FPGA detects abnormal, MCU readings are cached in before and after the abnormal point in SDRAM Data, and send supreme position machine.
The characteristics of TCP transmission that MCU is communicated with host computer using high speed USB 2.0 or 100 m ethernet, the two is transmission Reliably, speed is fast, is easily achieved.Usb communication or TCP communication all have the function of checksum error re-transmission first, ensure reliable Property;Both in addition rate is all than very fast, and for 2.0 Theoretical Rate of high speed USB up to 60MByte/s, 100 m ethernet rate is reachable 12.5MByte/s;Both last communication protocol has corresponding library file, is easy to realize on MCU, and on most of computer All there is such interface, it is easy to use.
The parameter of abnormal determination is sent to slave computer by host computer, including maximum operation voltage, minium operation voltage, work Upper current limit, the voltage change ratio upper limit, the current changing rate upper limit, non-maximum operation voltage, non-operating current upper limit etc..In FPGA Abnormal determination module when detecting that voltage and current is below non-maximum operation voltage and the non-operating current upper limit, be determined as not Work, not as exception.When voltage or electric current or the change rate of the two exceed setting range, then it is determined as exception, passes through string Mouth sends Exception Type, and uploads the Wave data near abnormal point.Host computer is according to Exception Type and abnormal front and rear voltage Current values make fault type judgement, and send out corresponding prompting or alarm.

Claims (8)

1. a kind of bank base power supply output transient state monitoring system for water quality online observation net, which is characterized in that adopted including front end Egf block, AD conversion module, FPGA, SDRAM, MCU, communication module and host computer;The front-end sampling module opposite bank reference power supply Output voltage and electric current sampled and improved, be then input to AD conversion module;The AD conversion module is by sampled signal FPGA is input to after being converted to digital signal;The FPGA carries out the digital signal of input abnormal in real time to judge, and by data Caching when FPGA has found input signal exception, the data before and after the abnormal point of the caching in SDRAM is read, hair to SDRAM It send to MCU;The MCU sends data to host computer by communication module.
2. the bank base power supply output transient state monitoring system according to claim 1 for water quality online observation net, feature It is, the front-end sampling module, voltage sample is divided by parallel resistance and realized, current sample is by series connection sampling resistor reality Existing, rear end increases RC filter circuits, and filter cutoff frequency is the half of sample frequency.
3. the bank base power supply output transient state monitoring system according to claim 1 for water quality online observation net, feature It is, the conversion frequency of the AD conversion module is not less than 50MSPS.
4. the bank base power supply output transient state monitoring system according to claim 1 for water quality online observation net, feature It is, the abnormal judgement includes:Judge voltage, electric current, voltage change ratio and current changing rate whether in normal range (NR).
5. the bank base power supply output transient state monitoring system according to claim 1 for water quality online observation net, feature Be, the SDRAM be buffered in write-in and read when respectively buffered by an asynchronous FIFO, asynchronous FIFO by FGPA inside It is generated by logic.
6. the bank base power supply output transient state monitoring system according to claim 1 for water quality online observation net, feature It is, the SDRAM uses the cache way of recurrent wrIting.
7. the bank base power supply output transient state monitoring system according to claim 1 for water quality online observation net, feature It is, the MCU is communicated with the host computer by the way of high speed USB 2.0 or 100 m ethernet.
8. the bank base power supply output transient state monitoring system according to claim 1 for water quality online observation net, feature It is, the host computer periodically reads current voltage and current data and record preservation when not receiving abnormal;It receives different Chang Shi makes fault type according to Exception Type and abnormal front and rear voltage and current numerical value and judges, and preserve near abnormal point Wave data.
CN201810193779.1A 2018-03-09 2018-03-09 A kind of bank base power supply output transient state monitoring system for water quality online observation net Pending CN108267697A (en)

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CN115833670A (en) * 2023-02-15 2023-03-21 中北大学 Energy acquisition device for electromagnetic power generation unit and control method

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Effective date of registration: 20200313

Address after: Yangkou Port Business Building, Yangkou Port Economic Development Zone, Rudong County, Nantong City, Jiangsu Province

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