CN108257965A - Flash memory storage structure and its manufacturing method - Google Patents
Flash memory storage structure and its manufacturing method Download PDFInfo
- Publication number
- CN108257965A CN108257965A CN201611249146.5A CN201611249146A CN108257965A CN 108257965 A CN108257965 A CN 108257965A CN 201611249146 A CN201611249146 A CN 201611249146A CN 108257965 A CN108257965 A CN 108257965A
- Authority
- CN
- China
- Prior art keywords
- floating boom
- side wall
- flash memory
- memory storage
- storage structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005055 memory storage Effects 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims abstract description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 10
- 230000005641 tunneling Effects 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000000926 separation method Methods 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000002210 silicon-based material Substances 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 238000001039 wet etching Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 4
- 230000002265 prevention Effects 0.000 abstract description 3
- 238000003860 storage Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 239000000758 substrate Substances 0.000 description 6
- 238000012545 processing Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003313 weakening effect Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention relates to a kind of flash memory storage structure and its manufacturing methods.This method includes：The depositing polysilicon layer on substrat structure；Floating boom and the field oxide structure being covered on floating boom are formed using the polysilicon layer；Edge in the floating boom bottom forms protection side wall；Tunnel oxide is formed on oxide structure and floating boom on the scene；Control gate is formed on the tunnel oxide.Above-mentioned flash memory storage structure and method, by floating boom bottom edge formed protection side wall, after tunnel oxide is subsequently formed, even if undergoing multiple wet etching, the bottom edge of tunnel oxide is corroded, also can protected side wall prevention further corrode.Control gate will not form wedge angle, can be effectively prevented electron back tunnelling.Further, protection side wall, which uses, is not easy by the silicon nitride material of electron tunneling, it is possibility to have effect prevents electron back tunnelling.The semiconductor devices erasing formed is more stablized.
Description
Technical field
The present invention relates to technical field of semiconductor memory, more particularly to a kind of flash memory storage structure and its manufacturing method.
Background technology
The base unit of semiconductor storage unit is the semiconductor structure that can represent 0 and 1 two states, usually, all
Using the MOS structure that semiconductor devices is common.The basic structure of traditional flash memory (FLASH storages) is mostly in MOS structure
It adds in floating boom storage or release charge represents 0 and 1 two states to realize.
Fig. 1 is the schematic diagram of the memory formed using the basic structure with floating boom.As shown in Figure 2 a, it is this basic
The structure diagram of storage unit.The basic unit of storage 10 includes substrat structure 15, the multi-crystal silicon floating bar on substrate 15
11st, it the field oxide structure 12 that is formed on floating boom 11, the tunnel oxide 13 being covered on floating boom 11 and field oxide structure 12 and covers
Cover the polysilicon control grid 14 on tunnel oxide 13.Wherein, floating boom 11 has tip 111.
It when wiping the basic unit of storage 10, is added high pressure on control gate 14, makes 11 point discharge of floating boom.
The electronics stored in floating boom 11 is penetrated into control gate 14 from tunnel oxide 13, changes the storage state of basic unit of storage 10,
Achieve the purpose that erasing.It is understood that tunnel oxide 13 is thinner, the easier generation tunnelling of electronics.
However in the processing procedure of the basic unit of storage 10, it can be further formed covered with tunnel oxide after forming floating boom 11
The intermediate structure of layer 13.Hereafter the intermediate structure can undergo multiple wet corrosion technique.Due to the unstability of wet etching,
The edge of the bottom of tunnel oxide 13 can corrode more elsewhere relatively, therefore in the mistake for being subsequently formed control gate 14
Cheng Zhong, control gate 14 form wedge angle 141 at this, as shown in Figure 2 b.Electronics is easy to enter floating boom 11 from 14 tunnelling of control gate
(process is known as anti-tunnelling), cause to wipe unstable.
Invention content
Based on this, it is necessary to provide a kind of manufacturing method of flash memory storage structure, floating boom bottom edge can be eliminated
Over etching, improve the stability of erasing.
A kind of manufacturing method of flash memory storage structure, including：
The depositing polysilicon layer on substrat structure；
Floating boom and the field oxide structure being covered on floating boom are formed using the polysilicon layer；
Protection side wall is formed to the edge of the floating boom bottom；
Tunnel oxide is formed on oxide structure and floating boom on the scene；
Control gate is formed on the tunnel oxide.
The edge to the floating boom bottom forms the step of protecting side wall and includes in one of the embodiments,：
The layer deposited isolating in the intermediate structure after forming floating boom and field oxide structure；The separation layer covering field oxide structure,
It the side wall of floating boom and does not cover on the substrat structure of floating boom；
It removes part separation layer and only retains the protection side wall of the edge positioned at floating boom bottom.
In one of the embodiments, dry etching and autoregistration are used during the removal part separation layer.
The separation layer uses silicon nitride material in one of the embodiments,.
The field oxygen knot for forming floating boom using the polysilicon layer and being covered on floating boom in one of the embodiments,
The step of structure, includes：
Mask layer is formed on the polysilicon layer；
The graphical mask layer forms floating boom window exposed portion polysilicon layer；
Oxidation growth is carried out in the floating boom window and forms field oxide structure；
It removes the mask layer and etches the polysilicon layer except an oxide structure overlay area to form floating boom.
The mask layer is removed in one of the embodiments, and dry etching polysilicon layer is to form floating boom.
A kind of flash memory storage structure, including：
Substrat structure；
Floating boom is formed on the substrat structure；
Field oxide structure, covering is on the floating gate；
Protect side wall, the edge positioned at the floating boom bottom；
Tunnel oxide is formed on the floating boom and field oxide structure；
Control gate is formed on the tunnel oxide.
The protection side wall is the material for weakening electron tunneling in one of the embodiments,.
The protection side wall is silicon nitride material in one of the embodiments,.
The height of part that the protection side wall is covered on floating boom side wall in one of the embodiments, is floating boom side wall
The 1/5~1/2 of height.
The flash memory storage structure and method of above-described embodiment, by forming protection side wall in floating boom bottom edge, subsequently
After forming tunnel oxide, even if undergoing multiple wet etching, the bottom edge of tunnel oxide is corroded, and can also be protected
Side wall prevention further corrodes.Control gate will not form wedge angle, can be effectively prevented electron back tunnelling.Further, it protects
Side wall is used and is not easy by the material of electron tunneling, it is possibility to have effect prevents electron back tunnelling.Therefore the semiconductor devices formed
Erasing is more stablized.
Description of the drawings
Fig. 1 is the schematic diagram of the memory formed using the basic structure with floating boom；
Fig. 2 a are the structure diagram of the basic unit of storage in Fig. 1；
Fig. 2 b are structure diagram of the basic unit of storage when there is wet etching defect in Fig. 1；
Fig. 3 is the manufacturing method flow chart of the flash memory storage structure of an embodiment；
Fig. 4 a~Fig. 4 e are the intermediate structure schematic diagram after each step process in flow shown in Fig. 3；
Fig. 5 is the flow chart to form floating boom；
Fig. 6 a~Fig. 6 c and Fig. 4 b are the intermediate structure schematic diagram after each step process in flow shown in Fig. 5；
Fig. 7 is the structure diagram that is formed after the layer deposited isolating in intermediate structure.
Specific embodiment
It is further described below in conjunction with the drawings and specific embodiments.
Fig. 3 is the manufacturing method flow chart of the flash memory storage structure of an embodiment.This method include the following steps S110~
S150.Fig. 4 a~Fig. 4 e are the intermediate structure schematic diagram after each step process.
Step S110：The depositing polysilicon layer 200 on substrat structure 100.Substrat structure 100 includes substrate, on substrate
Source area, drain region and the channel region of formation, and there is grid oxide layer above channel region, for the sake of simplicity, these detailed structures exist
It is not explicitly shown in Fig. 4 a~4e, is only represented with entire substrat structure 100.This step is after substrat structure 100 is completed
Process.The structure formed after this step process is as shown in fig. 4 a.
Step S120：Floating boom 210 and the field oxide structure 220 being covered on floating boom are formed using the polysilicon layer 200.It is more
Crystal silicon layer 200 forms floating boom 210 and field oxide structure 220 by processing.The structure formed after this step process is as shown in Figure 4 b.
Since subsequent wet cleaning is by by many step wet processings, leading to subsequent 220 bottom edge indent of tunnel oxide, very
To the edge indent of the bottom of floating boom 210, it is therefore desirable to perform following steps S130.
Step S130：Protection side wall 610 is formed to the edge of 210 bottom of floating boom.It is formed after this step process
Structure is as illustrated in fig. 4 c.
Step S140：Tunnel oxide is formed on oxide structure 220 and floating boom 210 on the scene.Tunnel oxide 300 is titanium dioxide
Silicon layer, the mode that deposit may be used are formed.The structure formed after this step process is as shown in figure 4d.
Step S150：Control gate 400 is formed on the tunnel oxide 300.The structure formed after this step process is such as
Shown in Fig. 4 e.
The method of above-described embodiment by forming protection side wall 610 in 210 bottom edge of floating boom, is being subsequently formed tunnel
After wearing oxide layer 220, even if undergoing multiple wet etching, the bottom edge of tunnel oxide 220 is corroded, and can also be protected
The prevention of side wall 610 further corrodes.Control gate 400 will not form wedge angle, can be effectively prevented electron back tunnelling.Further
Ground, protection side wall 610, which uses, to be not easy by the silicon nitride material of electron tunneling, it is possibility to have effect prevents electron back tunnelling.Therefore institute
The semiconductor devices erasing of formation is more stablized.
In one embodiment, as shown in figure 5, above-mentioned steps S120 can include following sub-step S121~S124.Figure
6a~Fig. 6 c and Fig. 4 b are the intermediate structure schematic diagram after each step process.
Sub-step S121：Mask layer 500 is formed on the polysilicon layer 200.The mask layer 500 can be silicon nitride
(SiN) layer.The structure formed after this step process is as shown in Figure 6 a.
Sub-step S122：The graphical mask layer 500 forms 510 exposed portion polysilicon layer of floating boom window.This step
The structure formed after processing is as shown in Figure 6 b.
Sub-step S123：Oxidation growth is carried out in the floating boom window and forms field oxide structure.This step is in raw long field oxide
While structure, the tip of floating boom can be formed.The structure formed after this step process is as fig. 6 c.
Sub-step S124：The polysilicon layer for removing the mask layer and etching except an oxide structure overlay area is floating to be formed
Grid.The structure formed after this step process is as shown in Figure 4 b.
In one embodiment, above-mentioned steps S130 can include following sub-step S131~S132.Below in conjunction with Fig. 4 b,
Fig. 7 and Fig. 4 c are illustrated.
Step S131：The layer deposited isolating in the intermediate structure after forming floating boom and field oxide structure.The intermediate structure is as schemed
Shown in 4b.After this step process, as shown in fig. 7, the separation layer 600 covering field oxide structure 220, floating boom 210 side wall with
And it does not cover on the substrat structure 100 of floating boom 210.Silicon nitride material may be used in the separation layer 500.It is appreciated that by heavy
Product separation layer, the edge of floating boom 210 also have part separation layer.
Step S132：It removes part separation layer and only retains the separation layer formation protection side wall positioned at floating boom edge.It goes
The part separation layer removed includes covering the part on oxide structure surface on the scene, is covered in the part of floating boom side wall and is covered in substrate
Part in structure.Dry etching may be used in this step.When etching is positioned at the part of floating boom side wall, carved using autoregistration
Erosion.After this step process, the structure of formation is as illustrated in fig. 4 c.
It is appreciated that other modes can also be used to form protection side wall in the floating boom edge, it is not limited to above-mentioned side
Formula.
Based on identical inventive concept, a kind of flash memory storage structure is provided.As shown in fig 4e, the flash memory storage structure include according to
Substrat structure 100, floating boom 210, field oxide structure 220, tunnel oxide 300 and the control gate 400 of secondary stacking.
Substrat structure 100 includes substrate, the source area formed on substrate, drain region and channel region, and above channel region
With grid oxide layer, floating boom 210 is located on grid oxide layer.For the sake of simplicity, these detailed structures are not explicitly shown in figure 4e, only with
Entire substrat structure 100 represents.Floating boom 210 is formed on the substrat structure 100, and positioned at the source area and drain region
Between raceway groove on.Floating boom 210 is polycrystalline silicon material.The floating boom 210 has discharge tip 211.Field oxide structure 220 covers
On the floating boom 210, field oxide structure 220 is earth silicon material.Tunnel oxide 300 is formed in the floating boom 210 and field
On oxide structure 220, tunnel oxide 300 is earth silicon material.Wherein, being equipped with for the edge of 210 bottom of floating boom protects side
The material for weakening electron tunneling, such as silicon nitride material may be used in wall 610, the protection side wall 610.Tunnel oxide 300
It is covered on the side wall and protection side wall 610 of floating boom 210.Control gate 400 is formed on the tunnel oxide 300, control
Grid 400 are polycrystalline silicon material.The height for protecting side wall 610 is the 1/5~1/2 of floating boom height of side wall.
The flash memory storage structure of above-described embodiment, by forming protection side wall 610 in 210 bottom edge of floating boom, rear
Continue after forming tunnel oxide 300, even if undergoing multiple wet etching, the bottom edge of tunnel oxide 220 is corroded,
Meeting protected side wall 610 prevents to further corrode.Control gate 400 will not form wedge angle, can be effectively prevented electron back tunnelling.
Further, protection side wall 610, which uses, is not easy by the silicon nitride material of electron tunneling, it is possibility to have effect prevents electron back tunnelling.
The semiconductor devices erasing formed is more stablized.
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, it is all considered to be the range of this specification record.
Embodiment described above only expresses the several embodiments of the present invention, and description is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that those of ordinary skill in the art are come
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Range.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
1. a kind of manufacturing method of flash memory storage structure, including：
The depositing polysilicon layer on substrat structure；
Floating boom and the field oxide structure being covered on floating boom are formed using the polysilicon layer；
Protection side wall is formed to the edge of the floating boom bottom；
Tunnel oxide is formed on oxide structure and floating boom on the scene；
Control gate is formed on the tunnel oxide.
2. the manufacturing method of flash memory storage structure according to claim 1, which is characterized in that described to the floating boom bottom
Edge formed protection side wall the step of include：
The layer deposited isolating in the intermediate structure after forming floating boom and field oxide structure；The separation layer covering field oxide structure, floating boom
Side wall and do not cover on the substrat structure of floating boom；
It removes part separation layer and only retains the protection side wall of the edge positioned at floating boom bottom.
3. the manufacturing method of flash memory storage structure according to claim 2, which is characterized in that the removal part separation layer
Shi Caiyong dry etchings and autoregistration.
4. the manufacturing method of flash memory storage structure according to claim 2, which is characterized in that the separation layer is using nitridation
Silicon materials.
5. the manufacturing method of flash memory storage structure according to claim 1, which is characterized in that described to utilize the polysilicon
The step of layer formation floating boom and the field oxide structure being covered on floating boom, includes：
Mask layer is formed on the polysilicon layer；
The graphical mask layer forms floating boom window exposed portion polysilicon layer；
Oxidation growth is carried out in the floating boom window and forms field oxide structure；
It removes the mask layer and etches the polysilicon layer except an oxide structure overlay area to form floating boom.
6. the manufacturing method of flash memory storage structure according to claim 5, which is characterized in that remove the mask layer and do
Method etches polysilicon layer to form floating boom.
7. a kind of flash memory storage structure, including：
Substrat structure；
Floating boom is formed on the substrat structure；
Field oxide structure, covering is on the floating gate；
Protect side wall, the edge positioned at the floating boom bottom；
Tunnel oxide is formed on the floating boom and field oxide structure；
Control gate is formed on the tunnel oxide.
8. flash memory storage structure according to claim 7, which is characterized in that the protection side wall is to weaken electron tunneling
Material.
9. flash memory storage structure according to claim 7, which is characterized in that the protection side wall is silicon nitride material.
10. flash memory storage structure according to claim 7, which is characterized in that the protection side wall is covered in floating boom side wall
On part height be floating boom height of side wall 1/5~1/2.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611249146.5A CN108257965A (en) | 2016-12-29 | 2016-12-29 | Flash memory storage structure and its manufacturing method |
| PCT/CN2017/110888 WO2018121109A1 (en) | 2016-12-29 | 2017-11-14 | Flash storage structure and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611249146.5A CN108257965A (en) | 2016-12-29 | 2016-12-29 | Flash memory storage structure and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108257965A true CN108257965A (en) | 2018-07-06 |
Family
ID=62706935
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611249146.5A Pending CN108257965A (en) | 2016-12-29 | 2016-12-29 | Flash memory storage structure and its manufacturing method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN108257965A (en) |
| WO (1) | WO2018121109A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111048511A (en) * | 2018-10-15 | 2020-04-21 | 无锡华润上华科技有限公司 | Flash device and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08204034A (en) * | 1995-01-26 | 1996-08-09 | Sanyo Electric Co Ltd | Manufacture of nonvolatile semiconductor memory device |
| US5879993A (en) * | 1997-09-29 | 1999-03-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nitride spacer technology for flash EPROM |
| US6001690A (en) * | 1998-02-13 | 1999-12-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming flash EPROM by using iso+aniso silicon nitride spacer etching technology |
| US6908813B2 (en) * | 2003-04-09 | 2005-06-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming tiny silicon nitride spacer for flash EPROM by fully wet etching technology |
| CN101123269A (en) * | 2006-08-10 | 2008-02-13 | 台湾积体电路制造股份有限公司 | Split-gate flash memory device and its manufacture method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000216274A (en) * | 1999-01-26 | 2000-08-04 | Seiko Epson Corp | Semiconductor device and manufacture of the same |
| KR20030060139A (en) * | 2002-01-07 | 2003-07-16 | 삼성전자주식회사 | Split-gate type non-volatile memory and method of fabricating the same |
| KR100718253B1 (en) * | 2005-08-17 | 2007-05-16 | 삼성전자주식회사 | Method of manufacturing a non-volatile memory device |
-
2016
- 2016-12-29 CN CN201611249146.5A patent/CN108257965A/en active Pending
-
2017
- 2017-11-14 WO PCT/CN2017/110888 patent/WO2018121109A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08204034A (en) * | 1995-01-26 | 1996-08-09 | Sanyo Electric Co Ltd | Manufacture of nonvolatile semiconductor memory device |
| US5879993A (en) * | 1997-09-29 | 1999-03-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nitride spacer technology for flash EPROM |
| US6001690A (en) * | 1998-02-13 | 1999-12-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming flash EPROM by using iso+aniso silicon nitride spacer etching technology |
| US6908813B2 (en) * | 2003-04-09 | 2005-06-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming tiny silicon nitride spacer for flash EPROM by fully wet etching technology |
| CN101123269A (en) * | 2006-08-10 | 2008-02-13 | 台湾积体电路制造股份有限公司 | Split-gate flash memory device and its manufacture method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111048511A (en) * | 2018-10-15 | 2020-04-21 | 无锡华润上华科技有限公司 | Flash device and preparation method thereof |
| CN111048511B (en) * | 2018-10-15 | 2022-03-01 | 无锡华润上华科技有限公司 | Flash device and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2018121109A1 (en) | 2018-07-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100568509C (en) | The manufacture method of nonvolatile semiconductor memory member | |
| CN100373552C (en) | Method for forming a gate electrode in a non volatile memory device | |
| CN105742171A (en) | Floating gate and preparation method thereof | |
| CN109378314A (en) | A kind of manufacturing method of flush memory device | |
| US20080213970A1 (en) | Process for the formation of dielectric isolation structures in semiconductor devices | |
| CN103035561A (en) | Process method for forming inclined angle at top of deep groove | |
| CN108257965A (en) | Flash memory storage structure and its manufacturing method | |
| CN104979295A (en) | Manufacturing method of embedded split-gate flash memory device | |
| CN108807392A (en) | Flash memory and its manufacturing method | |
| CN109728099A (en) | A kind of flush memory device and its manufacturing method | |
| WO2006046301A1 (en) | Semiconductor device and semiconductor device manufacturing method | |
| TW202117845A (en) | Method for manufacturing semiconductor structure | |
| CN101211800A (en) | Method for preventing water vapor and mobile ion entering into internal circuit and corresponding bonding window | |
| CN108493190A (en) | Memory and forming method thereof | |
| CN102280378B (en) | The forming method of SONOS structure | |
| TW201537748A (en) | Memory device and method for forming the same | |
| KR20080064306A (en) | Method of fabricating trench isolation for semiconductor device | |
| CN105336697B (en) | A method of manufacture flash memory | |
| CN105336699B (en) | The forming method of NAND flash memory device | |
| US10930545B2 (en) | Method for forming semiconductor structure | |
| CN108598082A (en) | flash memory preparation method | |
| CN102117777B (en) | Method for etching oxide-nitride-oxide interpoly dielectric with wet method | |
| JP3054530B2 (en) | Manufacturing method of nonvolatile semiconductor memory device | |
| KR100998959B1 (en) | Method for manufacturing of flash memory device | |
| CN106129060B (en) | A kind of floating gate type flash memory and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180706 |
|
| RJ01 | Rejection of invention patent application after publication |