CN108257914A - A kind of method that multiple regular hexagon wafer units are arranged on wafer - Google Patents
A kind of method that multiple regular hexagon wafer units are arranged on wafer Download PDFInfo
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- CN108257914A CN108257914A CN201810061238.3A CN201810061238A CN108257914A CN 108257914 A CN108257914 A CN 108257914A CN 201810061238 A CN201810061238 A CN 201810061238A CN 108257914 A CN108257914 A CN 108257914A
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Abstract
This disclosure relates to a kind of method that multiple regular hexagon wafer units are arranged on wafer, includes the following steps：According to the expection area of the substrate for semiconductor chip, the length of side d of each regular hexagon wafer unit in the multiple regular hexagon wafer unit is determined；The multiple regular hexagon wafer unit is arranged on the wafer, enabling the length of side being cut into from the wafer is that the quantity of the regular hexagon wafer unit of d is maximum.
Description
Technical field
This disclosure relates to semiconductor applications, multiple regular hexagon wafer lists are arranged in particular to one kind on wafer
The method of member.
Background technology
In the manufacturing process of semiconductor chip, need to manufacture semiconductor chip using wafer as substrate.In general, wafer
It is relatively large sized, and selected from a series of stock sizes (for example, a diameter of 6 inches, 8 inches, 12 inches etc.), and partly lead
The size of body chip is often much smaller.Therefore, single wafer can serve as the substrate of multiple semiconductor chips, wherein, each
The substrate of semiconductor chip both corresponds to the smaller wafer unit as a wafer part.In order to be produced from single wafer
Multiple semiconductor chips usually arrange corresponding multiple wafer units on wafer first, then according to the arrangement to wafer into
Row cutting, so as to obtain multiple wafer units for semiconductor chip.
In the prior art, shallow slot generally is marked in crystal column surface using laser, is then marked using diamond tool edge
Shallow slot cut, that is, with grinding mode wafer is divided into multiple wafer units.By diamond tool, machinery belongs in itself
The limitation of property, this cutting mode are adapted for long straight cuts.Therefore, in the prior art, the wafer that will usually cut
Unit is arranged as multiple rectangular or squares closely arranged, in order to which cutter carries out continuous long straight cuts.But with gold
The loss that hard rock cutter is cut to cutter is very huge.Moreover, multiple rectangular or squares are arranged on circular wafer
Wafer unit the marginal portion for leading to wafer can not be fully utilized, so as to limit the utilization rate of wafer.
It is, therefore, desirable to provide a kind of new technology is above-mentioned of the prior art one or more to solve the problems, such as.
Invention content
One purpose of the disclosure is to provide a kind of method that multiple regular hexagon wafer units are arranged on wafer.
According to the disclosure in a first aspect, providing a kind of side that multiple regular hexagon wafer units are arranged on wafer
Method, this method include the following steps：According to the expection area of the substrate for semiconductor chip, multiple regular hexagon wafers are determined
The length of side d of each regular hexagon wafer unit in unit；Multiple regular hexagon wafer unit is arranged on wafer so that energy
The quantity of regular hexagon wafer unit that enough length of sides being cut into from wafer are d is maximum.
One according to an embodiment of the present disclosure the advantage is that wafer list by arranging multiple regular hexagons on wafer
The wafer unit of member rather than rectangular or square can improve the utilization rate of wafer in the case where wafer cellar area is identical.
It is another advantage of according to an embodiment of the present disclosure to be, it is cut without using diamond tool, so as to keep away
Exempt from tool wear, and the wafer unit convenient for being cut into regular hexagon.
By referring to the drawings to the detailed description of the exemplary embodiment of the disclosure, the other feature of the disclosure and its
Advantage will become apparent.
Description of the drawings
The attached drawing of a part for constitution instruction describes embodiment of the disclosure, and is used to solve together with the description
Release the principle of the disclosure.
With reference to attached drawing, according to following detailed description, the disclosure can be more clearly understood, wherein：
Fig. 1 shows the schematic diagram for arranging multiple square wafer units on wafer in the prior art.
Fig. 2 shows the signals according to an embodiment of the present disclosure that multiple regular hexagon wafer units are arranged on wafer
Figure.
Fig. 3 A-3D schematically show cutting step according to an embodiment of the present disclosure, and the cutting step is used for
Multiple cutting line segments corresponding with the arrangement of Fig. 2 are formed on wafer.
Fig. 4 is the schematic diagram for illustrating to be formed the sequence of each cutting line segment in cutting step.
Fig. 5 show for perform cutting step periodic laser source excitation cycle schematic diagram.
Fig. 6 A show the schematic diagram of the mask according to an embodiment of the present disclosure for cutting step.
Fig. 6 B-6C show the system according to an embodiment of the present disclosure that cutting step is performed using mask.
Fig. 7 A, which are shown, according to an embodiment of the present disclosure to be used to from wafer obtain showing for multiple regular hexagon wafer units
The flow chart of example property method.
Fig. 7 B further illustrate the flow chart of the cutting step in Fig. 7 A according to an embodiment of the present disclosure.
Note that in embodiments described below, same reference numeral is used in conjunction between different attached drawings sometimes
Come the part for representing same section or there is identical function, and omit its repeated explanation.In the present specification, using similar mark
Number and letter represent similar terms, therefore, once being defined in a certain Xiang Yi attached drawing, then do not needed in subsequent attached drawing pair
It is further discussed.
In order to make it easy to understand, position, size and range of each structure shown in attached drawing etc. etc. does not indicate that reality sometimes
Position, size and range etc..Therefore, disclosed invention is not limited to position, size and range disclosed in attached drawing etc. etc..
Specific embodiment
The various exemplary embodiments of the disclosure are described in detail now with reference to attached drawing.It should be noted that：Unless in addition have
Body illustrates that the unlimited system of component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
Scope of disclosure.
It is illustrative to the description only actually of at least one exemplary embodiment below, is never used as to the disclosure
And its application or any restrictions that use.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of, the technology, method and apparatus should be considered as authorizing part of specification.
In shown here and discussion all examples, any occurrence should be construed as merely illustrative, without
It is as limitation.Therefore, the other examples of exemplary embodiment can have different values.
Referring now to Fig. 1.Fig. 1 is shown arranges multiple square wafer unit 111A- on wafer 101 in the prior art
The schematic diagram of E.
In Fig. 1, wafer 101 is the circular wafers used in semiconductor chip production process, for example, a diameter of 6 inches,
8 inches or 12 inches of wafer.It is substrate with wafer 101, it is possible to produce multiple semiconductor chips, each semiconductor chip pair
Smaller wafer unit 111A-Es of the Ying Yu as a part for wafer 101.It should be noted that although fig 1 illustrate that in crystalline substance
5 wafer unit 111A-E are disposed on circle 101, but this is only to facilitate the purpose of explanation.In practice, wafer unit
Area it is usually more much smaller than the area of wafer, therefore would generally be disposed on a wafer more wafer units (for example,
Tens up to a hundred).
Arrange that square wafer unit 111A-E is relatively low by the utilization rate for leading to wafer 101 on wafer 101.In Fig. 1,
Wafer unit 111A-E is depicted with solid line, this shows that complete wafer unit 111A-E can be obtained from wafer 101.In addition,
In Fig. 1 also wafer unit 111F-I is depicted with dotted line.According to arrangement shown in FIG. 1, it is impossible to be obtained completely from wafer 101
Wafer unit 111F-I.In fact, even if the arrangement of adjustment Fig. 1, can not also obtain more areas and wafer unit 111A-E
Equal square wafer unit.That is, in wafer 101 other than those parts occupied by wafer unit 111A-E,
Remaining part will be wasted.The arrangement of this multiple square wafers shown in FIG. 1 limits the utilization rate of wafer, is unfavorable for
Reduce production cost.
It should be noted that even if by the square wafer unit in Fig. 1 replace with rectangle wafer unit or area compared with
Small rectangular or square unit, still will face the problem of wafer edge portion is difficult to be fully utilized, this is by square
Or rectangle wafer unit is relative to the geometric attribute decision of circular wafers.
For this purpose, embodiment of the disclosure proposes a kind of method that multiple regular hexagon wafer units are arranged on wafer.
Multiple regular hexagon wafer unit 211A- are arranged on wafer 201 Fig. 2 shows according to an embodiment of the present disclosure
The schematic diagram of G.
In fig. 2, wafer 201 is the circular wafers used in semiconductor chip production process, for example, a diameter of 6 inches,
8 inches or 12 inches of wafer.For the purpose for comparing and illustrating, the area of wafer 201 is plotted as and the wafer in Fig. 1
101 area equation.
In accordance with an embodiment of the present disclosure, multiple regular hexagon wafer unit 211A-G are arranged on wafer 201.This is multiple just
The length of side of each regular hexagon wafer unit is equal in hexagon wafer unit 211A-G, herein with symbol d come unified table
Show.The length of side d of regular hexagon wafer unit 211A-G be according to the expection area of the substrate of the semiconductor chip used in it come
Determining.For example, the chip area when semiconductor chip is expected to SdieWhen, it may be determined that the length of side of regular hexagon wafer unit
About d=(Sdie/2.59)1/2.Regular hexagon wafer unit is determined in the expection area of the substrate according to semiconductor chip
During the value of the length of side d of 211A-G, it may be considered that the loss of the wafer area in technique (such as cutting step).
The quantity of regular hexagon wafer unit for being d Fig. 2 shows the length of side for making it possible to be cut into from wafer 201 is maximum
A kind of arrangement.In this preferred embodiment, regular hexagon wafer unit 211A-G is arranged so that one of those
The center of regular hexagon wafer unit (for example, regular hexagon wafer unit 211D) is overlapped with the center of circle of wafer 201, and other
Regular hexagon wafer unit (that is, wafer unit 211A-C, 211E-G) be arranged to closely surround regular hexagon wafer unit
211D.As an example, in the arrangement shown in fig. 2, it can be brilliant from the regular hexagon that the length of side that wafer unit 201 is cut into is d
Circle unit is 7.
It should be noted that while figure 2 show that a kind of preferred embodiment, but what those skilled in the art will be clear that
It is that other arrangements are also feasible.For example, in the area S for having selected wafer 201 and expected regular hexagon wafer is determined
In the case of the length of side d of unit, there are 7 such regular hexagon wafer units being cut into from wafer 201 other
Arrangement.For example, the center of regular hexagon wafer unit 211D can not be overlapped with the center of circle of wafer 201, but it is spaced centainly
The distance of distance, the wherein interval is associated with S and d.
Compared to Figure 1, it is shown in Fig. 2 to arrange the utilization rate that wafer 201 greatly improved.As previously mentioned, in order to compare
Purpose, wafer 201 are plotted as and 101 area equation of wafer in Fig. 1.Similarly, for comparison purposes, wafer unit
Any wafer unit in 211A-G is plotted as and any square wafer elemental area in the wafer unit 111A-E in Fig. 1
Product is of substantially equal (that is, the area of any wafer unit in wafer unit 211A-G is plotted as about 2.59d2, and wafer list
The area of any square wafer unit in first 111A-E is plotted as 2.56d2).It as shown in Fig. 2, can be with from wafer 201
7 areas are obtained as 2.59d2Complete regular hexagon wafer unit.In contrast, as shown in Figure 1, only may be used from wafer 101
To obtain 5 areas as 2.56d2Complete square wafer unit.From shown embodiment it is found that according to the disclosure
The method of preferred embodiment has been obviously improved the utilization rate of wafer relative to existing method.
Fig. 3 A- Fig. 3 D schematically show cutting step according to an embodiment of the present disclosure, and the cutting step is used for
Multiple cutting line segments corresponding with the arrangement of Fig. 2 are formed on wafer 301.
In Fig. 3 A- Fig. 3 D, wafer 301 is the circular wafers used in semiconductor chip production process.For example, wafer
301 can be the wafer identical with wafer 201.
The arrangement of Fig. 2 is applied to the wafer 301 in Fig. 3 A- Fig. 3 D, multiple wafer units on wafer 301 can be obtained
The arrangement of 311A-G.For convenience described below, in Fig. 3 A- Fig. 3 D, describe multiple wafer unit 311A- using dotted line
G。
Fig. 3 A depict cutting step 300A according to an embodiment of the present disclosure.Cutting step 300A shapes on wafer 301
Into discontinuous multiple first cutting line segments 321.Multiple first cutting line segments 321 can include being drawn with heavy line in figure 3 a
First cutting line segment 321-1 to 321-10.It should be noted that when using term " cutting line segment ", can refer in crystalline substance
The slot (for example, cutting groove, scribe line etc.) formed on circle 301 or the metamorphic layer formed inside wafer 301, and this
The depth of a little slots or metamorphic layer can be suitable arbitrary depth.
As shown in Figure 3A, it is obtained by the length of each first cutting line segment 321 that cutting step 300A is obtained for expection
Regular hexagon wafer unit length of side d, also, this multiple first cuttings line segment 321 be distributed in wafer 301 planar
In one group of first straight line 322.
One group of first straight line 322 includes first straight line 322-1 to 322-7.It should be noted that first straight line 322
It is not the entity being present on wafer 301, but is introduced into describe the path along cutting step 300A.First is straight
Line 322 is parallel to each other, and is separated between adjacent two first straight lines 322 with the first preset distance L1.Every first straight line
One or more first can be distributed on 322 and cut line segment 321, and in the one or more first cutting line segment 321
It is separated between two neighboring first cutting line segment with the second preset distance L2.For example, on first straight line 322-6 there are two distributions
First cutting line segment 321-8 and 321-9, and between the first cutting line segment 321-8 and 321-9 between be divided into L2.In addition, along
The adjacent first cutting line segment of same first straight line 322 (for example, first straight line 322-6) is (for example, the first cutting line segment 321-
8 and 321-9) between wafer be not cut, also that is, locating not forming cutting line segment in the position.
Comparison diagram 2 and Fig. 3 A, it may be clearly seen that, multiple first cutting line segments 321 that cutting step 300A is formed
Corresponding to the part in all sides of regular hexagon wafer unit 211A-G multiple in the arrangement of Fig. 2.Such as it will be detailed below
Description, after cutting step 300A is performed, by repeating similar with 300A cut twice as shown in Fig. 3 B- Fig. 3 C
Step is cut, the corresponding cutting line in all sides of multiple regular hexagon wafer unit 211A-G in the arrangement with Fig. 2 can be formed
Section.
For example, by the way that wafer to be rotated by a certain angle to (for example, 60 ° or 120 °) later to the repetition Fig. 3 of wafer 301 A's
The cutting step of the repetition (for ease of description, is known as cutting step 300B) by cutting step 300A here, can be in wafer
Discontinuous multiple second cutting line segments 331 are formed on 301, as shown in Figure 3B.In figure 3b, multiple second cutting line segments 331
It can include the second cutting line segment 331-1 to 331-10 drawn with heavy line.Here, for the sake of clarity, in figure 3b only
Multiple second cutting line segments 331 that cutting step 300B is formed are depicted, without the cutting step 300A before being depicted in
In formed it is multiple first cutting line segments 321.
As shown in Figure 3B, it is obtained by the length of each second cutting line segment 331 that cutting step 300B is obtained for expection
Regular hexagon wafer unit length of side d, also, this multiple second cuttings line segment 331 be distributed in wafer 301 planar
In one group of second straight line 332.
One group of second straight line 332 includes second straight line 332-1 to 332-7.It is similar with first straight line, second straight line
322 be not entity present on wafer 301, but is introduced into the path along for description cutting step 300B.Second
Straight line 332 is parallel to each other and intersects with first straight line 322.With the first preset distance between two adjacent second straight lines 332
L1 is separated.One or more second can be distributed in every second straight line 332 and cut line segment 331, and the one or more
It is separated between two neighboring second cutting line segment in second cutting line segment 331 with the second preset distance L2.In addition, along same
Wafer between the adjacent second cutting line segment of second straight line 332 (for example, second straight line 332-6) is not cut, also that is,
Cutting line segment is not formed at the position.
Cutting step 300B completion after, by again by wafer rotate by a certain angle (for example, 60 ° or 120 °) it
The cutting step 300A for repeating Fig. 3 A to wafer 301 afterwards (for ease of description, repetition cutting step here is known as to cut step
Rapid 300C), discontinuous multiple third cutting line segments 341 can be formed on wafer 301, as shown in Figure 3 C.In fig. 3 c, it is more
A third cutting line segment 341 can include cutting line segment 341-1 to 341-10 with the third that heavy line is drawn.Similarly, in order to
For the sake of clear, multiple thirds cutting line segment 341 that cutting step 300C is formed is depicted only in fig. 3 c, without being depicted in
The multiple first cutting line segments 321 and multiple second cutting line segments 331 formed in cutting step 300A and 300B before.
As shown in Figure 3 C, the length of each third cutting line segment 341 obtained by cutting step 300C is obtained for expection
Regular hexagon wafer unit length of side d, also, this multiple thirds cutting line segment 341 be distributed in wafer 301 planar
On one group of third straight line 342.
One group of third straight line 342 includes third straight line 342-1 to 342-7.It is similar with first straight line and second straight line,
Third straight line 342 is not entity present on wafer 301, but is introduced into the road along for description cutting step 300C
Diameter.Third straight line 342 is parallel to each other and intersects with first straight line 322, second straight line 332.Two adjacent third straight lines 342
Between separated with the first preset distance L1.One or more third cutting line segments can be distributed on every third straight line 342
341, and with the second preset distance between the two neighboring third cutting line segment in one or more third cutting line segment 341
L2 is separated.In addition, along same third straight line 342 (for example, third straight line 342-6) two neighboring third cutting line segment it
Between wafer be not cut, also that is, locating not forming cutting line segment in the position.
In accordance with an embodiment of the present disclosure, diamond cutter can not be used, but one or more lasing light emitters is used to emit
Laser realize above-mentioned cutting step 300A, 330B and 300C.Lasing light emitter (not drawing) can emit laser to wafer 301,
So that the property of the wafer at illuminated laser spot changes.By illuminated laser spot relative to the movement of wafer 301, Ke Yi
Expected cutting line segment is formed on wafer 301.Wherein, by lasing light emitter emit laser can be infrared laser or it is ultraviolet swash
Light or other kinds of suitable laser well known by persons skilled in the art.
By above-mentioned cutting step 300A, 300B and 300C, can obtain as shown in Figure 3D comprising the multiple first cuttings
Line segment, the second cutting line segment, third cut the wafer 301 of line segment.Pass through this cutting step, it is possible to reduce cutting positive six side
The number of revolutions of wafer or the number of revolutions in laser line diameter path in shape wafer unit process.
After the above-mentioned cutting step of completion is performed, after one or more of semiconductor chip fabrication process being performed
Continuous step.For example, in accordance with an embodiment of the present disclosure, further step toward division can be performed to wafer 301, make the wafer edge more
A first cutting line segment, the second cutting line segment and third cutting line segment division, so as to obtain multiple regular hexagon wafer units.
Any suitable splitting method can be used, including but not limited to applies stress to wafer 301 or using extension glued membrane side
Method.
Described above is arrange multiple regular hexagon wafer units and according to institute on wafer according to various embodiments
It states arrangement and obtains the method that multiple regular hexagon wafer unit is obtained from wafer.It will be apparent to one skilled in the art that
Geometry shown in foregoing description is only schematical with quantitative relation, is not meant to the scope of the present disclosure being limited to
The arrangement of specific quantity or particular geometric relationship.
Next multiple cutting line segments how are formed on wafer for cutting step specific descriptions.
Fig. 4 is the schematic diagram for illustrating to be formed the sequence of each first cutting line segment 321 in cutting step 300A.
In cutting step 300A, each first cutting line segment 321 is formed along each in one group of first straight line 322.For example, edge
First straight line 322-1 to form the first cutting line segment 321-1 and form the first cutting line segment along first straight line 322-2
321-2 and 321-3.In accordance with an embodiment of the present disclosure, it can concurrently be formed on the different straight lines in one group of first straight line 322
First cutting line segment.For example, it can concurrently be formed positioned at different first straight line Shangdis cutting line segment 321-1,321-4,321-
7、321-10.This point can be realized using multiple lasing light emitters for being excited simultaneously, wherein, each lasing light emitter is used to form pair
The first cutting line segment in the first straight line 322 answered.In addition, for any bar first straight line 322, it can be sequentially formed
On one or more first cut line segment.For example, for first straight line 322-2, the first cutting line thereon can be initially formed
Section 321-2 subsequently forms another first cutting line segment 321-3 thereon.
It should be noted that although Fig. 4 is described for cutting step 300A, description can also be applied to
Cutting step 300B and 300C.
In accordance with an embodiment of the present disclosure, can aforementioned cutting step be performed with the lasing light emitter that service life excites, so as to
Multiple first cutting line segments 321 using the length that the second preset distance L2 is separated as d are sequentially formed in every first straight line 322
(for cutting step 300A).
Fig. 5 show for perform cutting step (300A, 300B or 300C) periodic laser source excitation cycle
Schematic diagram.For example, periodic laser source can be activated into higher-wattage P1 in time T1 to wafer transmitting laser, and
Kept relatively low power P 2 (for example, P2 can be 0) in time T2 by deexcitation, wherein power P 1 be selected as it is sufficiently high with
As for can form corresponding cutting line segment on wafer, and power P 2 be selected as it is sufficiently low so that it cannot on wafer shape
Into cutting line segment.Therefore, the firing time section (T1) of lasing light emitter can correspond to be formed the cutting line segment on wafer, and lasing light emitter
The deexcitation period (T2) can correspond between the adjacent cutting line segment being located along the same line on wafer be spaced.According to
Embodiment of the disclosure, the excitation cycle in periodic laser source is the length of side d and based on above-mentioned regular hexagon wafer unit
Two preset distance L2 come determining.For example, lasing light emitter is excited when illuminated laser spot passes through the cutting line segment that length is d, and
When by cutting the interval L2 between line segment, lasing light emitter is by deexcitation.Further, it is also possible to according to lasing light emitter (laser in other words
Point of irradiation) period that at least one lasing light emitter is excited is determined relative to the movement speed of wafer.
In accordance with an embodiment of the present disclosure, laser that lasing light emitter emits and wafer can be controlled to connect by using mask
It touches, so as to control the formation that line segment is cut on wafer.
Fig. 6 A show the schematic diagram of the mask 650 according to an embodiment of the present disclosure for cutting step.Fig. 6 B-6C show
The system 600 according to an embodiment of the present disclosure that cutting step is performed using mask 650 is gone out.
Mask 650 can be made of light blocking material to be shone directly into the laser that lasing light emitter is prevented to emit on wafer, and
Preferably, mask 650 can partly reflected laser light source transmitting laser.As shown in Figure 6A, it can be disposed with not on mask 650
Continuous multiple slots 621 (for example, slot 621-1 to 621-10), each slot 621 can run through mask 650, so that laser energy
Enough across slot.Laser cannot pass through the other parts of mask 650.On mask 650, the arrangement of multiple slots 621 can correspond to
The arrangement of cutting line segment to be formed on wafer.For example, the length of each slot 621 can be d, and compartment of terrain is distributed in one
On the parallel straight line 622 of group, wherein, the distance of adjacent two straight lines 622 is the first preset distance L1, and in same straight line
The distance between two adjacent slots 621 on 622 are the second preset distance L2.This arrangement of multiple slots 621 on mask 650
So that during the cutting step is performed, it can be in institute when across the multiple slot 621 along the laser that straight line 622 moves
It states and the cutting line segment with corresponding arrangement is formed on wafer.
In addition, one or more alignment marks 651 and 652 are also provided on mask 650.For example, alignment mark 651
It can be used for mask 650 and wafer alignment (for example, being aligned with the notch (not shown) on wafer).Alignment mark 652 can be with
For mask 650 to be aligned with lasing light emitter.By the way that mask 650 is aligned respectively with wafer and lasing light emitter, can realize wafer with
The alignment of lasing light emitter therebetween.
Fig. 6 B-6C show the example according to an embodiment of the present disclosure that cutting step can be performed using mask 650
Sexual system 600.
In system 600, wafer 601 is fixed relative to wafer carrying platform 602, and mask 650 passes through 603 quilt of support construction
It is placed between wafer 601 and lasing light emitter 604.Preferably, mask 650 is not contacted with wafer 601, and line segment is cut to avoid interference
Formation.Lasing light emitter 604 is configured as emitting laser to wafer 601, to form desired cutting line segment on wafer 601.
In fig. 6b, the laser (being represented by solid arrow) emitted by lasing light emitter 604 is illustrated as passing through on mask 650 just
One or more slots 621 (light-colored part on mask 650), so as to form cutting line segment (on wafer 601 on wafer 601
Dark parts).In this case, the reflected light (being represented by dotted arrow) for arriving at the laser of wafer 601 is largely covered
Mould 650 stops.
In figure 6 c, the laser (being represented by solid arrow) emitted by lasing light emitter 604 be illustrated as being masked 650 blockings (that is,
The position that laser path intersects with mask 650 is not slot 621) and the wafer 601 below mask cannot be arrived at, therefore,
Corresponding position on wafer 601 does not form cutting line segment.In this case, there is more laser (being represented by dotted arrow)
It is masked 650 reflections.
It can judge whether the laser currently emitted passes through mask based on the laser energy reflected by mask 650
Multiple slots on 650, and the transmission power of lasing light emitter 604 is adjusted based on the judgement.For example, when reflection laser energy compared with
When low, it is meant that the laser emitted currently can by the slot 621 on mask 650, and by wafer reflect laser energy
(if any) it is masked blocking substantially, the laser power emitted at this time is effective (Fig. 6 B)；And when the laser of reflection
When energy is higher, it is meant that the laser emitted is largely directly masked 650 reflections, and the laser power emitted at this time is nothing
(Fig. 6 C) of effect.It in accordance with an embodiment of the present disclosure, can be when the laser energy of reflection be weaker (during such as less than first threshold)
Laser is emitted with higher the first power, for forming cutting line segment on wafer；And the laser energy in reflection is higher
When (such as during higher than second threshold) laser is emitted with the second relatively low power, so as to avoid mask is damaged and is saved
About laser power.In order to accomplish this point, it can set and be passed for sensing the one or more of the laser energy reflected by mask
Sensor 660, sensor 660 can be coupled with lasing light emitter 604, to adjust lasing light emitter based on the reflected laser energy sensed
604 transmission power.
System 600 can be used for consistently performing multiple steps in aforementioned cutting step 300A, 300B, 300C.For example,
When performing cutting step 300A, the relative position of mask 650 and wafer 601 can be set so that the slot 621 on mask 650
The expected multiple first cutting line segments 321 to be formed of alignment.This can be realized by the alignment mark 651 on mask 650.
After the completion of cutting step 300A is performed, the relative position of mask 650 and wafer 601 can be converted so that the slot on mask 650
The expected multiple second cutting line segments 331 to be formed of 621 alignments, then perform cutting step 300B.The transformation can pass through rotation
Turn either or both of wafer 601 or mask 650 to realize.It for example, can be by wafer carrying platform 602 by wafer
601 around the scheduled first angle of crystal circle center's axis (in Fig. 6 B-6C represented with chain-dotted line) rotation, will by support construction 603
Mask 650 rotates scheduled second angle around crystal circle center's axis or is both rotated.Similarly, in cutting step
After the completion of 300B is performed, can the relative position of mask 650 and wafer 601 be converted by similar rotation again so that
The expected multiple third cutting line segments 341 to be formed of the alignment of slot 621 on mask 650, then perform cutting step 300C.In shape
Into multiple first, second, third cutting line segments after, other subsequent processing steps can be performed to wafer 601, including but not
It is limited to the step toward division for wafer to be split into multiple regular hexagon wafer units.
It should be noted that in the case where being cut without using mask 650, it can also be by cutting twice step
Period is inserted into spin step to convert the relative position of wafer and lasing light emitter.
Fig. 7 A, which are shown, according to an embodiment of the present disclosure to be used to from wafer obtain showing for multiple regular hexagon wafer units
The flow chart of example property method 700.
In step 701, according to the expection area of the substrate for semiconductor chip, multiple regular hexagon wafer lists are determined
The length of side d of each regular hexagon wafer unit in member.
In a step 702, multiple regular hexagon wafer units are arranged on wafer, enabling from the side that wafer is cut into
The quantity of the regular hexagon wafer unit of a length of d is maximum.
In step 703, foregoing cutting step is performed to wafer, so as to form multiple first on wafer, the
2nd, third cutting line segment.
In step 704, step toward division is performed to wafer, makes wafer along the multiple first cutting line segments, multiple second cuttings
Line segment and the cutting line segment division of multiple thirds, so as to obtain multiple regular hexagon wafer units.
Fig. 7 B further illustrate the flow chart of the cutting step in step 703 according to an embodiment of the present disclosure.
In step 703A, the first cutting step (for example, 300A) is performed, so as to form multiple first cuttings on wafer
Line segment.
In step 703B, rotating wafer at a predetermined angle.
In step 703C, the second cutting step (for example, 300B) is performed, so as to form multiple second cuttings on wafer
Line segment.
In step 703D, rotating wafer at a predetermined angle again.
In step 703E, third cutting step (for example, 300C) is performed, so as to form multiple third cuttings on wafer
Line segment.
After performing step 703E, the step 704 in method 700 can be continued to execute.
Embodiment of the disclosure on wafer by arranging the wafer unit rather than rectangular or square of multiple regular hexagons
Wafer unit, the utilization rate of wafer can be improved in the case where wafer cellar area is identical.Further, since cutting step can
Not use diamond tool, so as to avoid tool wear, and the wafer unit convenient for being cut into regular hexagon.
Word "front", "rear", " top ", " bottom " in specification and claim, " on ", " under " etc., if deposited
If, it is not necessarily used to describe constant relative position for descriptive purposes.It should be appreciated that the word used in this way
Language is interchangeable in appropriate circumstances so that embodiment of the disclosure described herein, for example, can in this institute
Those of description show or other are orientated in other different orientations and operate.
As used in this, word " illustrative " means " be used as example, example or explanation ", not as will be by
" model " accurately replicated.It is not necessarily to be interpreted than other realization methods in the arbitrary realization method of this exemplary description
Preferred or advantageous.Moreover, the disclosure is not by above-mentioned technical field, background technology, invention content or specific embodiment
Given in the theory that is any stated or being implied that goes out limited.
As used in this, word " substantially " mean comprising by design or manufacture the defects of, device or element appearance
Arbitrary small variation caused by difference, environment influence and/or other factors.Word " substantially " also allows by ghost effect, makes an uproar
Caused by sound and the other practical Considerations being likely to be present in practical realization method with perfect or ideal situation
Between difference.
Foregoing description can indicate to be " connected " or " coupled " element together or node or feature.As used herein
, unless explicitly stated otherwise, " connection " means an element/node/feature with another element/node/feature in electricity
Above, it is directly connected mechanically, in logic or in other ways (or direct communication).Similarly, unless explicitly stated otherwise,
" coupling " mean an element/node/feature can with another element/node/feature in a manner of direct or be indirect in machine
On tool, electrically, in logic or in other ways link to allow to interact, even if the two features may not direct
Connection is also such.That is, " coupling " is intended to encompass the direct connection and connection indirectly of element or other feature, including profit
With the connection of one or more intermediary elements.
In addition, just to the purpose of reference, can also be described below it is middle use certain term, and thus not anticipate
Figure limits.For example, unless clearly indicated by the context, be otherwise related to the word " first " of structure or element, " second " and it is other this
Class number word does not imply order or sequence.
It should also be understood that one word of "comprises/comprising" as used herein, illustrates that there are pointed feature, entirety, steps
Suddenly, operation, unit and/or component, but it is not excluded that in the presence of or increase one or more of the other feature, entirety, step, behaviour
Work, unit and/or component and/or combination thereof.
In the disclosure, therefore term " offer " " it is right to provide certain from broadly by covering obtain object all modes
As " including but not limited to " purchase ", " preparation/manufacture ", " arrangement/setting ", " installation/assembling ", and/or " order " object etc..
It should be appreciated by those skilled in the art that the boundary between aforesaid operations is merely illustrative.Multiple operations
Single operation can be combined into, single operation can be distributed in additional operation, and operate can at least portion in time
Divide and overlappingly perform.Moreover, alternative embodiment can include multiple examples of specific operation, and in other various embodiments
In can change operation order.But others are changed, variations and alternatives are equally possible.Therefore, the specification and drawings
It should be counted as illustrative and not restrictive.
In addition, embodiment of the present disclosure can also include the example below：
1st, a kind of method that multiple regular hexagon wafer units are arranged on wafer, which is characterized in that the method includes
Following steps：According to the expection area of the substrate for semiconductor chip, determine every in the multiple regular hexagon wafer unit
The length of side d of one regular hexagon wafer unit；And the multiple regular hexagon wafer unit is arranged on the wafer so that
It can be from the quantity maximum for the regular hexagon wafer unit that the length of side that the wafer is cut into is d.
2nd, method as described in example 1, which is characterized in that the arrangement includes：Cause the multiple regular hexagon wafer
The center of the first regular hexagon wafer unit in unit is overlapped with the center of circle of the wafer, and the multiple regular hexagon is brilliant
Justify the close arrangement centered on the first regular hexagon wafer unit of other regular hexagon wafer units in unit.
3rd, method as described in example 1, which is characterized in that the method further includes：Cutting step, the cutting step
Suddenly discontinuous multiple first cutting line segments are formed on the wafer, each first cutting line segment length is d, wherein, it is described
Multiple first cutting line segments are distributed in one group of first straight line in wafer plane, and one group of first straight line is parallel to each other, and
And separated between adjacent first straight line with the first preset distance L1, one or more first is distributed in every first straight line and cuts
Line segment, and the one or more first cutting line segment in it is adjacent first cutting line segment between with the second preset distance L2 every
It opens, the wafer between adjacent first cutting line segment is not cut.
4th, the method as described in example 3, which is characterized in that the method further includes：The cutting step is repeated, from
And discontinuous multiple second cutting line segments are formed on the wafer；Wherein, each second cutting line segment length is d, described
Multiple second cutting line segments are distributed in one group of second straight line in wafer plane, and one group of second straight line is parallel to each other, phase
It is separated between adjacent second straight line with the first preset distance L1；And one or more second is distributed in every second straight line to cut
Line segment, and the one or more second cutting line segment in it is adjacent second cutting line segment between with the second preset distance L2 every
It opens, the wafer between adjacent second cutting line segment is not cut.
5th, the method as described in example 4, which is characterized in that the method further includes：The cutting step is repeated again
Suddenly, so as to form discontinuous multiple third cutting line segments on the wafer；Wherein, each third cutting line segment length is d,
The multiple third cutting line segment is distributed on one group of third straight line in wafer plane, and one group of third straight line is put down each other
It goes, is separated between adjacent third straight line with the first preset distance L1；And one or more the are distributed on every third straight line
Three cutting line segments, and with the second preset distance between the adjacent third cutting line segment in one or more third cutting line segment
L2 is separated, and the wafer between adjacent third cutting line segment is not cut.
6th, the method according to example 5, which is characterized in that the method further includes step toward division, the division
Step makes the wafer along the multiple first cutting line segment, multiple second cutting line segments and multiple thirds cutting line segment point
It splits, so as to obtain the multiple regular hexagon wafer unit.
7th, the method as described in example 3, which is characterized in that using the laser emitted by least one lasing light emitter to perform
State cutting step.
8th, the method as described in example 3, which is characterized in that during the cutting step is performed, along described one group first
Straight line cuts the wafer.
9th, the method as described in example 7, which is characterized in that at least one lasing light emitter includes multiple lasing light emitters, also,
During the cutting step is performed, each lasing light emitter in the multiple lasing light emitter is simultaneously excited, with concurrently in institute
It states and cutting line segment is formed on the different straight lines in one group of first straight line.
10th, the method as described in example 7, which is characterized in that described at least one sharp during the cutting step is performed
Light source forms cutting line segment on every straight line in one group of first straight line successively.
11st, the method as described in example 7, which is characterized in that described at least one sharp during the cutting step is performed
Light source is periodically excited, so as to sequentially form the cutting line segment separated with the second preset distance L2 on every straight line.
12nd, the method as described in example 11, which is characterized in that the length of side d based on the regular hexagon wafer unit, described
First preset distance L1 and the second preset distance L2 determines period that at least one lasing light emitter is excited.
13rd, the method as described in example 12, which is characterized in that the method further includes：Based on described at least one
Lasing light emitter determines the period that at least one lasing light emitter is excited relative to the movement speed of the wafer.
14th, the method as described in example 7, which is characterized in that the method further includes：In at least one laser
Mask is placed between source and the wafer, discontinuous multiple slots are disposed on the mask, the arrangement of the multiple slot corresponds to
In the arrangement of cutting line segment with to be formed on the wafer, during the cutting step is performed, across the multiple slot
Laser corresponding cutting line segment is formed on the wafer.
15th, the method as described in example 14, which is characterized in that rotation step is further included between two adjacent cutting steps
Suddenly, the spin step includes at least one in the following terms：(1) wafer is rotated about its center axis scheduled first
Angle；Or the mask is surrounded the scheduled second angle of center axis rotation of the wafer by (2).
16th, the method as described in example 14, which is characterized in that judge to work as based on the laser energy reflected by the mask
Whether preceding emitted laser passes through multiple slots on the mask, and described at least one to adjust based on the judgement
The transmission power of lasing light emitter.
17th, the method as described in example 16, which is characterized in that sensed using one or more sensors by the mask
The laser energy of reflection, one or more of sensors are coupled at least one lasing light emitter.
18th, the method as described in example 16, which is characterized in that at least one lasing light emitter is adjusted based on the judgement
Transmission power include：When the laser energy of mask reflection is less than first threshold, at least one lasing light emitter is with the
One power emits laser；And when the laser energy of mask reflection is higher than second threshold, at least one laser
Source emits laser with second power；Wherein, second power is less than first power.
19th, the method as described in example 14, which is characterized in that the mask includes the first alignment mark and second pair of fiducial mark
Note, wherein, the first alignment mark is used for the mask and the wafer alignment, and the second alignment mark is used at least one by described in
A lasing light emitter and the mask alignment.
20th, the method as described in example 14, which is characterized in that do not contacted between the mask and the wafer.
21st, the method as described in example 6, which is characterized in that the step toward division includes applying stress to the wafer.
22nd, the method as described in example 6, which is characterized in that the step toward division includes applying the wafer in extension glue
Film method.
23rd, the method as described in example 7, which is characterized in that the laser is one in infrared laser or ultraviolet laser
Person.
Although some specific embodiments of the disclosure are described in detail by example, the skill of this field
Art personnel it should be understood that above example merely to illustrating rather than in order to limit the scope of the present disclosure.It is disclosed herein
Each embodiment can in any combination, without departing from spirit and scope of the present disclosure.It is to be appreciated by one skilled in the art that can be with
A variety of modifications are carried out to embodiment without departing from the scope and spirit of the disclosure.The scope of the present disclosure is limited by appended claims
It is fixed.
Claims (10)
- A kind of 1. method that multiple regular hexagon wafer units are arranged on wafer, which is characterized in that the method includes following Step：According to the expection area of the substrate for semiconductor chip, each in the multiple regular hexagon wafer unit is being determined just The length of side d of hexagon wafer unit；AndThe multiple regular hexagon wafer unit is arranged on the wafer, enabling the length of side being cut into from the wafer is The quantity of the regular hexagon wafer unit of d is maximum.
- 2. the method as described in claim 1, which is characterized in that the arrangement includes：Cause the multiple regular hexagon wafer The center of the first regular hexagon wafer unit in unit is overlapped with the center of circle of the wafer, and the multiple regular hexagon is brilliant Justify the close arrangement centered on the first regular hexagon wafer unit of other regular hexagon wafer units in unit.
- 3. the method as described in claim 1, which is characterized in that the method further includes：Cutting step, the cutting step form discontinuous multiple first cutting line segments on the wafer, and each first cuts Secant segment length is d, wherein, the multiple first cutting line segment is distributed in one group of first straight line in wafer plane, described One group of first straight line is parallel to each other, and is separated between adjacent first straight line with the first preset distance L1, in every first straight line One or more first is distributed with and cuts line segment, and the adjacent first cutting line segment in the one or more first cutting line segment Between separated with the second preset distance L2, it is adjacent first cutting line segment between wafer be not cut.
- 4. method as claimed in claim 3, which is characterized in that the method further includes：The cutting step is repeated, from And discontinuous multiple second cutting line segments are formed on the wafer；Wherein, each second cutting line segment length is d, and the multiple second cutting line segment is distributed in one group in wafer plane the On two straight lines, one group of second straight line is parallel to each other, is separated between adjacent second straight line with the first preset distance L1；AndOne or more second is distributed in every second straight line and cuts line segment, and in the one or more second cutting line segment It is adjacent second cutting line segment between separated with the second preset distance L2, it is adjacent second cutting line segment between wafer do not cut It cuts.
- 5. method as claimed in claim 4, which is characterized in that the method further includes：The cutting step is repeated again, so as to form discontinuous multiple third cutting line segments on the wafer；Wherein, each third cutting line segment length is d, and the multiple third cutting line segment is distributed in one group in wafer plane the On three straight lines, one group of third straight line is parallel to each other, is separated between adjacent third straight line with the first preset distance L1；AndOne or more third cutting line segments are distributed on every third straight line, and in one or more third cutting line segment Adjacent third cutting line segment between separated with the second preset distance L2, the wafer between adjacent third cutting line segment is not cut It cuts.
- 6. method as claimed in claim 3, which is characterized in that using the laser emitted by least one lasing light emitter to perform State cutting step.
- 7. method as claimed in claim 6, which is characterized in that the method further includes：Mask is placed between at least one lasing light emitter and the wafer, is disposed on the mask discontinuous multiple Slot, the arrangement of the multiple slot correspond to the arrangement of cutting line segment with to be formed on the wafer, are performing the cutting During step, the laser across the multiple slot forms corresponding cutting line segment on the wafer.
- 8. the method for claim 7, which is characterized in that judged based on the laser energy reflected by the mask current Whether the laser emitted passes through multiple slots on the mask, and described at least one sharp to adjust based on the judgement The transmission power of light source.
- 9. method as claimed in claim 8, which is characterized in that at least one lasing light emitter is adjusted based on the judgement Transmission power includes：When the laser energy of mask reflection is less than first threshold, at least one lasing light emitter is emitted with the first power Laser；AndWhen the laser energy of mask reflection is higher than second threshold, at least one lasing light emitter is emitted with the second power Laser；Wherein, second power is less than first power.
- 10. the method for claim 7, which is characterized in that do not contacted between the mask and the wafer.
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| CN201810061238.3A CN108257914A (en) | 2018-01-23 | 2018-01-23 | A kind of method that multiple regular hexagon wafer units are arranged on wafer |
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|---|---|---|---|
| CN201810061238.3A CN108257914A (en) | 2018-01-23 | 2018-01-23 | A kind of method that multiple regular hexagon wafer units are arranged on wafer |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5341024A (en) * | 1992-07-17 | 1994-08-23 | Lsi Logic Corporation | Method of increasing the layout efficiency of dies on a wafer, and increasing the ratio of I/O area to active area per die |
| US6030885A (en) * | 1997-04-18 | 2000-02-29 | Vlsi Technology, Inc. | Hexagonal semiconductor die, semiconductor substrates, and methods of forming a semiconductor die |
| US20080220206A1 (en) * | 2007-03-06 | 2008-09-11 | Ken Jian Ming Wang | Semiconductor die for increasing yield and usable wafer area |
-
2018
- 2018-01-23 CN CN201810061238.3A patent/CN108257914A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5341024A (en) * | 1992-07-17 | 1994-08-23 | Lsi Logic Corporation | Method of increasing the layout efficiency of dies on a wafer, and increasing the ratio of I/O area to active area per die |
| US6030885A (en) * | 1997-04-18 | 2000-02-29 | Vlsi Technology, Inc. | Hexagonal semiconductor die, semiconductor substrates, and methods of forming a semiconductor die |
| US20080220206A1 (en) * | 2007-03-06 | 2008-09-11 | Ken Jian Ming Wang | Semiconductor die for increasing yield and usable wafer area |
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