CN108257261A - A kind of access control system and implementation method based on bore hole 3D display - Google Patents
A kind of access control system and implementation method based on bore hole 3D display Download PDFInfo
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- CN108257261A CN108257261A CN201711479946.0A CN201711479946A CN108257261A CN 108257261 A CN108257261 A CN 108257261A CN 201711479946 A CN201711479946 A CN 201711479946A CN 108257261 A CN108257261 A CN 108257261A
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- G—PHYSICS
- G07—CHECKING-DEVICES
- G07C—TIME OR ATTENDANCE REGISTERS; REGISTERING OR INDICATING THE WORKING OF MACHINES; GENERATING RANDOM NUMBERS; VOTING OR LOTTERY APPARATUS; ARRANGEMENTS, SYSTEMS OR APPARATUS FOR CHECKING NOT PROVIDED FOR ELSEWHERE
- G07C9/00—Individual registration on entry or exit
- G07C9/00174—Electronically operated locks; Circuits therefor; Nonmechanical keys therefor, e.g. passive or active electrical keys or other data carriers without mechanical keys
- G07C9/00563—Electronically operated locks; Circuits therefor; Nonmechanical keys therefor, e.g. passive or active electrical keys or other data carriers without mechanical keys using personal physical data of the operator, e.g. finger prints, retinal images, voicepatterns
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- Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
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Abstract
The invention discloses a kind of access control systems based on bore hole 3D display, including FPGA, left camera, right camera, ARM, 3D LCD and gate inhibition's peripheral equipment, the left camera and the right camera are connect with the FPGA, the FPGA is connect with the ARM, the 3D LCD are connect with the FPGA, and the ARM is connect with gate inhibition's peripheral equipment.The invention also discloses a kind of gate inhibition's implementation methods based on bore hole 3D display.The present invention relates to intelligent entrance guard technical fields, a kind of access control system and implementation method based on bore hole 3D display, using the function of ARM compatibility gate inhibitions, image data is acquired by dual camera, it is handled using the FPGA image datas acquired to dual camera, bore hole 3D effect is shown by 3D LCD, reduces the erroneous judgement to recognition of face, compared with existing 2D LCD, recognition of face reliability is stronger.
Description
Technical field
The present invention relates to intelligent entrance guard technical field more particularly to a kind of access control systems and realization based on bore hole 3D display
Method.
Background technology
At present, the display that visual door control system uses in the market is all that traditional 2D is shown, bore hole 3D not yet occur can
Depending on gate inhibition's product.Bore hole display technology is applied to intelligent district access control system, accelerates the novel display technology of access control system
Development.Traditional gate inhibition acquires image using an imaging sensor, due to can not only have from an angle acquisition, the image of acquisition
Parallax information, the relative position relation of reconstructed object that cannot be three-dimensional when image is being shown on 2D LCD.And bore hole solid is shown
The information such as the structure, curvature and the depth of field of complex scene can be provided, and can be according to the improvement pair of these information by showing the image of technology acquisition
The judgement of movement.Application of the bore hole 3D technology in intelligent entrance guard will bring user new visual experience, allow user without wearing
3D glasses just can immersively experience the exchange of " face-to-face " each other.Bore hole stereoscopic display gate inhibition's technology promotes Intelligent human-face
The development of recognition access control system technology.Application of the recognition of face in some special occasions access control systems is also increasingly paid attention to.But
Image for two-dimension human face identification is the facial image acquired from some special angle, is illuminated by the light the influence for waiting many factors,
Erroneous judgement is susceptible to during identification.Bore hole 3D gate inhibition technology simultaneously respectively adopts facial image from two visual angles
Collection in identification process, can increase the reliability of recognition of face by left and right two groups of image correlation analysis.
Invention content
In order to solve the above-mentioned technical problem, the object of the present invention is to provide a kind of highly reliable based on bore hole 3D display
Access control system.
In order to solve the above-mentioned technical problem, the object of the present invention is to provide a kind of highly reliable based on bore hole 3D display
Gate inhibition's implementation method.
The technical solution adopted in the present invention is：
A kind of access control system based on bore hole 3D display, including FPGA, left camera, right camera, ARM, 3D LCD and
Gate inhibition's peripheral equipment, the left camera and the right camera are connect with the FPGA, and the FPGA is connect with the ARM,
The 3D LCD are connect with the FPGA, and the ARM is connect with gate inhibition's peripheral equipment.
As being further improved for said program, the system also includes the first SDRAM memories and the 2nd SDRAM to store
Device, first SDRAM memory and second SDRAM memory are connect with the FPGA.
As being further improved for said program, the FPGA includes system clock and reseting module, the first image data
Receiving module, the second image data receiving module, first write data simultaneous module, second write data simultaneous module, the first SDRAM
Cache module, the 2nd SDRAM cache modules, the first reading data simultaneous module, the second reading data simultaneous module and 3D LCD are shown
Drive module, the system clock and reseting module and the first image data receiving module, the second image data receiving module,
One writes data simultaneous module, second writes data simultaneous module, first read data simultaneous module, second read data simultaneous module and 3D
LCD driver modules connect, and described first image data reception module is write data simultaneous module with described first and connect, described
First writes data simultaneous module connect with the first SDRAM cache modules, the first SDRAM cache modules and described first
Data simultaneous module connection is read, the first reading data simultaneous module is connect with the 3D LCD driver modules, and described the
Two image data receiving modules are write data simultaneous module with described second and are connect, and described second writes data simultaneous module and described the
Two SDRAM cache modules connect, and the 2nd SDRAM cache modules are read data simultaneous module with described second and connect, and described the
Second reading data simultaneous module is connect with the 3D LCD driver modules, the first SDRAM cache modules and described first
SDRAM memory connects, and the 2nd SDRAM cache modules are connect with second SDRAM memory.
As being further improved for said program, described first image data reception module is connect with the left camera,
The second image data receiving module is connect with the right camera.
As being further improved for said program, the FPGA is configured with JTAG/AS ports.
As being further improved for said program, the ARM is configured with SD card, the ARM be configured with USB_OTG interfaces,
MAX232 serial ports and BOOT configuration switches.
As being further improved for said program, gate inhibition's peripheral equipment includes loudspeaker, electronic lock, identification mould
Block, microphone and intercom.
As being further improved for said program, the system also includes 2D LCD, the 2D LCD and FPGA connects
It connects.
A kind of gate inhibition's implementation method based on bore hole 3D display, suitable for a kind of door based on bore hole 3D display as described above
Access control system, including step：
S1, left camera and right camera acquire left eye image data and right eye image data in real time respectively, and will acquisition
Left eye image data and right eye image data be sent to FPGA；
After S2, FPGA receive left eye image data and right eye image data, by blending algorithm to left eye image data
It is handled with right eye image data, obtains fusion image data, and fusion image data is sent to 3D LCD and is shown.
As being further improved for said program, the step S2 includes sub-step：
S21, the first image data receiving module receive the left eye image data that left camera is sent, and by left-eye image number
Data simultaneous module is write according to being sent to first, meanwhile, the second image data receiving module receives the right eye figure that right camera is sent
As data, and right eye image data is sent to second and writes data simultaneous module；
S22, first, which writes data simultaneous module, receives left eye image data and second and writes data simultaneous module and receive the right side
After eye image data, the first SDRAM caching moulds are sent to after processing is synchronized to left eye image data and right eye image data
Block and the 2nd SDRAM cache modules；
S23, the first SDRAM cache modules and the 2nd SDRAM cache modules are respectively received the left-eye image number after synchronizing
According to after right eye image data, the first SDRAM memory is written in synchronous left eye image data by the first SDRAM cache modules,
First reads the left eye image data in data simultaneous module the first SDRAM memory of reading, and the 2nd SDRAM cache modules will be synchronous
Right eye image data be written the second SDRAM memory, second read data simultaneous module read the second SDRAM memory in the right side
Eye image data；
S24, first read data simultaneous module and second read data simultaneous module according to system clock and reseting module when
Clock signal by the left eye image data received and right eye image data respectively to carrying out second synchronization processing, and by second synchronization
Left eye image data that treated and right eye image data are sent to 3D LCD driver module fusion treatments, and 3D LCD are shown
Drive module is sent to 3D LCD in the case where system clock is synchronous with reseting module, by fusion image data and shows.
The beneficial effects of the invention are as follows：
A kind of access control system based on bore hole 3D display using the function of ARM compatibility gate inhibitions, is acquired by dual camera and schemed
It as data, is handled using the FPGA image datas acquired to dual camera, bore hole 3D effect is shown by 3D LCD, dropped
The low erroneous judgement to recognition of face, compared with existing 2D LCD, recognition of face reliability is stronger.
A kind of gate inhibition's implementation method based on bore hole 3D display using the function of ARM compatibility gate inhibitions, is adopted by dual camera
Collect image data, handled using the FPGA image datas acquired to dual camera, show that bore hole 3D is imitated by 3D LCD
Fruit reduces the erroneous judgement to recognition of face, and compared with existing 2D LCD, recognition of face reliability is stronger.
Description of the drawings
The specific embodiment of the present invention is described further below in conjunction with the accompanying drawings：
Fig. 1 is a kind of access control system structure diagram based on bore hole 3D display of the present invention；
Fig. 2 is a kind of gate inhibition's implementation method flow chart based on bore hole 3D display of the present invention；
Fig. 3 is a kind of gate inhibition's implementation method blending algorithm flow chart based on bore hole 3D display of the present invention.
Specific embodiment
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the application can phase
Mutually combination.
Fig. 1 is a kind of access control system structure diagram based on bore hole 3D display of the present invention, and with reference to Fig. 1, one kind is based on bore hole
The access control system of 3D display, including FPGA, left camera, right camera, ARM, 3D LCD and gate inhibition's peripheral equipment.Wherein, it is left
Camera and right camera are connect with FPGA, and real-time the image collected data are sent to FPGA processing, 3D LCD and FPGA
Connection, for showing bore hole 3D rendering.FPGA is connect with ARM, and ARM is connect with gate inhibition's peripheral equipment.In the present embodiment, outside gate inhibition
Peripheral equipment includes loudspeaker, electronic lock, identification module, microphone and intercom.
Specifically, the system further includes the first SDRAM memory and the second SDRAM memory, the first SDRAM memory and
Second SDRAM memory is connect with FPGA, and the first SDRAM memory is used to cache the left-eye image number of left camera acquisition
According to the second SDRAM memory is used to cache the right eye image data of right camera acquisition.
Specifically, in the present embodiment, FPGA includes system clock and reseting module, the first image data receiving module, the
Two image data receiving modules, first write data simultaneous module, second write data simultaneous module, the first SDRAM cache modules,
Two SDRAM cache modules, first read data simultaneous module, the second reading data simultaneous module and 3D LCD driver modules, are
System clock and reseting module and the first image data receiving module, the second image data receiving module, first write the synchronous mould of data
Block, second write data simultaneous module, the first reading data simultaneous module, the second reading data simultaneous module and 3D LCD display driving moulds
Block connects, and the first image data receiving module is write data simultaneous module with first and connect, and first writes data simultaneous module and first
SDRAM cache modules connect, and the first SDRAM cache modules are connect with the first reading data simultaneous module, and first, which reads data, synchronizes mould
Block is connect with 3D LCD driver modules, and the second image data receiving module is write data simultaneous module with second and connect, and second
It writes data simultaneous module to connect with the 2nd SDRAM cache modules, the 2nd SDRAM cache modules and second read data simultaneous module company
It connects, the second reading data simultaneous module is connect with 3D LCD driver modules, and the first SDRAM cache modules are deposited with the first SDRAM
Reservoir connects, and the 2nd SDRAM cache modules are connect with the second SDRAM memory.Wherein, the first image data receiving module and a left side
Camera connects, and the second image data receiving module is connect with right camera.
Specifically, the FPGA of the present embodiment is configured with JTAG/AS ports, ARM be configured with SD card, USB_OTG interfaces,
MAX232 serial ports and BOOT configuration switches.According to the type and model of gate inhibition's peripheral equipment, good corresponding system is configured in PC machine
System and driving, and switch option and installment mode is configured by BOOT, by USB_OTG interfaces and MAX232 serial ports, WinCE,
Android or linux operating systems are from the burned ARM of SD card.For the power consumption of reduction system, the power-supply ripple amplitude of output is limited,
Ensure the stabilization of circuit system, keep the integrality of signal, in the present embodiment, devise independent confession to FPGA and ARM respectively
Power supply.
As being further improved for above system embodiment, which further includes 2D LCD, and 2D LCD are connect with FPGA, this
Invention access control system had both supported bore hole 3D rendering to show or support 2D images to show.
Fig. 2 is a kind of gate inhibition's implementation method flow chart based on bore hole 3D display of the present invention, and with reference to Fig. 2, one kind is based on naked
Gate inhibition's implementation method of eye 3D display, suitable for a kind of above-mentioned access control system based on bore hole 3D display, the method includes steps
Suddenly：
S1, left camera and right camera acquire left eye image data and right eye image data in real time respectively, and will acquisition
Left eye image data and right eye image data be sent to FPGA；
After S2, FPGA receive left eye image data and right eye image data, by blending algorithm to left eye image data
It is handled with right eye image data, obtains fusion image data, and fusion image data is sent to 3D LCD and is shown.
Fig. 3 is a kind of gate inhibition's implementation method blending algorithm flow chart based on bore hole 3D display of the present invention, with reference to Fig. 2 and figure
3, step S2 include sub-step：
S21, the first image data receiving module receive the left eye image data that left camera is sent, and by left-eye image number
Data simultaneous module is write according to being sent to first, meanwhile, the second image data receiving module receives the right eye figure that right camera is sent
As data, and right eye image data is sent to second and writes data simultaneous module.
S22, first, which writes data simultaneous module, receives left eye image data and second and writes data simultaneous module and receive the right side
After eye image data, the first SDRAM caching moulds are sent to after processing is synchronized to left eye image data and right eye image data
Block and the 2nd SDRAM cache modules；The present invention writes data simultaneous module using first with asynchronous clock and second to write data same
Module is walked to solve the problems, such as image data asynchronous transmission between image data receiving module and SDRAM cache modules.
S23, the first SDRAM cache modules and the 2nd SDRAM cache modules are respectively received the left-eye image number after synchronizing
According to after right eye image data, the first SDRAM memory is written in synchronous left eye image data by the first SDRAM cache modules,
First reads the left eye image data in data simultaneous module the first SDRAM memory of reading, and the 2nd SDRAM cache modules will be synchronous
Right eye image data be written the second SDRAM memory, second read data simultaneous module read the second SDRAM memory in the right side
Eye image data.
S24, first read data simultaneous module and second read data simultaneous module according to system clock and reseting module when
Clock signal by the left eye image data received and right eye image data respectively to carrying out second synchronization processing, and by second synchronization
Left eye image data that treated and right eye image data are sent to 3D LCD driver module fusion treatments, and 3D LCD are shown
Drive module is sent to 3D LCD in the case where system clock is synchronous with reseting module, by fusion image data and shows.According to
The timing waveform and time sequence parameter that 3D LCD are shown generate row, field sync signal, and in the effective display area domain of 3D LCD,
The same period of 3D LCD pixel clocks clk_lcd is triggered by same enable signal rdf_req, by left-eye image and right eye
The data of image respective pixel are sent to 3D LCD driver modules simultaneously.Due to simultaneously into 3D LCD driver modules
Data there are two, the respectively color data of left-eye image and eye image respective pixel, so can be former according to different fusions
Reason, selectivity display and shielding two color data in one or by three color data of two pixel datas according to Asia
After the combination of pixel fusion principle, 3D LCD are shown in, realize the effect of bore hole 3D.
In the present embodiment, 50MHz clocks are inputted from the global clock pin of FPGA, drive global clock network, are fanned out to and are
The clock for the different frequency united needed for logical algorithm generates the reset signal for being synchronized with clock.50MHz clocks are divided through counting
Afterwards, the clock for meeting camera configuration frequency is generated, the configuration of SDRAM memory data is completed under the synchronization of the clock, just
Beginningization camera.After the completion of camera initialization, by the work clock driving acquisition image data of 24MHz, and by the number of acquisition
According to being sent to FPGA.
A kind of gate inhibition's implementation method based on bore hole 3D display using the function of ARM compatibility gate inhibitions, is adopted by dual camera
Collect image data, handled using the FPGA image datas acquired to dual camera, show that bore hole 3D is imitated by 3D LCD
Fruit reduces the erroneous judgement to recognition of face, and compared with existing 2D LCD, recognition of face reliability is stronger.
It is that the preferable of the present invention is implemented to be illustrated, but the invention is not limited to the implementation above
Example, those skilled in the art can also make various equivalent variations under the premise of without prejudice to spirit of the invention or replace
It changes, these equivalent deformations or replacement are all contained in the application claim limited range.
Claims (10)
1. a kind of access control system based on bore hole 3D display, which is characterized in that it include FPGA, left camera, right camera,
ARM, 3D LCD and gate inhibition's peripheral equipment, the left camera and the right camera are connect with the FPGA, the FPGA with
The ARM connections, the 3D LCD are connect with the FPGA, and the ARM is connect with gate inhibition's peripheral equipment.
2. a kind of access control system based on bore hole 3D display according to claim 1, which is characterized in that the system is also wrapped
The first SDRAM memory and the second SDRAM memory are included, first SDRAM memory and second SDRAM memory are equal
It is connect with the FPGA.
3. a kind of access control system based on bore hole 3D display according to claim 2, which is characterized in that the FPGA includes
System clock and reseting module, the first image data receiving module, the second image data receiving module, first write the synchronous mould of data
Block, second write data simultaneous module, the first SDRAM cache modules, the 2nd SDRAM cache modules, first read data simultaneous module,
Second reading data simultaneous module and 3D LCD driver modules, the system clock and reseting module connect with the first image data
Receive module, the second image data receiving module, first write data simultaneous module, second write data simultaneous module, first read data
Synchronization module, the second reading data simultaneous module are connected with 3D LCD driver modules, described first image data reception module
Data simultaneous module is write with described first to connect, described first writes data simultaneous module connects with the first SDRAM cache modules
Connect, the first SDRAM cache modules with described first reading data simultaneous module connect, it is described first read data simultaneous module and
The 3D LCD driver modules connection, the second image data receiving module write data simultaneous module company with described second
Connect, described second writes data simultaneous module connect with the 2nd SDRAM cache modules, the 2nd SDRAM cache modules with
Described second reads data simultaneous module connection, and described second reads data simultaneous module connects with the 3D LCD driver modules
Connect, the first SDRAM cache modules are connect with first SDRAM memory, the 2nd SDRAM cache modules with it is described
Second SDRAM memory connects.
A kind of 4. access control system based on bore hole 3D display according to claim 3, which is characterized in that described first image
Data reception module is connect with the left camera, and the second image data receiving module is connect with the right camera.
A kind of 5. access control system based on bore hole 3D display according to claim 4, which is characterized in that the FPGA configurations
There are JTAG/AS ports.
A kind of 6. access control system based on bore hole 3D display according to claim 5, which is characterized in that the ARM configurations
There is SD card, the ARM is configured with USB_OTG interfaces, MAX232 serial ports and BOOT configuration switches.
A kind of 7. access control system based on bore hole 3D display according to claim 6, which is characterized in that the gate inhibition periphery
Equipment includes loudspeaker, electronic lock, identification module, microphone and intercom.
A kind of 8. access control system based on bore hole 3D display according to any one of claims 1 to 7, which is characterized in that institute
The system of stating further includes 2D LCD, and the 2D LCD are connect with the FPGA.
9. a kind of gate inhibition's implementation method based on bore hole 3D display, suitable for a kind of such as base of claim 1 to 8 any one of them
In the access control system of bore hole 3D display, which is characterized in that it includes step：
S1, left camera and right camera acquisition left eye image data and right eye image data in real time respectively, and by a left side for acquisition
Eye image data and right eye image data are sent to FPGA；
After S2, FPGA receive left eye image data and right eye image data, by blending algorithm to left eye image data and the right side
Eye image data is handled, and obtains fusion image data, and fusion image data is sent to 3D LCD and is shown.
10. a kind of gate inhibition's implementation method based on bore hole 3D display according to claim 6,
It is characterized in that, the step S2 includes sub-step：
S21, the first image data receiving module receives the left eye image data that left camera is sent, and left eye image data is sent out
It gives first and writes data simultaneous module, meanwhile, the second image data receiving module receives the eye image number that right camera is sent
According to, and right eye image data is sent to second and writes data simultaneous module；
S22, first, which writes data simultaneous module, receives left eye image data and second and writes data simultaneous module and receive right eye figure
As after data, left eye image data and right eye image data are synchronized be sent to after processing the first SDRAM cache modules and
2nd SDRAM cache modules；
S23, the first SDRAM cache modules and the 2nd SDRAM cache modules be respectively received the left eye image data after synchronizing and
After right eye image data, the first SDRAM memory is written in synchronous left eye image data by the first SDRAM cache modules, and first
It reads data simultaneous module and reads left eye image data in the first SDRAM memory, the 2nd SDRAM cache modules are by the synchronous right side
The second SDRAM memory is written in eye image data, and second reads the right eye figure in data simultaneous module the second SDRAM memory of reading
As data；
S24, first, which reads data simultaneous module and second, reads data simultaneous module according to the clock of system clock and reseting module letter
Number respectively to the left eye image data received and right eye image data are carried out second synchronization processing, and second synchronization is handled
Left eye image data and right eye image data afterwards is sent to 3D LCD driver module fusion treatments, 3DLCD display drivings
Module is sent to 3D LCD in the case where system clock is synchronous with reseting module, by fusion image data and shows.
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| CN102520901A (en) * | 2011-12-21 | 2012-06-27 | Tcl集团股份有限公司 | Data acquisition and storage method, data acquisition and storage system and data acquisition and storage device for naked eye 3D (three-dimensional) display |
| CN102636878A (en) * | 2012-03-16 | 2012-08-15 | 中山大学 | Naked-eye stereoscopic display system and method for realizing naked-eye stereoscopic display |
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Application publication date: 20180706 |