CN108235558B - Circuit board structure and manufacturing method thereof - Google Patents
Circuit board structure and manufacturing method thereof Download PDFInfo
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- CN108235558B CN108235558B CN201611150983.2A CN201611150983A CN108235558B CN 108235558 B CN108235558 B CN 108235558B CN 201611150983 A CN201611150983 A CN 201611150983A CN 108235558 B CN108235558 B CN 108235558B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0338—Layered conductor, e.g. layered metal substrate, layered finish layer, layered thin film adhesion layer
Abstract
The invention relates to a circuit board structure and a manufacturing method thereof. The circuit board structure comprises an inner layer circuit structure and a first layer-adding circuit structure. The inner-layer circuit structure comprises a core layer, a first patterned circuit layer, a second patterned circuit layer and a conductive through hole, wherein the core layer is provided with an upper surface and a lower surface which are opposite to each other, the first patterned circuit layer is arranged on the upper surface, the second patterned circuit layer is arranged on the lower surface, and the conductive through hole is used for connecting the first patterned circuit layer and the second patterned circuit layer. The first build-up circuit structure is disposed on the upper surface of the core layer and covers the first patterned circuit layer, wherein the first build-up circuit structure has at least one groove, the groove exposes a portion of the first patterned circuit layer, and a cross-sectional profile of a top surface edge of the portion of the first patterned circuit layer exposed by the groove is a curved surface. The circuit board structure can have better wiring flexibility.
Description
Technical Field
The present invention relates to a circuit board structure and a method for manufacturing the same, and more particularly, to a circuit board structure having a groove and a method for manufacturing the same.
Background
Generally, to fabricate a circuit board structure with a recess, an alignment copper layer is fabricated on a core layer of an inner circuit structure, and the purpose is to: in the subsequent process of forming the groove by laser ablation of the circuit structure, the alignment copper layer can be regarded as a laser barrier layer to avoid excessive ablation of the circuit structure, and can also be regarded as a laser alignment pattern to facilitate the laser ablation procedure. However, since the alignment copper layer is directly formed on the core layer of the inner circuit layer, the circuit layout of the core layer is limited, and the wiring flexibility of the core layer is reduced.
Disclosure of Invention
The invention provides a circuit board structure which can have better wiring flexibility.
The invention provides a manufacturing method of a circuit board structure, which is used for manufacturing the circuit board structure.
The circuit board structure comprises an inner layer circuit structure and a first layer-adding circuit structure. The inner-layer circuit structure comprises a core layer, a first patterned circuit layer, a second patterned circuit layer and a conductive through hole, wherein the core layer is provided with an upper surface and a lower surface which are opposite to each other, the first patterned circuit layer is arranged on the upper surface, the second patterned circuit layer is arranged on the lower surface, and the conductive through hole is used for connecting the first patterned circuit layer and the second patterned circuit layer. The first build-up circuit structure is disposed on the upper surface of the core layer and covers the first patterned circuit layer, wherein the first build-up circuit structure at least has a groove, the groove exposes a portion of the first patterned circuit layer, and a cross-sectional profile of a top surface edge of the portion of the first patterned circuit layer exposed by the groove is a curved surface.
In an embodiment of the invention, the first build-up circuit structure includes an inner dielectric layer, at least one first patterned conductive layer, and at least one first conductive via structure penetrating the inner dielectric layer and the first dielectric layer. The first patterned conductive layer and the first dielectric layer are sequentially stacked on the inner dielectric layer, and the first patterned conductive layer is electrically connected with the first patterned circuit layer through the first conductive through hole structure.
In an embodiment of the invention, the recess further exposes a portion of the interlayer dielectric layer. The inner dielectric layer has a first inner surface and a second inner surface. The first inner surface is higher than the second inner surface, the groove exposes the second inner surface, and the top surface of the part of the first patterned circuit layer exposed by the groove is higher than the second inner surface.
In an embodiment of the invention, the recess further exposes a portion of the interlayer dielectric layer. The inner dielectric layer has a first inner surface and a second inner surface, the first inner surface is higher than the second inner surface, the second inner surface is exposed by the groove, and the top surface of the part of the first patterned circuit layer exposed by the groove is aligned with the second inner surface.
In an embodiment of the invention, the groove further exposes a portion of the core layer of the inner circuit structure. The upper surface of the core layer includes a first upper surface and a second upper surface. The groove exposes the first upper surface, the second upper surface is higher than the first upper surface, and the top surface of the part of the first patterned circuit layer exposed by the groove is higher than the first upper surface.
In an embodiment of the invention, the groove further exposes a portion of the upper surface of the core layer of the inner-layer circuit structure, and the bottom surface of the portion of the first patterned circuit layer exposed by the groove is aligned with the portion of the upper surface of the core layer.
In an embodiment of the invention, the portion of the first patterned circuit layer exposed by the groove includes at least one pad, at least one circuit, or a combination thereof.
In an embodiment of the invention, the circuit board structure further includes: the first patterned solder mask layer is at least arranged on the first surface of the first build-up circuit structure relatively far away from the inner layer circuit structure and the part of the first patterned circuit layer exposed by the groove.
In an embodiment of the invention, the circuit board structure further includes: the second build-up circuit structure and the second patterned solder mask layer. The second build-up circuit structure is arranged on the lower surface of the core layer and covers the second patterned circuit layer. The second patterned solder mask layer is disposed on a second surface of the second build-up circuit structure relatively far away from the inner circuit structure.
In an embodiment of the invention, the second build-up circuit structure includes at least one second dielectric layer, at least one second patterned conductive layer, and at least one second conductive via structure penetrating the second dielectric layer. The second dielectric layer and the second patterned conductive layer are sequentially stacked on the lower surface of the core layer, and the second patterned conductive layer is electrically connected with the second patterned circuit layer through the second conductive through hole structure.
The manufacturing method of the circuit board structure comprises the following manufacturing steps. An inner layer circuit structure is provided, and the inner layer circuit structure comprises a core layer, a first patterned circuit layer, a second patterned circuit layer and a conductive through hole, wherein the core layer is provided with an upper surface and a lower surface which are opposite to each other, the first patterned circuit layer is arranged on the upper surface, the second patterned circuit layer is arranged on the lower surface, and the conductive through hole is communicated with the first patterned circuit layer and the second patterned circuit layer. And performing a build-up procedure to press the first build-up circuit structure on the first patterned circuit layer, wherein the first build-up circuit layer at least comprises an inner dielectric layer, and the inner dielectric layer directly covers the upper surface of the core layer and the first patterned circuit layer. Removing part of the first build-up circuit layer to form an opening extending from a first surface of the first build-up circuit layer relatively far away from the inner layer circuit structure to part of the inner layer dielectric layer, wherein the opening exposes a first inner surface of the inner layer dielectric layer. The first inner surface of the interlayer dielectric layer exposed by the opening is subjected to a sand blasting procedure to remove at least part of the interlayer dielectric layer exposed by the opening, so as to form a groove exposing at least part of the first patterned circuit layer.
In an embodiment of the invention, the first build-up circuit structure further includes at least one first dielectric layer, at least one first patterned conductive layer, and at least one first conductive via structure penetrating the inner dielectric layer and the first dielectric layer. The first patterned conductive layer and the first dielectric layer are sequentially stacked on the inner dielectric layer, and the first patterned conductive layer is electrically connected with the first patterned circuit layer through the first conductive through hole structure.
In an embodiment of the invention, the recess further exposes the second inner surface of the interlayer dielectric layer. The first inner surface is higher than the second inner surface, and the top surface of the portion of the first patterned circuit layer exposed by the recess is higher than the second inner surface.
In an embodiment of the invention, a cross-sectional profile of an edge of a top surface of the portion of the first patterned circuit layer exposed by the groove is a curved surface.
In an embodiment of the invention, the step of removing the portion of the first build-up circuit layer includes performing a depth-setting fishing process or a sand-blasting process on the first build-up circuit layer.
In an embodiment of the invention, the sand blasting procedure is performed on the first inner surface of the interlayer dielectric layer exposed by the opening to completely remove the interlayer dielectric layer and a portion of the core layer exposed by the opening, so as to form a groove exposing a portion of the first patterned circuit layer and the first upper surface of the core layer. The upper surface of the core layer includes a first upper surface and a second upper surface, the second upper surface is higher than the first upper surface, and a top surface of a portion of the first patterned circuit layer exposed by the groove is higher than the first upper surface.
In an embodiment of the invention, a cross-sectional profile of an edge of a top surface of the portion of the first patterned circuit layer exposed by the groove is a curved surface.
In an embodiment of the invention, the pair of grooves further exposes the second inner surface of the interlayer dielectric layer. The first inner surface is higher than the second inner surface, and the top surface of the part of the first patterned circuit layer exposed by the groove is level with the second inner surface.
In an embodiment of the invention, the sand blasting procedure is performed on the first inner surface of the interlayer dielectric layer exposed by the opening to completely remove the interlayer dielectric layer exposed by the opening, so as to form a groove exposing a portion of the first patterned circuit layer and a portion of the upper surface of the core layer. The top surface of the portion of the first patterned circuit layer exposed by the groove is higher than the upper surface of the core layer exposed.
In an embodiment of the invention, the sand blasting procedure is performed on the first inner surface of the interlayer dielectric layer exposed by the opening to completely remove the interlayer dielectric layer exposed by the opening, so as to form a groove exposing a portion of the first patterned circuit layer and a portion of the upper surface of the core layer. The bottom surface of the part of the first patterned circuit layer exposed by the groove is cut to be flush with the upper surface.
In an embodiment of the invention, the portion of the first patterned circuit layer exposed by the groove includes at least one pad, at least one circuit, or a combination thereof.
In an embodiment of the invention, the method for manufacturing the circuit board structure further includes: after forming the groove exposing at least part of the first patterned circuit layer, forming the first patterned solder mask layer on at least the first surface of the first build-up circuit structure relatively far away from the inner circuit structure and the part of the first patterned circuit layer exposed by the groove.
In an embodiment of the invention, the method for manufacturing the circuit board structure further includes: when the layer adding procedure is carried out, simultaneously pressing a second layer adding circuit structure on the second patterned circuit layer; and forming a second patterned solder mask layer on a second surface of the second build-up circuit structure relatively far away from the inner circuit structure.
In an embodiment of the invention, the second build-up circuit structure includes at least one second dielectric layer, at least one second patterned conductive layer, and at least one second conductive via structure penetrating the second dielectric layer. The second dielectric layer and the second patterned conductive layer are sequentially stacked on the lower surface of the core layer, and the second patterned conductive layer is electrically connected with the second patterned circuit layer through the second conductive through hole structure.
Based on the above, in the manufacturing process of the circuit board structure of the invention, the inner dielectric layer exposed by the opening is at least partially removed by the sand blasting procedure, so as to form the groove exposing at least a portion of the first patterned circuit layer. Therefore, the formation of the groove of the invention does not need to arrange an alignment copper layer and does not influence the circuit layout of the inner layer circuit structure, so that the circuit board structure formed by the invention can provide larger layout space.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to fig. 1E are schematic cross-sectional views illustrating a method for manufacturing a circuit board structure according to an embodiment of the invention.
Fig. 2 is an enlarged view of a pad region of the circuit board structure shown in fig. 1D.
Fig. 3 is a partial top view of the circuit board structure of fig. 1E.
Fig. 4A to 4C are enlarged views of the pad region of the circuit board structure of fig. 1D at different sandblasting depths, respectively.
Fig. 5A to 5C are schematic cross-sectional views of the pad region of the circuit board structure of fig. 1E at different sandblasting depths, respectively.
Description of reference numerals:
100: a circuit board structure;
110: an inner layer circuit structure;
111: an upper surface;
111 a: a first upper surface;
111 b: a second upper surface;
112: a core layer;
113: a lower surface;
114: a first patterned circuit layer;
114 a: a top surface;
114 b: a bottom surface;
116: a second patterned circuit layer;
118: a conductive via;
120: a first build-up circuit layer;
121: a first surface;
122: an inner dielectric layer;
122 a: a first inner surface;
122b, 122 b': a second inner surface;
124: a first patterned conductive layer;
126: a first dielectric layer;
128: a first conductive via structure;
130: a second build-up line structure;
131: a second surface;
132: a second dielectric layer;
134: a second patterned conductive layer;
136: a second conductive via structure;
140: a first patterned solder mask layer;
150: a second patterned solder mask layer;
c: a groove;
o: an opening;
t: a line;
p: and a pad.
Detailed Description
Fig. 1A to fig. 1E are schematic cross-sectional views illustrating a method for manufacturing a circuit board structure according to an embodiment of the invention. Fig. 2 is an enlarged view of a pad region of the circuit board structure shown in fig. 1D. Fig. 3 is a partial top view of the circuit board structure of fig. 1E. Referring to fig. 1A, first, an inner circuit structure 110 is provided, in which the inner circuit structure 110 includes a core layer 112 having an upper surface 111 and a lower surface 113 opposite to each other, a first patterned circuit layer 114 disposed on the upper surface 111, a second patterned circuit layer 116 disposed on the lower surface 113, and a conductive via 118 communicating the first patterned circuit layer 114 and the second patterned circuit layer 116. Here, the material of the first patterned circuit layer 114 and the material of the second patterned circuit layer 116 are, for example, copper, nickel, palladium, beryllium, or a copper alloy thereof, but not limited thereto.
Next, referring to fig. 1B, a build-up process is performed to press the first build-up circuit structure 120 on the first patterned circuit layer 114, wherein the first build-up circuit layer 120 includes at least one interlayer dielectric layer 122, and the interlayer dielectric layer 122 directly covers the upper surface 111 of the core layer 110 and the first patterned circuit layer 114. Further, the first build-up line structure 120 of the present embodiment further includes at least one first patterned conductive layer 124, at least one first dielectric layer 126, and at least one first conductive via structure 128 penetrating the inner dielectric layer 122 and the first dielectric layer 126. The first patterned conductive layer 124 and the first dielectric layer 126 are sequentially stacked on the interlayer dielectric layer 122, and the first patterned conductive layer 124 is electrically connected to the first patterned circuit layer 114 through the first conductive via structure 128.
Referring to fig. 1B, a build-up process is performed to laminate the first build-up circuit structure 120 on the first patterned circuit layer 114, and a second build-up circuit structure 130 on the second patterned circuit layer 116. The second build-up line structure 130 includes at least one second dielectric layer 132, at least one second patterned conductive layer 134, and at least one second conductive via structure 136 penetrating the second dielectric layer 132. The second dielectric layer 132 and the second patterned conductive layer 134 are sequentially stacked on the lower surface 113 of the core layer 110, and the second patterned conductive layer 134 is electrically connected to the second patterned circuit layer 116 through the second conductive via structure 136.
Next, referring to fig. 1C, a portion of the first build-up circuit layer 120 is removed to form an opening O extending from the first surface 121 of the first build-up circuit layer 120 relatively far away from the inner circuit structure 110 to a portion of the inner dielectric layer 122, wherein the opening O exposes the first inner surface 122a of the inner dielectric layer 122. Here, the step of removing a portion of the first build-up circuit layer 120 may perform a depthwise drilling (deep controlling) procedure or a sand blasting (sand blasting) procedure on the first build-up circuit layer 120, but is not limited thereto.
Then, referring to fig. 1C and fig. 1D, a sand blasting process is performed on the first inner surface 122a of the interlayer dielectric layer 122 exposed by the opening O to remove at least a portion of the interlayer dielectric layer 122 exposed by the opening O, so as to form a groove C exposing at least a portion of the first patterned circuit layer 114. In detail, the sand blasting procedure has a different removal efficiency for the ild layer 122 and the first patterned circuit layer 114, wherein the sand blasting procedure has a greater removal efficiency for the ild layer 122 than for the first patterned circuit layer 114. As shown in fig. 1D and fig. 2, the recess C exposes a portion of the first patterned circuit layer 114 and the second inner surface 122b of the interlayer dielectric layer 122. The portion of the first patterned circuit layer 114 exposed by the recess C is, for example, at least one pad, at least one circuit, or a combination thereof. The portion of the first patterned circuit layer 114 exposed by the groove C in the embodiment is embodied as the circuit T1 and the pad P, but not limited thereto. At this time, the first inner surface 122a of the interlayer dielectric layer 122 is higher than the second inner surface 122b, and the top surface 114a of the portion of the first patterned circuit layer 114 exposed by the groove C is higher than the second inner surface 122 b. In particular, the cross-sectional profile of the line T of the first patterned circuit layer 114 exposed by the groove C and the edge of the top surface 114a of the pad P is embodied as a curved surface.
Finally, referring to fig. 1E and fig. 3, a first patterned solder mask layer 140 is formed at least on the first surface 121 of the first build-up circuit structure 120 relatively far from the inner layer circuit structure 110 and on the portion of the first patterned circuit layer 114 (i.e., the circuit T and the pad P) exposed by the groove C; and forming a second patterned solder mask layer 150 on a second surface 131 of the second build-up circuit structure 130, which is relatively far away from the inner circuit structure 110. Here, the first patterned solder mask layer 140 exposes a portion of the first dielectric layer 126 farthest from the inner circuit structure 110 and a portion of the pad P of the first patterned circuit layer 114. The second patterned solder mask layer 150 exposes a portion of the second dielectric layer 132 and the second patterned conductive layer 134 farthest from the inner circuit structure 110. Thus, the circuit board structure 100 is completed. A portion of the first patterned solder mask layer 140 on the portion of the first patterned circuit layer 114 exposed by the recess C (i.e., the circuit T and the pad P) may be formed by spray printing. In this embodiment, an oxidation resistant layer 160, such as a gold plating layer or an OSP (Organic Solderability Preservative) layer, may also be formed on the pad P not covered by the first patterned solder resist layer 140.
Structurally, referring to fig. 1E again, the circuit board structure 100 includes an inner layer circuit structure 110 and a first build-up circuit structure 120. The inner circuit structure 110 includes a core layer 110 having an upper surface 111 and a lower surface 113 opposite to each other, a first patterned circuit layer 114 disposed on the upper surface 111, a second patterned circuit layer 116 disposed on the lower surface 113, and a conductive via 118 connecting the first patterned circuit layer 114 and the second patterned circuit layer 116. The first build-up circuit structure 130 is disposed on the upper surface 111 of the core layer 110 and covers the first patterned circuit layer 114, wherein the first build-up circuit structure 130 at least has a groove C exposing a portion of the first patterned circuit layer 114, and a cross-sectional profile of an edge of a top surface 114a of the portion of the first patterned circuit layer 114 exposed by the groove C is a curved surface.
More specifically, the first build-up line structure 120 of the present embodiment includes an inner dielectric layer 122, a first patterned conductive layer 124, a first dielectric layer 126, and a first conductive via structure 128 penetrating the inner dielectric layer 122 and the first dielectric layer 126. The first patterned conductive layer 124 and the first dielectric layer 126 are sequentially stacked on the interlayer dielectric layer 122, and the first patterned conductive layer 124 is electrically connected to the first patterned circuit layer 114 through the first conductive via structure 128. As shown in fig. 1E, the recess C of the present embodiment exposes a portion of the ild layer 122. The interlayer dielectric layer 122 has a first inner surface 122a and a second inner surface 122b, wherein the first inner surface 122a is higher than the second inner surface 122b, the recess C exposes the second inner surface 122b, and the top surface 114a of the portion (i.e., the trace T and the pad P) of the first patterned trace layer 114 exposed by the recess C is higher than the second inner surface 122 b.
Furthermore, the circuit board structure 100 of the present embodiment further includes a second build-up circuit structure 130 disposed on the lower surface 113 of the core layer 110 and covering the second patterned circuit layer 116. The second build-up line structure 130 includes a second dielectric layer 132, a second patterned conductive layer 134, and a second conductive via structure 136 penetrating the second dielectric layer 132. The second dielectric layer 132 and the second patterned conductive layer 134 are sequentially stacked on the lower surface 113 of the core layer 110, and the second patterned conductive layer 134 is electrically connected to the second patterned circuit layer 116 through the second conductive via structure 136.
In addition, the circuit board structure 100 of the present embodiment further includes a first patterned solder mask layer 140 and a second patterned solder mask layer 150. The first patterned solder mask layer 140 is disposed on at least the first surface 121 of the first build-up circuit structure 120 relatively far from the inner circuit structure 110 and the portion of the first patterned circuit layer 114 (i.e., the circuit T and the pad P) exposed by the recess C. The second patterned solder mask layer 150 is disposed on the second surface 131 of the second build-up circuit structure 130, which is relatively far away from the inner circuit structure 110.
In the present embodiment, the removal efficiency of the interlayer dielectric layer 122 and the first patterned circuit layer 114 is different by the sand blasting process, so as to form the groove C exposing at least a portion of the first patterned circuit layer 114 (i.e., the circuit T and the pad P). In this way, the formation of the groove C in the present embodiment does not require an alignment copper layer and does not affect the circuit layout of the inner circuit structure 110, so the circuit board structure 100 formed in the present embodiment can provide a larger layout space.
It should be noted that the following embodiments follow the element labels and parts of the contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.
Fig. 4A to 4C are enlarged views of the pad region of the circuit board structure of fig. 1D at different sandblasting depths, respectively. Fig. 5A to 5C are schematic cross-sectional views of the pad region of the circuit board structure of fig. 1E at different sandblasting depths, respectively. The structural differences produced at different blasting depths will be explained below with reference to these figures.
Referring to fig. 4A and 5A, in comparison with the embodiment of fig. 2 and 1E, when the sandblasting process is performed on the first inner surface 122a of the ild layer 122 exposed by the opening O (as shown in fig. 1C), the sandblasting depth is smaller, so that a portion of the ild layer 122 in the recess C is removed, such that the thickness of the ild layer 122 is equal to the thickness (or height) of the pad P. Therefore, the recess C exposes portions of the first patterned circuit layer 114 (i.e., the pad P and the circuit T) and the second inner surface 122 b' of the ild layer 122. Here, the first inner surface 122a is higher than the second inner surface 122b ', and the top surface 114a of the portion of the first patterned circuit layer 114 exposed by the recess C is aligned with the second inner surface 122 b'.
Referring to fig. 4B and 5B, in comparison with the embodiment of fig. 2 and 1E, when the sandblasting process is performed on the first inner surface 122a of the ild layer 122 exposed by the opening O (as shown in fig. 1C), the sandblasting depth is larger, so that the ild layer 122 exposed by the opening O is completely removed. Therefore, the groove C exposes portions (i.e., the pad P and the trace T) of the first patterned trace layer 114 and a portion of the upper surface 111 of the core layer 110. The top surface 114a of the portion of the first patterned circuit layer 114 exposed by the groove C is higher than the upper surface 111 of the core layer 110, the cross-sectional profile of the edge of the top surface 114a of the portion of the first patterned circuit layer 114 exposed by the groove C (i.e., the pad P and the circuit T) is a curved surface, and the bottom surface 114b of the portion of the first patterned circuit layer 114 exposed by the groove C (i.e., the pad P and the circuit T) is aligned with the upper surface 111.
Referring to fig. 4C and 5C, in comparison with the embodiment of fig. 2 and 1E, when the blasting process is performed on the first inner surface 122a of the interlayer dielectric layer 122 exposed by the opening O, the blasting depth is greater, so that the interlayer dielectric layer 122 and a portion of the core layer 110 exposed by the opening O are completely removed. Accordingly, the groove C exposes a portion of the first patterned circuit layer 114 and the first upper surface 111a of the core layer 110. The upper surface 111 of the core layer 110 includes a first upper surface 111a and a second upper surface 111b, wherein the second upper surface 111b is higher than the first upper surface 111a, and the top surface 114a of the portion (i.e., the pad P and the trace T) of the first patterned trace layer 114 exposed by the groove C is higher than the first upper surface 111 a.
In summary, in the manufacturing process of the circuit board structure of the present invention, the inner dielectric layer exposed by the opening is at least partially removed by the sand blasting process, so as to form the groove exposing at least a portion of the first patterned circuit layer. Therefore, the formation of the groove of the invention does not need to arrange an alignment copper layer and does not influence the circuit layout of the inner layer circuit structure, so that the circuit board structure formed by the invention can provide larger layout space.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (20)
1. A circuit board structure comprising:
an inner layer circuit structure including a core layer having an upper surface and a lower surface opposite to each other, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface, and a conductive via connecting the first patterned circuit layer and the second patterned circuit layer; and
a first build-up circuit structure disposed on the upper surface of the core layer and covering the first patterned circuit layer, wherein the first build-up circuit structure has at least one groove exposing a portion of the first patterned circuit layer, and a cross-sectional profile of a top surface edge of the portion of the first patterned circuit layer exposed by the groove is a curved surface, wherein the first build-up circuit structure includes an interlayer dielectric layer, at least one first patterned conductive layer, and at least one first conductive via structure penetrating the interlayer dielectric layer and the at least one first dielectric layer, the at least one first patterned conductive layer and the at least one first dielectric layer are sequentially stacked on the interlayer dielectric layer, and the at least one first patterned conductive layer is electrically connected to the first patterned circuit layer through the at least one first conductive via structure, wherein the recess also exposes a portion of the interlayer dielectric layer, the interlayer dielectric layer has a first inner surface and a second inner surface, the first inner surface is higher than the second inner surface, the recess exposes the second inner surface, and the top surface of the portion of the first patterned wire layer exposed by the recess is higher than the second inner surface.
2. The circuit board structure of claim 1, wherein the portion of the first patterned circuit layer exposed by the recess comprises at least one pad, at least one circuit, or a combination thereof.
3. The wiring board structure of claim 1, further comprising:
the first patterned solder mask layer is at least arranged on a first surface of the first build-up circuit structure relatively far away from the inner-layer circuit structure and the part of the first patterned circuit layer exposed by the groove.
4. The wiring board structure of claim 1, further comprising:
a second build-up circuit structure disposed on the lower surface of the core layer and covering the second patterned circuit layer; and
and the second patterned solder mask layer is configured on a second surface, which is relatively far away from the inner layer circuit structure, of the second build-up circuit structure.
5. The circuit board structure of claim 4, wherein the second build-up circuit structure comprises at least one second dielectric layer, at least one second patterned conductive layer, and at least one second conductive via structure penetrating the second dielectric layer, the at least one second dielectric layer and the at least one second patterned conductive layer are sequentially stacked on the lower surface of the core layer, and the at least one second patterned conductive layer is electrically connected to the second patterned circuit layer through the at least one second conductive via structure.
6. A circuit board structure comprising:
an inner layer circuit structure including a core layer having an upper surface and a lower surface opposite to each other, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface, and a conductive via connecting the first patterned circuit layer and the second patterned circuit layer; and
a first build-up circuit structure disposed on the upper surface of the core layer and covering the first patterned circuit layer, wherein the first build-up circuit structure has at least one groove exposing a portion of the first patterned circuit layer, and a cross-sectional profile of a top surface edge of the portion of the first patterned circuit layer exposed by the groove is a curved surface, wherein the first build-up circuit structure includes an interlayer dielectric layer, at least one first patterned conductive layer, and at least one first conductive via structure penetrating the interlayer dielectric layer and the at least one first dielectric layer, the at least one first patterned conductive layer and the at least one first dielectric layer are sequentially stacked on the interlayer dielectric layer, and the at least one first patterned conductive layer is electrically connected to the first patterned circuit layer through the at least one first conductive via structure, wherein the recess further exposes a portion of the interlayer dielectric layer, the interlayer dielectric layer has a first inner surface and a second inner surface, the first inner surface is higher than the second inner surface, the recess exposes the second inner surface, and the top surface of the portion of the first patterned circuit layer exposed by the recess is flush with the second inner surface, wherein the top surface of the portion is composed of a flat surface and a curved edge connecting the flat surface.
7. A manufacturing method of a circuit board structure comprises the following steps:
providing an inner layer circuit structure, wherein the inner layer circuit structure comprises a core layer, a first patterned circuit layer, a second patterned circuit layer and a conductive through hole, the core layer is provided with an upper surface and a lower surface which are opposite to each other, the first patterned circuit layer is arranged on the upper surface, the second patterned circuit layer is arranged on the lower surface, and the conductive through hole is communicated with the first patterned circuit layer and the second patterned circuit layer;
performing a build-up procedure to press a first build-up circuit structure on the first patterned circuit layer, wherein the first build-up circuit layer at least comprises an inner dielectric layer, and the inner dielectric layer directly covers the upper surface of the core layer and the first patterned circuit layer;
removing a portion of the first build-up line layer to form an opening extending from a first surface of the first build-up line layer relatively away from the inner dielectric layer structure to a portion of the inner dielectric layer, wherein the opening exposes a first inner surface of the inner dielectric layer; and
and performing a sand blasting procedure on the first inner surface of the interlayer dielectric layer exposed by the opening to remove at least part of the interlayer dielectric layer exposed by the opening so as to form a groove at least exposing part of the first patterned circuit layer.
8. The method of claim 7, wherein the first build-up circuitry structure further comprises at least one first dielectric layer, at least one first patterned conductive layer, and at least one first conductive via structure penetrating the inner dielectric layer and the first dielectric layer, the at least one first patterned conductive layer and the at least one first dielectric layer are sequentially stacked on the inner dielectric layer, and the at least one first patterned conductive layer is electrically connected to the first patterned circuitry layer through the at least one first conductive via structure.
9. The method of claim 8, wherein the recess further exposes a second inner surface of the inter-layer dielectric layer, the first inner surface is higher than the second inner surface, and a top surface of the portion of the first patterned circuit layer exposed by the recess is higher than the second inner surface.
10. The method of claim 9, wherein a cross-sectional profile of the top surface edge of the portion of the first patterned circuit layer exposed by the recess is curved.
11. The method of fabricating a circuit board structure according to claim 7, wherein the step of removing a portion of the first build-up circuit layer comprises performing a depth-cut procedure or a sand-blast procedure on the first build-up circuit layer.
12. The method of claim 7, wherein the sand blasting procedure is performed on the first inner surface of the inner dielectric layer exposed by the opening to completely remove the inner dielectric layer exposed by the opening and a portion of the core layer, thereby forming the groove exposing the portion of the first patterned circuit layer and a first upper surface of the core layer, the upper surface of the core layer comprises the first upper surface and a second upper surface, the second upper surface is higher than the first upper surface, and a top surface of the portion of the first patterned circuit layer exposed by the groove is higher than the first upper surface.
13. The method of claim 12, wherein a cross-sectional profile of the top surface edge of the portion of the first patterned circuit layer exposed by the recess is curved.
14. The method of claim 7, wherein the recess further exposes a second inner surface of the inter-layer dielectric layer, the first inner surface is higher than the second inner surface, and a top surface of the portion of the first patterned circuit layer exposed by the recess is flush with the second inner surface, wherein the top surface of the portion is composed of a flat surface and a curved edge connecting the flat surface.
15. The method of claim 7, wherein the sand blasting procedure is performed on the first inner surface of the interlayer dielectric layer exposed by the opening to completely remove the interlayer dielectric layer exposed by the opening, thereby forming the groove exposing the portion of the first patterned circuit layer and the portion of the upper surface of the core layer, and the top surface of the portion of the first patterned circuit layer exposed by the groove is higher than the upper surface of the core layer exposed.
16. The method as claimed in claim 7, wherein the sand blasting procedure is performed on the first inner surface of the interlayer dielectric layer exposed by the opening to completely remove the interlayer dielectric layer exposed by the opening, so as to form the groove exposing the portion of the first patterned circuit layer and the portion of the upper surface of the core layer, and a bottom surface of the portion of the first patterned circuit layer exposed by the groove is aligned with the upper surface.
17. The method of claim 7, wherein the portion of the first patterned circuit layer exposed by the recess comprises at least one pad, at least one circuit, or a combination thereof.
18. The method of making a circuit board structure of claim 7, further comprising:
after the groove at least exposing the part of the first patterned circuit layer is formed, a first patterned solder mask layer is formed at least on a first surface of the first build-up circuit structure relatively far away from the inner circuit structure and the part of the first patterned circuit layer exposed by the groove.
19. The method of making a circuit board structure of claim 7, further comprising:
when the layer adding procedure is carried out, simultaneously pressing a second layer adding circuit structure on the second patterned circuit layer; and
and forming a second patterned solder mask layer on a second surface of the second build-up circuit structure, which is relatively far away from the inner layer circuit structure.
20. The method of claim 19, wherein the second build-up circuitry structure comprises at least one second dielectric layer, at least one second patterned conductive layer, and at least one second conductive via structure penetrating the second dielectric layer, the at least one second dielectric layer and the at least one second patterned conductive layer are sequentially stacked on the lower surface of the core layer, and the at least one second patterned conductive layer is electrically connected to the second patterned circuitry layer through the at least one second conductive via structure.
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| CN108235558B (en) * | 2016-12-14 | 2020-12-01 | 欣兴电子股份有限公司 | Circuit board structure and manufacturing method thereof |
| CN110858575B (en) * | 2018-08-23 | 2021-07-27 | 欣兴电子股份有限公司 | Heat dissipation substrate, manufacturing method thereof and chip packaging structure |
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