CN108235352B - Data monitoring method and device - Google Patents
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- CN108235352B CN108235352B CN201810005520.XA CN201810005520A CN108235352B CN 108235352 B CN108235352 B CN 108235352B CN 201810005520 A CN201810005520 A CN 201810005520A CN 108235352 B CN108235352 B CN 108235352B
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- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
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Abstract
The invention provides a data monitoring method and a device, under the condition that a CCU system is detected to load configuration data, the CPLD of the CCU system outputs the configuration data to be loaded to a universal asynchronous receiving and transmitting transmitter externally connected with the CCU system according to the corresponding time sequence of the universal asynchronous receiving and transmitting transmitter externally connected with the CCU system, and after the CCU system is detected to finish the loading of the configuration data and a CPU of the CCU system initializes the universal asynchronous receiving and transmitting transmitter externally connected with the CPU, a starting operation log recorded with the starting operation process of the CPU is output to the universal asynchronous receiving and transmitting transmitter externally connected with the CCU, thereby realizing the time division multiplexing of the universal asynchronous receiving and transmitting transmitter externally connected with the CCU, and the data loading and the starting operation process of the CPU can be monitored by the data of the universal asynchronous receiving and transmitting transmitter externally connected with the CCU, such as the configuration data and the starting operation log, thereby realizing the positioning of problems in the starting loading process, thereby reducing the difficulty of research and development and debugging.
Description
Technical Field
The present invention belongs to the field of data communication technologies, and in particular, to a data monitoring method and apparatus.
Background
At present, a Base station (LTE Base station for short) in a Long Term Evolution (LTE) network at least includes a Base Band Unit (BBU) and a Radio Remote Unit (RRU), where the BBU is responsible for processing an uplink baseband signal and a downlink baseband signal, and provides a physical interface to complete information interaction with the RRU and other networks through the physical interface, and the RRU communicates with the BBU through the physical interface to complete conversion between the baseband signal and the Radio frequency signal.
For BBU, a CCU (master Control clock board) system in BBU can provide a system clock and a synchronization signal for an LTE base station, and is responsible for OAM (Operation Administration and Maintenance) and RRC (Radio Resource Control), where the CCU system includes: the system comprises a Central Processing Unit (CPU), a Field Programmable Gate Array (FPGA), a Complex Programmable Logic Device (CPLD), etc., wherein the CPU and the CPLD are responsible for OAM and RRC control, and the FPGA is responsible for providing a system clock and synchronization signals.
A storage unit can be further integrated in the CCU system, the BOOT file and the FPGA configuration data are read from the storage unit, but in the prior art, some processes in the startup loading process of the CCU system are not monitored conveniently, such as the monitoring of the hardware configuration word loading process, so that if a problem occurs in the hardware configuration word loading process, the problem is difficult to locate quickly, and the research, development and debugging difficulty is increased.
Disclosure of Invention
In view of this, an object of the present invention is to provide a data monitoring method and apparatus, which are used to monitor the configuration data loading process of the CCU system and the startup operation process of the CPU in the CCU system, and implement positioning of problems in the startup loading process, thereby reducing difficulty in research and development and debugging, and implementing time division multiplexing of a universal asynchronous transceiver externally connected to the CCU system. The technical scheme is as follows:
the invention provides a data monitoring method, which is applied to a master control clock board system and comprises the following steps:
under the condition that a master control clock board system is detected to be loaded with configuration data, the configuration data to be loaded are output to a universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system through a complex programmable logic device of the master control clock board system in a time sequence corresponding to the universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system;
after detecting that the master control clock board system finishes configuration data loading and a central processing unit of the master control clock board system finishes initialization of a universal asynchronous receiving and transmitting transmitter externally connected with the central processing unit, outputting a starting operation log recorded with a starting operation process of the central processing unit to the universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system through control of a complex programmable logic device.
Preferably, when it is detected that the master clock board system needs to load the configuration data, the outputting, by the complex programmable logic device of the master clock board system, the configuration data to be loaded to the universal asynchronous transceiver transmitter externally connected to the master clock board system at a timing sequence corresponding to the universal asynchronous transceiver transmitter externally connected to the master clock board system includes:
under the condition that a central processing unit of the master control clock board system is detected to be required to load a hardware configuration word, outputting the hardware configuration word to a universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system through the complex programmable logic device according to a time sequence corresponding to the universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system;
and under the condition that the situation that a driver communicating with the complex programmable logic device needs to load field programmable gate array configuration data is detected, outputting the field programmable gate array configuration data to a universal asynchronous receiving and transmitting transmitter externally connected with a master control clock board system through the complex programmable logic device according to the time sequence corresponding to the universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system.
Preferably, when it is detected that the central processing unit of the master control clock board system needs to load the hardware configuration word, the outputting, by the complex programmable logic device, the hardware configuration word to the external universal asynchronous transceiver transmitter of the master control clock board system at a timing sequence corresponding to the external universal asynchronous transceiver transmitter of the master control clock board system includes:
and under the condition that the central processing unit is detected to be required to load the hardware configuration words, according to a time sequence required format corresponding to a universal asynchronous receiving and transmitting transmitter externally connected with the main control clock board system, packaging the preset number of hardware configuration words into universal asynchronous receiving and transmitting transmitter time sequence data when the complex programmable logic device receives the preset number of hardware configuration words, and outputting the universal asynchronous receiving and transmitting transmitter time sequence data to the universal asynchronous receiving and transmitting transmitter externally connected with the main control clock board system.
Preferably, when it is detected that the driver communicating with the complex programmable logic device needs to load the configuration data of the field programmable gate array, the complex programmable logic device outputs the configuration data of the field programmable gate array to the external universal asynchronous transceiver transmitter of the master control clock board system at a timing sequence corresponding to the external universal asynchronous transceiver transmitter of the master control clock board system, and the method includes:
under the condition that the driver needs to load the configuration data of the field programmable gate array, the complex programmable logic device acquires the configuration data of the field programmable gate array which is transmitted on a bus connected with the driver in parallel, and according to the required format of the time sequence corresponding to the universal asynchronous receiving and transmitting transmitter externally connected with the main control clock board system, after every time a preset number of configuration data of the field programmable gate array are acquired, the preset number of configuration data of the field programmable gate array are packaged into the time sequence data of the universal asynchronous receiving and transmitting transmitter, and the time sequence data of the universal asynchronous receiving and transmitting transmitter are output to the universal asynchronous receiving and transmitting transmitter externally connected with the main control clock board system.
Preferably, the method further comprises: and under the condition of receiving preset data, determining that the driver needs to load the configuration data of the field programmable gate array.
The invention also provides a data monitoring device, which is applied to a master control clock board system, and the device comprises:
the first control unit is used for outputting the configuration data to be loaded to a universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system through a complex programmable logic device of the master control clock board system according to a time sequence corresponding to the universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system under the condition that the master control clock board system is detected to be loaded with the configuration data;
and the second control unit is used for outputting the starting operation log recorded with the starting operation process of the central processing unit to the universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system through the control of a complex programmable logic device after detecting that the master control clock board system finishes the loading of the configuration data and the central processing unit of the master control clock board system finishes the initialization of the universal asynchronous receiving and transmitting transmitter externally connected with the central processing unit.
Preferably, the first control unit is specifically configured to, when it is detected that a central processing unit of the master control clock board system needs to load a hardware configuration word, output the hardware configuration word to a universal asynchronous transceiver transmitter externally connected to the master control clock board system through the complex programmable logic device in a timing sequence corresponding to the universal asynchronous transceiver transmitter externally connected to the master control clock board system;
and the field programmable gate array configuration data is output to the universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system through the complex programmable logic device according to the time sequence corresponding to the universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system under the condition that the situation that the field programmable gate array configuration data is required to be loaded by the driver communicated with the complex programmable logic device is detected.
Preferably, the first control unit is specifically configured to, when it is detected that the central processing unit needs to load a hardware configuration word, package, by the complex programmable logic device, a preset number of hardware configuration words into universal asynchronous transceiver transmitter timing data every time the complex programmable logic device receives the preset number of hardware configuration words according to a format required by a timing sequence corresponding to a universal asynchronous transceiver transmitter externally connected to the main control clock board system, and output the universal asynchronous transceiver transmitter timing data to the universal asynchronous transceiver externally connected to the main control clock board system.
Preferably, the first control unit is specifically configured to, when it is detected that the driver needs to load the fpga configuration data, obtain the fpga configuration data that is transmitted in parallel on the bus connected to the driver through the complex programmable logic device, package, after a preset number of fpga configuration data is obtained according to a format required by a timing sequence corresponding to the external uart of the master clock board system, the preset number of fpga configuration data into the uart timing data, and output the uart timing data to the external uart of the master clock board system.
The invention also provides a storage medium, which stores a computer program flow, and the computer program flow realizes the data monitoring method when being executed.
It can be known from the above technical solutions that, under the condition that it is detected that the CCU system needs to load configuration data, the CPLD of the CCU system outputs the configuration data (such as hardware configuration words and FPGA configuration data) to be loaded to the external universal asynchronous transceiver transmitter of the CCU system at a timing sequence corresponding to the external universal asynchronous transceiver transmitter of the CCU system, and after it is detected that the CCU system completes the loading of the configuration data and the CPU of the CCU system completes the initialization of the external universal asynchronous transceiver transmitter of the CPU, the CPLD controls to output the start operation log recorded with the start operation process of the CPU to the external universal asynchronous transceiver transmitter of the CCU system, so as to implement time division multiplexing of the external universal asynchronous transceiver transmitter of the CCU system, and the data loading and the start operation process of the CPU can be monitored by the data of the external universal asynchronous transceiver transmitter output to the CCU system, such as the configuration data and the start operation log, the problem in the starting loading process is positioned, so that the research and development and debugging difficulty is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a flow chart of a data monitoring method provided by an embodiment of the invention;
fig. 2 is a schematic structural diagram of a data monitoring apparatus according to an embodiment of the present invention.
Detailed Description
The conventional CCU system lacks the comprehensive and convenient monitoring on some processes in the CCU system startup loading process, so that the research and development and debugging difficulty is increased. To solve this problem, the CCU system corresponding to the data monitoring method and apparatus provided in this embodiment at least includes: CPLD and CPU, and CCU system connects with UART (Universal Asynchronous Receiver/Transmitter).
Wherein the CPLD comprises at least: the system comprises a time sequence conversion module and a URAT alternative module, wherein the time sequence conversion module is used for packaging data into UART time sequence data according to a time sequence required format corresponding to the UART, the UART alternative module is used for selecting the data which needs to be output to the UART externally connected with the CCU system, if the data packaged by the time sequence conversion module is output to the UART or the data related to the starting operation of the UART output externally connected with the CPU, such as a starting operation log is output to the UART externally connected with the CCU system, the UART alternative module selects which data output is determined by CPLD, if the data output can be determined according to the flow of the CCU system, if the CCU system is in a configuration data loading flow, the UART data packaged by the time sequence conversion module is controlled to be selected by the UART alternative module, and in the flow of the CCU system after the configuration data loading is completed and the CPU of the CCU system completes the initialization of the CPU externally connected with the CPU, the UART alternative module is controlled to select the UART data, for example, the start operation log realizes time division multiplexing of the external UART of the CCU system, and can monitor the data loading (such as loading of hardware configuration words and FPGA configuration data) in the CCU system and the start operation process of the CPU, thereby facilitating the positioning of problems in the start loading process and reducing the research and development and debugging difficulty.
For the CCU system, the idea of the data monitoring method provided by the embodiment of the present invention is as follows: under the condition that the CCU system is detected to need to load the configuration data, the configuration data needing to be loaded is output to the UART externally connected with the CCU system through the CPLD of the CCU system in a time sequence corresponding to the UART externally connected with the CCU system;
after detecting that the CCU system finishes configuration data loading and a CPU of the CCU system finishes UART initialization externally connected with the CPU, outputting a starting operation log recorded with a starting operation process of the CPU to the UART externally connected with the CCU system through CPLD control.
The following configuration data includes hardware configuration words and FPGA configuration data, and the boot loading process of the CCU system is as follows: the technical solutions in the embodiments of the present invention are clearly and completely described by taking examples of loading hardware configuration words, starting an operating system by a CPU, loading FPGA configuration data, and running the CPU, and combining with the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a flowchart of a data monitoring method provided in an embodiment of the present invention is shown, where the data monitoring method is used for monitoring a start loading process of a CCU system, such as a data loading process and a CPU start running process, and implementing positioning of a problem in the start loading process, and a specific data monitoring method shown in fig. 1 may include the following steps:
101: under the condition that the CPU of the CCU system needs to load the hardware configuration word, the hardware configuration word is output to the UART externally connected with the CCU system through the CPLD according to the time sequence corresponding to the UART externally connected with the CCU system in the process that the CPU loads the hardware configuration word.
In this embodiment, a feasible way of outputting the hardware configuration word to the UART externally connected to the CCU system through the CPLD in the timing sequence of the UART externally connected to the CCU system is as follows: under the condition that the CPU needs to load the hardware configuration words, according to the time sequence required format corresponding to the UART externally connected with the CCU system, when receiving the hardware configuration words with preset number, the hardware configuration words with preset number are packaged into UART time sequence data, the UART time sequence data is output to the UART externally connected with the CCU system, and the purpose that the hardware configuration words are output to the UART externally connected with the CCU system according to the UART time sequence in the process that the CPU loads the hardware configuration words is achieved.
The CPU loads the hardware configuration word after the CCU system finishes loading BOOT data and is electrified again, the hardware configuration word to be loaded by the CPU is read from a storage device, such as an external norflash, by the CPU through a CPLD, and the CPLD respectively performs two-step parallel processing when reading the hardware configuration word: the first step is to output the hardware configuration word to the CPU; the second step is: caching and packaging the hardware configuration words into UART time sequence data to be output to a UART pin externally connected with a CCU connected with the CPLD, wherein the process of the second step is as follows:
the CPLD caches the hardware configuration data read by the CPU from the storage device in a RAM (Random-Access Memory) inside the CPLD, for example, the CPU may send a chip select signal and a read signal to the storage device through the CPLD, and read a certain amount, such as 16-bit data, from the storage device every time one chip select signal and one read signal is sent, after the CPU sends a predetermined chip select signal and read signal through the CPLD, it indicates that the CPU reads all the hardware configuration data, and at this time, caches all the hardware configuration data in the RAM inside the CPLD. Taking a CPU of a type T4240 as an example, the CPU needs to read all hardware configuration data from the storage device by sending 36 chip select signals and 36 read signals through the CPLD, and a 16-bit hardware configuration word is read every time a chip select signal and a read signal are sent, so after sending 36 chip select signals and 36 read signals, all hardware configuration words are read from the storage device, for example, the read hardware configuration words include 64-bit flag bits and 512-bit hardware configuration data, where the hardware configuration data is used to configure Serdes PLL (Serializer-Deserializer Phase Locked Loop), clock and pin multiplexing, and the like.
For CPLD, after power-on, if CPLD monitors that chip select signal and read signal are 0 at the same time, a counter in CPLD starts counting, the counter accumulates to a value indicating that CPU has sent a specified number of chip select signals and read signals, and stops counting if the counter accumulates to 36, data read from a storage device, such as norflash externally connected to CPU, is written into RAM opened inside CPLD, when data is written into RAM of CPLD, the bit number of the hardware configuration word is determined, for example, when the read hardware configuration word is the above-mentioned 64-bit flag bit and 512-bit hardware configuration data, when data is written into RAM, bit width of data written into RAM is 16bits, addresses of data written into RAM are 0, 1 …, 35 in sequence, when all the read hardware configuration data are written into RAM when writing to address 35, an indication signal of completion of writing into RAM is generated at this time.
And the format of the UART timing data may be: a frame of UART timing data includes: the start bit, the data bit, the check bit, and the end bit, for example, the number of bits of the data bit of a frame of UART timing data is 8, and the 8-bit data bits are sequentially: bit0, Bit1, Bit2, Bit3, Bit4, Bit5, Bit6, and Bit 7. Under the condition that the write RAM is monitored to be completed, the CPLD can read a preset number of hardware configuration words specified by the UART time sequence data from the hardware configuration words cached in the RAM of the CPLD in sequence, and the hardware configuration words read each time are not overlapped, for example, 8-bit hardware configuration words are read each time and 8-bit hardware configuration words read each time are not overlapped, for any hardware configuration word read at any time, the hardware configuration words read at the time are packaged according to the format of the UART time sequence data to obtain the UART time sequence data, and the UART time sequence data are output to UART pins externally connected with a CCU connected with the CPLD and then output to a UART externally connected with a CCU system, so that the hardware configuration words loaded by the CPU are recorded, and the loading process of the hardware configuration words is monitored conveniently.
Still taking the above hardware configuration word including 64-Bit flag Bits and 512-Bit hardware configuration data as an example, when an indication signal that writing to the RAM (reading Bit width is 1Bit, useful data stored inside RAM is 576Bits, that is, reading address is from 0, 1.., 576-1) is completed is monitored, according to the format required by the timing sequence of the UART, frame 1: sequentially and serially adding a start Bit (realized by a CPLD program), reading data Bit0 with an address of 0 in the RAM, reading data Bit1 with an address of 1 in the RAM, reading data Bit2 with an address of 2 in the RAM, reading data Bit3 with an address of 3 in the RAM, reading data Bit4 with an address of 4 in the RAM, reading data Bit5 with an address of 5 in the RAM, reading data Bit6 with an address of 6 in the RAM, reading data Bit7 with an address of 7 in the RAM, adding a check Bit (realized by the CPLD program) and adding an end Bit (realized by the CPLD program) until the first frame of UART data is packaged and transmitted. The same goes for the same time sequence until the data at the address 576-1 in the RAM is read out, and the check bit and the end bit are added, i.e., the 576/8 th frame is 72 th frame and sent.
102: after the CCU system is detected to finish loading of the hardware configuration words and the CPU of the CCU system finishes initialization of the UART externally connected with the CPU, the CPLD is used for controlling to output the starting operation log recorded with the starting operation process of the CPU to the UART externally connected with the CCU system, so that the starting operation process of the CPU can be monitored through the output starting operation log.
103: under the condition that the driver communicating with the CPLD needs to load the FPGA configuration data, the FPGA configuration data are output to the UART externally connected with the CCU system through the CPLD according to the time sequence corresponding to the UART externally connected with the CCU system in the process of driving and loading the FPGA configuration data.
For the FPGA configuration data, a feasible way to output the FPGA configuration data to the UART through the CPLD in the timing sequence of the UART is: when it is detected that the driver needs to load the FPGA configuration data, the FPGA configuration data transmitted in parallel on the bus connected to the driver is obtained, for example, the FPGA configuration data transmitted in parallel on the localbus bus (or referred to as a CPU bus) connected to the driver can be obtained, where the process of obtaining the FPGA configuration data by the CPLD may refer to the prior art, and this embodiment is not described again.
For the acquired FPGA data, two steps of processing are performed in the CPLD: outputting an FPGA configuration pin to load FPGA configuration data; and in another step, the data is packaged into UART time sequence data and is output to a UART pin externally connected with a CCU connected with the CPLD. The process of packaging UART timing data is as follows:
after the FPGA configuration data with the preset number are obtained according to the format required by the time sequence corresponding to the UART externally connected with the CCU system, the FPGA configuration data with the preset number are packaged into UART time sequence data, the UART time sequence data are output to the UART externally connected with the CCU, and the FPGA configuration data are output to the UART externally connected with the CCU according to the UART time sequence in the process of driving and loading the FPGA configuration data.
In this embodiment, the format of the UART timing data may be: a frame of UART timing data includes: the start bit, the data bit, the check bit, and the end bit, for example, the number of data bits of a frame of UART timing data is 8, and the 8-bit data bits are sequentially: bit0, Bit1, Bit2, Bit3, Bit4, Bit5, Bit6 and Bit7, after the CPLD obtains the preset number of FPGA configuration data (such as the 8-Bit configuration data) sent in parallel on the bus (such as the localbus bus), the preset number of FPGA configuration data is converted into serial data (i.e. data that can be encapsulated in a frame of UART data), then the converted serial data is encapsulated according to the format requirement of the UART timing data, and the encapsulated serial data is output to the UART pin externally connected to the CCU connected to the UART through the pin.
The possible way to pack the converted serial data according to the format requirement of the UART timing data is: adding a start bit, a check bit and an end bit to the converted serial data to obtain a frame of UART data, wherein if the obtained UART data is as follows: the start bit, the converted 8-bit serial data, the check bit and the end bit, and the obtained UART data are output to a UART pin externally connected with a CCU (central processing unit) connected with the UART pin through the pin, so that FPGA (field programmable gate array) configuration data loaded by a driver are recorded and driven, and the loading process of the FPGA configuration data is conveniently monitored.
The points to be explained here are: the feasible method for detecting the driver to load the FPGA configuration data is as follows: and under the condition of receiving preset data, determining that the driver needs to load FPGA configuration data, wherein the preset data can be freely agreed, for example, the preset data can be sequentially written 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa and 0x55, and after receiving the data, the driver can load subsequently written FPGA configuration data if the next written data is the FPGA configuration data.
104: when the CCU system is detected to finish FPGA configuration data loading, the starting operation log recorded with the starting operation process of the CPU is output to a UART (universal asynchronous receiver/transmitter) externally connected with the CCU system through the control of the CPLD, so that the starting operation process of the CPU can be monitored through the output starting operation log.
In this embodiment, the feasible way of detecting that the CCU system completes configuration data loading is: when the completion flag bit of the configuration data is detected to be switched to the preset flag bit, if the completion flag bit is pulled high to 1, it indicates that the loading of the configuration data is completed, and for example, if the FPGA loading completion flag is pulled high, it indicates that the loading of the FPGA configuration data is completed.
It can be known from the above technical solutions that, under the condition that it is detected that the CCU system needs to load configuration data, the CPLD of the CCU system outputs the configuration data (such as hardware configuration words and FPGA configuration data) to be loaded to the external universal asynchronous transceiver transmitter of the CCU system at a timing sequence corresponding to the external universal asynchronous transceiver transmitter of the CCU system, and after it is detected that the CCU system completes the loading of the configuration data and the CPU of the CCU system completes the initialization of the external universal asynchronous transceiver transmitter of the CPU, the CPLD outputs the start operation log recorded with the start operation process of the CPU to the external universal asynchronous transceiver transmitter of the CCU system, so as to implement time division multiplexing of the external universal asynchronous transceiver transmitter of the CCU system, and the data loading and the start operation process of the CPU can be monitored by the data of the external universal asynchronous transceiver transmitter, such as the configuration data and the start operation log, output to the external universal asynchronous transceiver transmitter of the CCU system, the problem in the starting loading process is positioned, so that the research and development and debugging difficulty is reduced.
Corresponding to the foregoing method embodiment, an embodiment of the present invention further provides a data monitoring apparatus, which is applied to a CCU system, and a structure of the data monitoring apparatus is shown in fig. 2, where the data monitoring apparatus may include: a first control unit 11 and a second control unit 12.
The first control unit 11 is configured to, when it is detected that the CCU system needs to load the configuration data, output the configuration data that needs to be loaded to the UART externally connected to the CCU system through the CPLD of the CCU system at a timing sequence corresponding to the UART externally connected to the CCU system.
In this embodiment, the configuration data to be loaded by the CCU system includes, but is not limited to, hardware configuration words to be loaded by a CPU of the CCU system and FPGA configuration data to be loaded by a driver in communication with the CPLD. Correspondingly, the first control unit 11 outputs the hardware configuration word to the UART externally connected to the CCU system at the timing sequence corresponding to the UART externally connected to the CCU system through the CPLD when detecting that the CPU of the CCU system needs to load the hardware configuration word, and outputs the FPGA configuration data to the UART externally connected to the CCU system at the timing sequence corresponding to the UART externally connected to the CCU system through the CPLD when detecting that the driver of the CCU system needs to load the FPGA configuration data through the CPLD.
Specifically, when detecting that the CPU needs to load the hardware configuration word, the first control unit 11 encapsulates, by the CPLD, the preset number of hardware configuration words into UART timing data every time the CPLD receives the preset number of hardware configuration words according to a format required by a timing sequence corresponding to the UART externally connected to the CCU system, and outputs the UART timing data to the UART externally connected to the CCU system.
And when detecting that the driver needs to load the FPGA configuration data, the first control unit 11 obtains the FPGA configuration data transmitted in parallel on the bus connected to the driver through the CPLD, and encapsulates the FPGA configuration data of a preset number into UART timing data according to a timing required format corresponding to the UART externally connected to the CCU system after obtaining the FPGA configuration data of the preset number, and outputs the UART timing data to the UART externally connected to the CCU system.
And the second control unit 12 is configured to, after detecting that the CCU system completes configuration data loading and the CPU of the CCU system completes UART initialization externally connected to the CPU, output, through CPLD control, the start operation log in which the start operation process of the CPU is recorded to the UART externally connected to the CCU system.
According to the technical scheme, under the condition that the CCU system is detected to be loaded with the configuration data, the CPLD of the CCU system outputs the configuration data (such as hardware configuration words, FPGA configuration data and the like) to be loaded to the UART externally connected with the CCU system according to the time sequence corresponding to the UART externally connected with the CCU system, after the CCU system is detected to finish the loading of the configuration data and the CPU of the CCU system finishes the initialization of the UART externally connected with the CPU, the CPLD is used for controlling to output the starting operation log recorded with the starting operation process of the CPU to the UART externally connected with the CCU system, so that the time division multiplexing of the UART externally connected with the CCU system is realized, the data loading and the starting operation process of the CPU can be monitored through the UART data output to the CCU system, such as the configuration data and the starting operation log, and the positioning of the problems in the starting loading process is realized, and the research.
The embodiment of the invention also provides a storage medium, wherein the storage medium is stored with a computer program flow, and the data monitoring method is realized when the computer program flow is executed.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the device-like embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A data monitoring method is applied to a master clock board system, and is characterized by comprising the following steps:
under the condition that a master control clock board system is detected to be loaded with configuration data, the configuration data to be loaded is output to a universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system through a complex programmable logic device of the master control clock board system according to a time sequence corresponding to the universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system, wherein the complex programmable logic device at least comprises: the time sequence conversion module is used for packaging configuration data into time sequence data of the universal asynchronous receiving and transmitting transmitter according to a time sequence required format corresponding to the universal asynchronous receiving and transmitting transmitter, and the data at least comprises the configuration data and a start operation log;
after the master control clock board system is detected to finish configuration data loading and the central processing unit of the master control clock board system finishes initialization of the universal asynchronous receiving and transmitting transmitter externally connected with the central processing unit, a starting operation log recorded with a starting operation process of the central processing unit is output to the universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system through control of a complex programmable logic device, wherein the alternative module of the universal asynchronous receiving and transmitting transmitter is used for selecting data needing to be output to the universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board, and time division multiplexing of the master control clock board system to the universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system is achieved.
2. The method of claim 1, wherein outputting, by the complex programmable logic device of the master clock board system, the configuration data to be loaded to the external UART transmitter of the master clock board system at a timing sequence corresponding to the external UART transmitter of the master clock board system when it is detected that the master clock board system needs to load the configuration data comprises:
under the condition that a central processing unit of the master control clock board system is detected to be required to load a hardware configuration word, outputting the hardware configuration word to a universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system through the complex programmable logic device according to a time sequence corresponding to the universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system;
and under the condition that the situation that a driver communicating with the complex programmable logic device needs to load field programmable gate array configuration data is detected, outputting the field programmable gate array configuration data to a universal asynchronous receiving and transmitting transmitter externally connected with a master control clock board system through the complex programmable logic device according to the time sequence corresponding to the universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system.
3. The method of claim 2, wherein outputting, by the complex programmable logic device, the hardware configuration word to a universal asynchronous receiver/transmitter (UART) externally connected to a master clock board system at a timing sequence corresponding to the UART externally connected to the master clock board system when detecting that a central processing unit of the master clock board system needs to load the hardware configuration word comprises:
and under the condition that the central processing unit is detected to be required to load the hardware configuration words, according to a time sequence required format corresponding to a universal asynchronous receiving and transmitting transmitter externally connected with the main control clock board system, packaging the preset number of hardware configuration words into universal asynchronous receiving and transmitting transmitter time sequence data when the complex programmable logic device receives the preset number of hardware configuration words, and outputting the universal asynchronous receiving and transmitting transmitter time sequence data to the universal asynchronous receiving and transmitting transmitter externally connected with the main control clock board system.
4. The method of claim 2, wherein in the case that it is detected that the driver in communication with the complex programmable logic device needs to load the configuration data of the field programmable gate array, outputting, by the complex programmable logic device, the configuration data of the field programmable gate array to the universal asynchronous transceiver transmitter externally connected to the master clock board system at a timing corresponding to the universal asynchronous transceiver transmitter externally connected to the master clock board system comprises:
under the condition that the driver needs to load the configuration data of the field programmable gate array, the complex programmable logic device acquires the configuration data of the field programmable gate array which is transmitted on a bus connected with the driver in parallel, and according to the required format of the time sequence corresponding to the universal asynchronous receiving and transmitting transmitter externally connected with the main control clock board system, after every time a preset number of configuration data of the field programmable gate array are acquired, the preset number of configuration data of the field programmable gate array are packaged into the time sequence data of the universal asynchronous receiving and transmitting transmitter, and the time sequence data of the universal asynchronous receiving and transmitting transmitter are output to the universal asynchronous receiving and transmitting transmitter externally connected with the main control clock board system.
5. The method of claim 2, further comprising: and under the condition of receiving preset data, determining that the driver needs to load the configuration data of the field programmable gate array.
6. A data monitoring device is applied to a master control clock board system, and is characterized by comprising:
the first control unit is configured to, when it is detected that a master clock board system needs to load configuration data, output the configuration data that needs to be loaded to a universal asynchronous transceiver transmitter externally connected to the master clock board system through a complex programmable logic device of the master clock board system in a timing sequence corresponding to the universal asynchronous transceiver transmitter externally connected to the master clock board system, where the complex programmable logic device at least includes: the time sequence conversion module is used for packaging configuration data into time sequence data of the universal asynchronous receiving and transmitting transmitter according to a time sequence required format corresponding to the universal asynchronous receiving and transmitting transmitter, and the data at least comprises the configuration data and a start operation log;
and the second control unit is used for outputting a starting operation log recorded with a starting operation process of the central processing unit to the universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system through the control of a complex programmable logic device after detecting that the master control clock board system finishes the loading of the configuration data and the central processing unit of the master control clock board system finishes the initialization of the universal asynchronous receiving and transmitting transmitter externally connected with the central processing unit, wherein the alternative universal asynchronous receiving and transmitting transmitter module is used for selecting data needing to be output to the universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board, and further realizing the time division multiplexing of the master control clock board system to the universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system.
7. The apparatus according to claim 6, wherein the first control unit is specifically configured to, when it is detected that a central processing unit of the master clock board system needs to load a hardware configuration word, output, by the complex programmable logic device, the hardware configuration word to a universal asynchronous transceiver transmitter externally connected to the master clock board system at a timing sequence corresponding to the universal asynchronous transceiver transmitter externally connected to the master clock board system;
and the field programmable gate array configuration data is output to the universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system through the complex programmable logic device according to the time sequence corresponding to the universal asynchronous receiving and transmitting transmitter externally connected with the master control clock board system under the condition that the situation that the field programmable gate array configuration data is required to be loaded by the driver communicated with the complex programmable logic device is detected.
8. The apparatus according to claim 7, wherein the first control unit is specifically configured to, when it is detected that the central processing unit needs to load a hardware configuration word, encapsulate, by the complex programmable logic device, a preset number of hardware configuration words into the universal asynchronous transceiver timing data every time the complex programmable logic device receives the preset number of hardware configuration words according to a timing requirement format corresponding to a universal asynchronous transceiver externally connected to the master clock board system, and output the universal asynchronous transceiver timing data to the universal asynchronous transceiver externally connected to the master clock board system.
9. The apparatus according to claim 7, wherein the first control unit is specifically configured to, when it is detected that the driver needs to load the fpga configuration data, obtain, through the complex programmable logic device, fpga configuration data that is transmitted in parallel on a bus connected to the driver, and package, according to a format required by a timing sequence corresponding to a usb transceiver externally connected to the main control clock board system, a preset number of fpga configuration data into the uart timing data after each obtained configuration data is obtained, and output the usb transceiver timing data to the usb transceiver externally connected to the main control clock board system.
10. A storage medium having stored thereon a computer program stream which, when executed, implements a data monitoring method as claimed in any one of claims 1 to 5.
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| CN106155706A (en) * | 2015-03-22 | 2016-11-23 | 联想(北京)有限公司 | Preserve electronic equipment and start the system and method for information |
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| US9449643B1 (en) * | 2015-04-24 | 2016-09-20 | Seagate Technology Llc | Data storage component test deck |
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| CN1874252A (en) * | 2005-06-01 | 2006-12-06 | 华为技术有限公司 | Serial-port mapping system for debugging single board |
| CN101692210A (en) * | 2009-09-28 | 2010-04-07 | 中兴通讯股份有限公司 | Single board starting monitoring system and monitoring method |
| US8732526B1 (en) * | 2011-06-24 | 2014-05-20 | Maxim Integrated Products, Inc. | Single-wire data interface for programming, debugging and testing a programmable element |
| CN105634788A (en) * | 2014-11-28 | 2016-06-01 | 中兴通讯股份有限公司 | Single board and single board management method and system |
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