CN108233920A - 3/4 dual-mode frequency divider - Google Patents
3/4 dual-mode frequency divider Download PDFInfo
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- CN108233920A CN108233920A CN201711371761.8A CN201711371761A CN108233920A CN 108233920 A CN108233920 A CN 108233920A CN 201711371761 A CN201711371761 A CN 201711371761A CN 108233920 A CN108233920 A CN 108233920A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
- H03K23/502—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits with a base or a radix other than a power of two
- H03K23/507—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits with a base or a radix other than a power of two with a base which is a non-integer
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
- H03K23/52—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits using field-effect transistors
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Abstract
3/4 dual-mode frequency divider, including：Six grades of dynamic latch, level-one phase inverter and level-one frequency dividing mode controller.Wherein, the first order, the second level and third level dynamic latch form first order d type flip flop；The fourth stage, level V, the 6th grade of dynamic latch, frequency dividing mode controller and phase inverter form second level d type flip flop.Dual-mode frequency divider in the present invention, simple in structure, number of transistors is few, and area is small, and critical path delay is small.Compared to traditional 3/4 dual-mode frequency divider based on MUX logic gates, 3/4 dual-mode frequency divider based on NOR logic gates and current newest 3/4 dual-mode frequency divider, maximum operating frequency improves 60.6%, 41.2% and 10.1% respectively, and power consumption reduces 25.1%, 6.7% and 3.3% respectively.
Description
Technical field
The present invention relates to 3/4 dual-mode frequency dividers of high-frequency low-power consumption.
Background technology
With the development of technology of Internet of things, power consumption has become the important indicator of IC system, and power consumption and work
The tradeoff of working frequency has become the core topic of circuit design.As a part important in frequency synthesizer, frequency divider
Design be also concerned.The frequency dividing ratio of traditional pre-divider, generally use 2/3,4/5 or bigger, and it is special for some
Frequency dividing ratio, such as 7-11 frequency dividings are easier to realize by the cascade of 3/4 frequency divider.Existing 3/4 frequency divider, generally use
Outer plus logic gate mode realizes that this method can not only increase power consumption and area between two-stage d type flip flop, can also increase pass
The delay in key path, causes maximum operation frequency to reduce.
Invention content
The present invention will overcome the disadvantages mentioned above of the prior art, provide a kind of base simple in structure, low in energy consumption, working frequency is high
In the 3/4 dual-mode frequency divider designing scheme for extending true single phase clock d type flip flop.
Technical solution is used by the present invention realizes above-mentioned purpose：
3/4 dual-mode frequency divider circuit is made of first order d type flip flop and second level d type flip flop；Input single-phase clock signal
CK, output square-wave signal Q2；When mode control signal MC is " 0 ", four frequency dividings are realized, when mode control signal MC is " 1 ",
Realize three frequency division；
Wherein, the first order d type flip flop includes：
First order dynamic latch, second level dynamic latch and third level dynamic latch；
The second level d type flip flop includes：
Fourth stage dynamic latch, level V dynamic latch, the 6th grade of dynamic latch, phase inverter and scheme control
Device；
By two-stage d type flip flop, three frequency division to input single-phase clock signal CK is realized in the control in different MC
Or four frequency dividing；
First order dynamic latch~six grade dynamic latch is all comprising dynamic latch unit, the dynamic latch
Device unit includes a PMOS tube and is formed with a NMOS tube；The source electrode of PMOS tube connects power supply, the source electrode ground connection of NMOS tube；
The first order, the third level, the drain electrode of PMOS tube of fourth stage dynamic latch, the drain electrode of NMOS tube and next stage dynamic
The grid of the PMOS tube of latch is connected, the second level, the drain electrode of PMOS tube of level V dynamic latch, the drain electrode of NMOS tube with
The grid of the NMOS tube of next stage dynamic latch is connected, the drain electrode of the PMOS tube of the 6th grade of dynamic latch, the leakage of NMOS tube
Pole is connected with the grid of the NMOS tube of phase inverter and the grid of PMOS tube, the first order, the second level, the fourth stage, level V dynamic locking
The grid of the NMOS tube of storage, the third level and the grid of the PMOS tube of the 6th grade of dynamic latch and input clock signal CK phases
Even；
The phase inverter includes：
One PMOS tube and a NMOS tube；The source electrode of PMOS tube connects power supply, the source electrode ground connection of NMOS tube, the leakage of PMOS tube
The drain electrode of pole, NMOS tube is connected with the grid of the PMOS tube of first order dynamic latch；
The frequency dividing mode controller includes two NMOS tubes；Divide mode controller a NMOS tube drain electrode with
The grid of the NMOS tube of 6th grade of dynamic latch is connected, and grid is connected with the grid of the NMOS tube of third level dynamic latch,
The drain electrode of another NMOS tube of the source electrode with dividing mode controller is connected；Divide the source of another NMOS tube of mode controller
Pole is grounded, and grid meets mode control signal MC.
Further, realize that the process of three frequency division is as follows：
Step 1, input clock CK first failing edge arrive before, output node is high level.Work as input clock
First failing edge of CK arrives, and the input node of second level d type flip flop becomes low level, due to the effect of mode controller,
Output node also becomes low level.
Step 2, first rising edge arrival as input clock CK, the input node of second level d type flip flop and output save
Point remains unchanged.
Step 3, second failing edge arrival as input clock CK, the input node of second level d type flip flop become high electricity
Flat, output node remains unchanged.
Step 4, second rising edge arrival as input clock CK, the input node of second level d type flip flop and output save
Point remains unchanged.High level to this input clock CK terminates, and output node completes the logic in two input clock CK periods
" 0 " is converted.
Step 5, the third failing edge arrival as input clock CK, the input node of second level d type flip flop become low electricity
Flat, output node becomes high level.
Step 6, the third rising edge arrival as input clock CK, the input node of second level d type flip flop and output save
Point remains unchanged.Low level to this input clock CK terminates, and output node completes the logic in an input clock CK period
" 1 " is converted.So far, the three frequency division operating mode of 3/4 dual-mode frequency divider of the invention completes a complete output period, patrols
Collect level " 0-0-1 ", and the cycle that will be repeated the above steps.
Advantages of the present invention：Circuit structure is simple；Area is small；Maximum operation frequency is high；It is low in energy consumption；7 PMOS are used
Pipe and 9 NMOS tubes, 16 transistors, realize 3/4 controllable dual-mode frequency divider, especially suitable in frequency synthesizer altogether
The pre-divider of digital control frequency divider.
Description of the drawings
Fig. 1 is the structure diagram of 3/4 dual-mode frequency divider of transistor level of the present invention.
Fig. 2 is logical simulation waveform diagram of 3/4 dual-mode frequency divider of the present invention under divide-by-three mode.
Specific embodiment
Invention is further illustrated below in conjunction with the accompanying drawings.
It is as shown in Figure 1, a kind of based on 3/4 dual-mode frequency divider circuit of transistor level for extending true single phase clock d type flip flop.By
First d type flip flop DFF1 and the second d type flip flop DFF2 compositions.Wherein, the first d type flip flop DFF1 is by the first PMOS tube PM1, second
PMOS tube PM2, third PMOS tube PM3, the first NMOS tube NM1, the second NMOS tube NM2, third NMOS tube NM3 compositions, the 2nd D are touched
Device DFF2 is sent out by the 4th PMOS tube PM4, the 5th PMOS tube PM5, the 6th PMOS tube PM6, the 7th PMOS tube PM7, the 4th NMOS tube
NM4, the 5th NMOS tube NM5, the 6th NMOS tube NM6, the 7th NMOS tube NM7, the 8th NMOS tube NM8 and the 9th NMOS tube NM9 groups
Into.The source electrode of first PMOS tube PM1 connects power supply, the drain electrode of the first PMOS tube PM1, the drain electrode and second of the first NMOS tube NM1
The grid of PMOS tube PM2 is connected, the source electrode ground connection of the first NMOS tube NM1；The source electrode of second PMOS tube PM2 connects power supply, and second
The drain electrode of PMOS tube PM2, the drain electrode of the second NMOS tube NM2 are connected with the grid of third NMOS tube NM3, the second NMOS tube NM2's
Source electrode is grounded；The source electrode of third PMOS tube PM3 connects power supply, the drain electrode of third PMOS tube PM3, the drain electrode of third NMOS tube NM3 with
The grid of 4th PMOS tube PM4 is connected, the source electrode ground connection of third NMOS tube NM3；The source electrode of 4th PMOS tube PM4 connects power supply, the
The drain electrode of four PMOS tube PM4, the drain electrode of the 4th NMOS tube NM4 are connected with the grid of the 5th PMOS tube PM5, the 4th NMOS tube NM4
Source electrode ground connection；The source electrode of 5th PMOS tube PM5 connects power supply, the drain electrode of the 5th PMOS tube PM5, the drain electrode of the 5th NMOS tube NM5
It is connected with the grid of the 6th NMOS tube NM6, the source electrode ground connection of the 5th NMOS tube NM5；The source electrode of 6th PMOS tube PM6 connects power supply,
The drain electrode of 6th PMOS tube PM6, the drain electrode of the 6th NMOS tube NM6, the grid of the 7th PMOS tube PM7 and the 7th NMOS tube NM7
Grid is connected, the source electrode ground connection of the 6th NMOS tube NM6；The source electrode of 7th PMOS tube PM7 connects power supply, the leakage of the 7th PMOS tube PM7
Pole, the drain electrode of the 7th NMOS tube NM7 and the grid of the first PMOS tube PM1 are connected to output terminal, and the source electrode of the 7th NMOS tube NM7 connects
Ground；The drain electrode of 8th NMOS tube NM8 and the drain electrode, the drain electrode of the 5th NMOS tube NM5, the 6th NMOS tube NM6 of the 5th PMOS tube PM5
Grid be connected, the drain electrode of the grid of the 8th NMOS tube NM8 and the second PMOS tube PM2, the drain electrode of the second NMOS tube NM2, third
The grid of NMOS tube NM3 is connected, and the source electrode of the 8th NMOS tube NM8 is connected with the drain electrode of the 9th NMOS tube NM9, the 9th NMOS tube
The source electrode ground connection of NM9, the grid of the 9th NMOS tube NM9 are connected with frequency dividing mode control signal MC；The grid of first NMOS tube NM1
Pole, the grid of the second NMOS tube NM2, the grid of third PMOS tube PM3, the 4th NMOS tube NM4 grid, the 5th NMOS tube NM5
Grid and the grid of the 6th PMOS tube PM6 be connected to signal input part.
It is proposed by the present invention a kind of based on 3/4 dual-mode frequency divider circuit of transistor level for extending true single phase clock d type flip flop
Design, basic principle is：When mode control signal MC is " 0 ", the 9th NMOS tube NM9 shutdowns, mode controller is in
Invalid state, entire circuit are composed in series by two d type flip flops, realize the function of four frequency dividings；When mode control signal MC is " 1 "
When, the 8th NMOS tube NM8 is connected to the ground, circuit is made to enter divide-by-three mode by the 9th NMOS tube NM9 conductings.The present invention proposes
3/4 dual-mode frequency divider of transistor level input clock CK failing edge arrive when, output generate variation, so be one decline
Along the dual-mode frequency divider of triggering.By the improvement to mode controller, reduce the quantity of circuit transistor, reduce area,
The power consumption of integrated circuit is reduced, shortens critical path delay of the circuit under divide-by-three mode, improves the maximum of circuit
Working frequency.With reference to table 1, simulation result is based on smic40nmCMOS technology libraries, and simulated conditions are typical-typical techniques
Angle, 1.1V supply voltages and 300K temperature are patrolled compared to traditional 3/4 dual-mode frequency divider based on NOR logic gates and based on MUX
3/4 dual-mode frequency divider of door is collected, maximum operation frequency improves 41.2% and 60.6% respectively, compared to newest 3/4 bimodulus
Frequency divider, maximum operation frequency improve 10.1%；When working frequency is 4GHz under divide-by-three mode, compared to traditional base
3/4 dual-mode frequency divider in NOR logic gates and 3/4 dual-mode frequency divider based on MUX logic gates, power consumption reduce 25.1% respectively
With 6.7%, compared to newest 3/4 dual-mode frequency divider, lower power consumption 3.3%.
| Maximum operation frequency (GHz) | Operating current (uA) when 4GHz is inputted | |
| The present invention | 7.2 | 173.2 |
| Newest structure | 6.5 | 179 |
| Structure based on NOR logic gates | 5.1 | 184.8 |
| The structure of backbone MUX logic gates | 4.5 | 216.7 |
Table 1
The state transformational relation that 3/4 dual-mode frequency divider in the present invention works under divide-by-three mode is as shown in table 2：
Table 2
With reference to Fig. 2, the specific implementation step to work under divide-by-three mode is as follows：
Step 1, input clock CK first failing edge arrive before, node T1, T2, T4, T5 and Qn2 be low electricity
Flat, node Qn1 and Q2 are high level.As first failing edge arrival of input clock CK, third NMOS tube NM3, the 8th NMOS
Pipe NM8, the 7th NMOS tube NM7, the first PMOS tube PM1, the second PMOS tube PM2, third PMOS tube PM3, the 4th PMOS tube PM4 and
6th PMOS tube PM6 is connected, and node T1, T2, T4 and Qn2 become high level, and node Qn1 and Q2 become low level, remaining node
It is constant.
Step 2, first rising edge arrival as input clock CK, the first NMOS tube NM1, the second NMOS tube NM2, the 4th
NMOS tube NM4, the 5th NMOS tube NM5, the 7th NMOS tube NM7 and the 4th PMOS tube PM4 conductings, node T2 become low level,
Remaining node is constant.
Step 3 arrives when second failing edge of input clock CK, the 7th NMOS tube NM7, third PMOS tube PM3 and the
Six PMOS tube PM6 are connected, and node Qn1 becomes high level, remaining node is constant.
Step 4, second rising edge arrival as input clock CK, the first NMOS tube NM1, the second NMOS tube NM2, the 4th
NMOS tube NM4, the 5th NMOS tube NM5, the 7th NMOS tube NM7, the first PMOS tube PM1 and the 5th PMOS tube PM5 conductings, node T4
Become low level, remaining node is constant.High level to this input clock CK terminates, when output node Q2 completes two inputs
The logical zero conversion in clock CK periods.
Step 5, the third failing edge arrival as input clock CK, the 6th NMOS tube NM6, third PMOS tube PM3, the 5th
PMOS tube PM5, the 6th PMOS tube PM6 and the 7th PMOS tube PM7 conductings, node Qn2 become low level, and node T5, Q2 become high
Level, remaining node are constant.
Step 6, the third rising edge arrival as input clock CK, the first NMOS tube NM1, the second NMOS tube NM2, the 4th
NMOS tube NM4, the 5th NMOS tube NM5, the second PMOS tube PM2, the 5th PMOS tube PM5 and the 7th PMOS tube PM7 conductings, node T1
Become low level with T5, remaining node is constant.Low level to this input clock CK terminates, output node Q2 complete one it is defeated
Enter the logic " 1 conversion " in clock CK periods, so far, the three frequency division operating mode of 3/4 dual-mode frequency divider of the invention completes one
A complete output period, logic level " 0-0-1 ", and the cycle that will be repeated the above steps.
Content described in this specification embodiment is only enumerating to the way of realization of inventive concept, protection of the invention
Range is not construed as being only limitted to the concrete form that embodiment is stated, protection scope of the present invention is also and in art technology
Personnel according to present inventive concept it is conceivable that equivalent technologies mean.
Claims (2)
1.3/4 dual-mode frequency divider circuit, it is characterised in that：It is made of first order d type flip flop and second level d type flip flop；Input is single
Clock signal CK, output square-wave signal Q2；When mode control signal MC is " 0 ", realizes four frequency dividings, work as mode control signal
When MC is " 1 ", three frequency division is realized；
Wherein, the first order d type flip flop includes：
First order dynamic latch, second level dynamic latch and third level dynamic latch；
The second level d type flip flop includes：
Fourth stage dynamic latch, level V dynamic latch, the 6th grade of dynamic latch, phase inverter and mode controller；
By two-stage d type flip flop, three frequency division or four to input single-phase clock signal CK is realized in the control in different MC
Frequency dividing；
First order dynamic latch~six grade dynamic latch is all comprising dynamic latch unit, the dynamic latch list
Member includes a PMOS tube and is formed with a NMOS tube；The source electrode of PMOS tube connects power supply, the source electrode ground connection of NMOS tube；
The first order, the third level, the drain electrode of PMOS tube of fourth stage dynamic latch, the drain electrode of NMOS tube and next stage dynamic latch
The grid of the PMOS tube of device is connected, the second level, the drain electrode of PMOS tube of level V dynamic latch, the drain electrode of NMOS tube with it is next
The grid of NMOS tube of grade dynamic latch is connected, the drain electrode of the PMOS tube of the 6th grade of dynamic latch, the drain electrode of NMOS tube with
The grid of the NMOS tube of phase inverter is connected with the grid of PMOS tube, the first order, the second level, the fourth stage, level V dynamic latch
The grid of NMOS tube, the third level is connected with the grid of the PMOS tube of the 6th grade of dynamic latch with input clock signal CK；
The phase inverter includes：
One PMOS tube and a NMOS tube；The source electrode of PMOS tube connects power supply, and the source electrode of NMOS tube is grounded, the drain electrode of PMOS tube,
The drain electrode of NMOS tube is connected with the grid of the PMOS tube of first order dynamic latch；
The frequency dividing mode controller includes two NMOS tubes；Divide the drain electrode and the 6th of a NMOS tube of mode controller
The grid of the NMOS tube of grade dynamic latch is connected, and grid is connected with the grid of the NMOS tube of third level dynamic latch, source electrode
The drain electrode of another NMOS tube with dividing mode controller is connected；The source electrode for dividing another NMOS tube of mode controller connects
Ground, grid meet mode control signal MC.
2. suitable for 3/4 dual-mode frequency divider circuit described in claim 1, it is characterised in that：Realize that the process of three frequency division is as follows：
Step 1, input clock CK first failing edge arrive before, output node is high level.When input clock CK's
First failing edge arrives, and the input node of second level d type flip flop becomes low level, due to the effect of mode controller, output
Node also becomes low level.
Step 2, first rising edge arrival as input clock CK, the input node and output node of second level d type flip flop are protected
It holds constant.
Step 3, second failing edge arrival as input clock CK, the input node of second level d type flip flop becomes high level, defeated
Egress remains unchanged.
Step 4, second rising edge arrival as input clock CK, the input node and output node of second level d type flip flop are protected
It holds constant.High level to this input clock CK terminates, and the logical zero that output node completes two input clock CK periods turns
It changes.
Step 5, the third failing edge arrival as input clock CK, the input node of second level d type flip flop becomes low level, defeated
Egress becomes high level.
Step 6, the third rising edge arrival as input clock CK, the input node and output node of second level d type flip flop are protected
It holds constant.Low level to this input clock CK terminates, and the logical one that output node completes an input clock CK period turns
It changes.So far, the three frequency division operating mode of 3/4 dual-mode frequency divider of the invention completes a complete output period, logic electricity
Flat " 0-0-1 ", and the cycle that will be repeated the above steps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711371761.8A CN108233920A (en) | 2017-12-19 | 2017-12-19 | 3/4 dual-mode frequency divider |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711371761.8A CN108233920A (en) | 2017-12-19 | 2017-12-19 | 3/4 dual-mode frequency divider |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111835339A (en) * | 2020-07-21 | 2020-10-27 | 上海集成电路研发中心有限公司 | Frequency division unit and multi-mode frequency divider |
| US11342927B1 (en) | 2021-06-28 | 2022-05-24 | Qualcomm Incorporated | Ring oscillator based frequency divider |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111835339A (en) * | 2020-07-21 | 2020-10-27 | 上海集成电路研发中心有限公司 | Frequency division unit and multi-mode frequency divider |
| CN111835339B (en) * | 2020-07-21 | 2024-05-28 | 上海集成电路研发中心有限公司 | Frequency dividing unit and multi-mode frequency divider |
| US11342927B1 (en) | 2021-06-28 | 2022-05-24 | Qualcomm Incorporated | Ring oscillator based frequency divider |
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Application publication date: 20180629 |