CN108233895A - A kind of phase inverter and its driving method, shift register cell, display device - Google Patents
A kind of phase inverter and its driving method, shift register cell, display device Download PDFInfo
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- CN108233895A CN108233895A CN201810117060.XA CN201810117060A CN108233895A CN 108233895 A CN108233895 A CN 108233895A CN 201810117060 A CN201810117060 A CN 201810117060A CN 108233895 A CN108233895 A CN 108233895A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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Abstract
The present invention discloses a kind of phase inverter and its driving method, shift register cell, display device, is related to display technology field, the job stability to solve the problem of phase inverter in the prior art is relatively low.The phase inverter, including：First pull-up module, under the control of the first clock signal input terminal, whether the first level signal input terminal of control to connect with signal output end；Second pull-up module, under the control of second clock signal input part, whether the first level signal input terminal of control to connect with signal output end；Pull-down module is exported, under the control at input control end, control signal output and the no connection of second electrical level signal input part.Phase inverter provided by the invention is for output and the signal of input terminal reverse phase.
Description
Technical field
The present invention relates to display technology field more particularly to a kind of phase inverter and its driving method, shift register cell,
Display device.
Background technology
Often use phase inverter in display field, display panel, the major function of phase inverter be by input signal into
It is exported after 180 ° of overturnings of row, the high level of signal is represented with binary numeral 1, binary numeral 0 represents that the low level of signal is
Example, when the signal inputted to phase inverter is 1, the signal exported from phase inverter is 0, when the signal inputted to phase inverter is 0
When, the signal exported from phase inverter is 1.
Since phase inverter of the prior art generally comprises two modules, i.e. pull-up module and pull-down module, in phase inverter
Normal operating conditions in, pull-up module need for a long time it is in running order so that the transistor in pull-up module easily goes out
The problem of existing threshold voltage shift, and then cause the job stability of phase inverter relatively low.
Invention content
The purpose of the present invention is to provide a kind of phase inverter and its driving method, shift register cell, display devices, use
It is relatively low in the job stability for solving the problem of phase inverter in the prior art.
To achieve these goals, the present invention provides following technical solution：
The first aspect of the present invention provides a kind of phase inverter, including：
First pull-up module, respectively with the first level signal input terminal, the first clock signal input terminal and signal output end
Connection, under the control of first clock signal input terminal, controlling the first level signal input terminal and the letter
Whether number output terminal connects；
Second pull-up module, respectively with the first level signal input terminal, second clock signal input part and the letter
Number output terminal connection, under the control of the second clock signal input part, controlling the first level signal input terminal
Whether it is connect with the signal output end；
Pull-down module is exported, is connect respectively with input control end, the signal output end and second electrical level signal input part,
For under the control at the input control end, controlling the signal output end and the no company of second electrical level signal input part
It connects.
Further, first pull-up module includes first switch pipe and second switch pipe；Wherein, the first switch
The grid of pipe is connect with first clock signal input terminal, the first pole of the first switch pipe and first level signal
Input terminal connects, and the second pole of the first switch pipe is connect with first node；The grid of the second switch pipe and described the
One node connects, and the first pole of the second switch pipe is connect with the first level signal input terminal, the second switch pipe
The second pole connect with the signal output end；
Second pull-up module includes third switching tube and the 4th switching tube；Wherein, the grid of the third switching tube
It is connect with the second clock signal input part, the first pole of the third switching tube connects with the first level signal input terminal
It connects, the second pole of the third switching tube is connect with second node；The grid of 4th switching tube connects with the second node
It connects, the first pole of the 4th switching tube is connect with the first level signal input terminal, the second pole of the 4th switching tube
It is connect with the signal output end；
The output pull-down module includes the 5th switching tube, and grid and the input control end of the 5th switching tube connect
It connects, the first pole of the 5th switching tube is connect with the signal output end, the second pole of the 5th switching tube and described the
Two level signal input terminals connect.
Further, first pull-up module further includes the first capacitance, the first end of first capacitance and described the
One node connects, and the second end of first capacitance is connect with the signal output end；And/or
Second pull-up module further includes the second capacitance, and first end and the second node of second capacitance connect
It connects, the second end of second capacitance is connect with the signal output end.
Further, the phase inverter further includes：
First node control module, respectively with the second clock signal input part, the second electrical level signal input part
It is connected with the first node, under the control of the second clock signal input part, controlling the first node and institute
State whether second electrical level signal input part connects；And/or
Second node control module, respectively with first clock signal input terminal, the second electrical level signal input part
It is connected with the second node, under the control of first clock signal input terminal, controlling the second node and institute
State whether second electrical level signal input part connects.
Further, the first node control module includes the 6th switching tube, the grid of the 6th switching tube and institute
The connection of second clock signal input part is stated, the first pole of the 6th switching tube is connect with the first node, and the described 6th opens
The second pole for closing pipe is connect with the second electrical level signal input part；
The second node control module includes the 7th switching tube, grid and first clock of the 7th switching tube
Signal input part connects, and the first pole of the 7th switching tube is connect with the second node, and the second of the 7th switching tube
Pole is connect with the second electrical level signal input part.
Further, the phase inverter further includes：
First node pull-down module, respectively with the input control end, the first node and the second electrical level signal
Input terminal connects, under the control at the input control end, controlling the first node and the second electrical level signal defeated
Enter whether end connects；And/or
Second node pull-down module, respectively with the input control end, the second node and the second electrical level signal
Input terminal connects, under the control at the input control end, controlling the second node and the second electrical level signal defeated
Enter whether end connects.
Further, the first node pull-down module includes the 8th switching tube, the grid of the 8th switching tube and institute
The connection of input control end is stated, the first pole of the 8th switching tube connect with the first node, and the of the 8th switching tube
Two poles are connect with the second electrical level signal input part；
The second node pull-down module includes the 9th switching tube, grid and the input control of the 9th switching tube
End connection, the first pole of the 9th switching tube connect with the second node, the second pole of the 9th switching tube with it is described
Second electrical level signal input part connects.
Based on the technical solution of above-mentioned phase inverter, the second aspect of the present invention provides a kind of shift register cell, including
Above-mentioned phase inverter.
Based on the technical solution of above-mentioned shift register cell, the third aspect of the present invention provides a kind of display device, packet
Include above-mentioned shift register cell.
Based on the technical solution of above-mentioned phase inverter, the fourth aspect of the present invention provides a kind of driving method of phase inverter, uses
In driving above-mentioned phase inverter, the driving method includes：The first phase inverting step is performed in the first driving stage, rank is driven second
The second phase inverting steps of Duan Zhihang；The first driving stage includes the be arranged alternately first driving period and the second driving period；
First phase inverting step includes：
The period is driven described first, input control end input second electrical level, the first pull-up module is in the first clock signal
Under the control of input terminal, the first level signal input terminal is controlled to be connect with the signal output end；
The period is driven described second, the input control end inputs second electrical level, and the second pull-up module is in second clock
Under the control of signal input part, the first level signal input terminal is controlled to be connect with the signal output end；
Second phase inverting step includes：
The input control end inputs the first level, and output pull-down module is under the control at the input control end, control
The signal output end is connect with the second electrical level signal input part.
In technical solution provided by the invention, phase inverter includes the first pull-up module, the second pull-up module and pull-down module.
The period is driven first, the second pull-up module is in off position, only controls the first level signal by the first pull-up module
Input terminal is connect with signal output end so that signal output end can export the first level signal.And the period is driven second, the
One pull-up module is in off position, only controls the first level signal input terminal and signal output end by the second pull-up module
Connection, so that signal output end can export the first level signal.It can be seen that phase inverter provided in an embodiment of the present invention can
The first pull-up module and the second pull-up module is controlled to work alternatively, is avoided only by a pull-up module for a long time in work
The problem of mould transistor in the block is susceptible to threshold voltage shift caused by state, it is therefore, provided in an embodiment of the present invention
Phase inverter has better stability.
Description of the drawings
Attached drawing described herein is used to provide further understanding of the present invention, and forms the part of the present invention, this hair
Bright illustrative embodiments and their description do not constitute improper limitations of the present invention for explaining the present invention.In the accompanying drawings：
Fig. 1 is the structure diagram of phase inverter in the prior art；
Fig. 2 is the first module diagram of phase inverter in the embodiment of the present invention；
Fig. 3 is the second module diagram of phase inverter in the embodiment of the present invention；
Fig. 4 is the structure diagram of phase inverter in the embodiment of the present invention；
Fig. 5 is the working timing figure of phase inverter in the embodiment of the present invention.
Reference numeral：
S1- pull-up modules, S2- pull-down modules,
The first pull-up modules of 1-, the second pull-up modules of 2-,
3- output pull-down modules, 4- first node control modules,
5- second node control modules, 6- first node pull-down modules,
7- second node pull-down modules, V1- the first level signal input terminals,
The first clock signal input terminals of CLKA-, VOUT- signal output ends,
CLKB- second clock signal input parts, VIN- input controls end,
V2- second electrical level signal input parts, N1- first nodes,
N2- second nodes, the first capacitances of C1-,
The second capacitances of C2-, T1- first switch pipes,
T2- second switch pipes, T3- third switching tubes,
The 4th switching tubes of T4-, the 5th switching tubes of T5-,
The 6th switching tubes of T6-, the 7th switching tubes of T7-,
The 8th switching tubes of T8-, the 9th switching tubes of T9-,
P1- first drives the stage, and P11- first drives the period,
P12- second drives the period, and P2- second drives the stage.
Specific embodiment
It is embodiment provides in order to further illustrate the present invention phase inverter and its driving method, shift register cell, aobvious
Showing device is described in detail with reference to the accompanying drawings of the specification.
As stated in the Background Art, referring to Fig. 1, phase inverter of the prior art generally comprises pull-up module S1 and lower drawing-die
Block S2, in normal operation, the transistor that pull-up module S1 includes are constantly in working condition, when transistor uses oxygen
During compound thin film transistor (TFT), the problem of being susceptible to threshold voltage shift, and then cause the job stability of phase inverter relatively low.
Presence based on the above problem, the present inventor it has been investigated that, can pass through set two pull-up modules
It works alternatively to solve the above problems, specifically, referring to Fig. 2, an embodiment of the present invention provides a kind of phase inverter, including：
First pull-up module 1, respectively with the first level signal input terminal V1, the first clock signal input terminal CLKA and signal
Output terminal VOUT connections, under the control of the first clock signal input terminal CLKA, controlling the first level signal input terminal V1
Whether it is connect with signal output end VOUT；
Second pull-up module 2, respectively with the first level signal input terminal V1, second clock signal input part CLKB and signal
Output terminal VOUT connections, under the control of second clock signal input part CLKB, controlling the first level signal input terminal V1
Whether it is connect with signal output end VOUT；
Export pull-down module 3, respectively with input control end VIN, signal output end VOUT and second electrical level signal input part
V2 connections, under the control of input control end VIN, control signal output VOUT and second electrical level signal input part V2 to be no
Connection.
Above-mentioned phase inverter is in specific works, and first is performed instead including two driving stages, and in the first driving stage P1
To step, the second reverse step is performed in the second driving stage P2；Wherein first driving stage P1 included be arranged alternately first
Drive the drivings of period P11 and second period P12.
Period P11 is driven first：Input control end VIN inputs second electrical level, and output pull-down module 3 is at input control end
Under the control of VIN, control signal output VOUT is not connected to second electrical level signal input part V2.First pull-up module 1 is
Under the control of one clock signal input terminal CLKA, the first level signal input terminal V1 of control is connect with signal output end VOUT, from
And signal output end VOUT is enabled to export the first level signal.Meanwhile the drawing-die on first driving period P11, second
Block 2 is in idle state under the control of second clock signal input part CLKB, it is achieved thereby that in first driving
Section P11 only exports the first level signal by 1 control signal output VOUT of the first pull-up module.
Period P12 is driven second：Input control end VIN continues to input second electrical level, and output pull-down module 3 is controlled in input
Under the control of end VIN processed, continue control signal output VOUT and second electrical level signal input part V2 and be not connected to.Drawing-die on second
Block 2 is under the control of second clock signal input part CLKB, the first level signal input terminal V1 of control and signal output end VOUT
Connection, so that signal output end VOUT can export the first level signal.Meanwhile this second driving period P12, first
Pull-up module 1 under the control of the first clock signal input terminal CLKA in idle state, it is achieved thereby that this second
Period P12 is driven only to export the first level signal by 2 control signal output VOUT of the second pull-up module.
Stage P2 is driven second：First pull-up module 1 is under the control of the first clock signal input terminal CLKA in not
The state of work, the second pull-up module 2 are in idle state under the control of second clock signal input part CLKB.Input
Control terminal VIN inputs the first level, and output pull-down module 3 is under the control of input control end VIN, control signal output VOUT
It is connect with second electrical level signal input part V2, so that signal output end VOUT exports second electrical level signal.
The concrete structure and the course of work of the phase inverter provided according to above-described embodiment are it is found that provided in an embodiment of the present invention
Phase inverter includes the first pull-up module 1, the second pull-up module 2 and output pull-down module 3.First drive period P11, second
Pull-up module 2 is in off position, only the first level signal input terminal V1 is controlled to be exported with signal by the first pull-up module 1
Hold VOUT connections so that signal output end VOUT can export the first level signal.And period P12 is driven second, on first
Drawing-die block 1 is in off position, only controls the first level signal input terminal V1 and signal output end by the second pull-up module 2
VOUT connections, so that signal output end VOUT can export the first level signal.It is it can be seen that provided in an embodiment of the present invention anti-
Phase device can control the first pull-up module 1 and the second pull-up module 2 to work alternatively, avoid only by a pull-up module it is long when
Between it is in running order caused by mould transistor in the block the problem of being susceptible to threshold voltage shift, therefore, the present invention is real
The phase inverter for applying example offer has better job stability, and signal output end VOUT can export more stable signal.
The first pull-up module 1, the second pull-up module 2 and the concrete structure for exporting pull-down module 3 that above-described embodiment provides
It is varied, a kind of corresponding concrete structure of each module is given below, and to the work of the phase inverter under this concrete structure
Process is described in detail.
As shown in figure 4, above-mentioned first pull-up module 1 includes first switch pipe T1 and second switch pipe T2；Wherein, it first opens
The grid for closing pipe T1 is connect with the first clock signal input terminal CLKA, and the first pole of first switch pipe T1 and the first level signal are defeated
Enter V1 is held to connect, the second pole of first switch pipe T1 is connect with first node N1；The grid and first node of second switch pipe T2
Connection, the first pole of second switch pipe T2 are connect with the first level signal input terminal V1, the second pole and the letter of second switch pipe T2
Number output terminal VOUT connections.
Second pull-up module 2 includes 3 and the 4th switch transistor T 4 of third switch transistor T；Wherein, the grid of third switch transistor T 3 with
The CLKB connections of second clock signal input part, the first pole of third switch transistor T 3 are connect with the first level signal input terminal V1, the
Second pole of three switch transistor Ts 3 is connect with second node N2；The grid of 4th switch transistor T 4 is connect with second node, the 4th switch
The first pole of pipe T4 is connect with the first level signal input terminal V1, and the second pole and the signal output end VOUT of the 4th switch transistor T 4 connect
It connects.
It exporting pull-down module 3 and includes the 5th switch transistor T 5, the grid of the 5th switch transistor T 5 is connect with input control end VIN,
First pole of the 5th switch transistor T 5 is connect with signal output end VOUT, and the second pole of the 5th switch transistor T 5 and second electrical level signal are defeated
Enter V2 is held to connect.
Specifically, the first driving period P11, the first clock signal input terminal CLKA control in the first driving stage P1
First switch pipe T1 is connected so that the first level signal input terminal V1 is connect with first node N1, is inputted by the first level signal
First level signal of end V1 inputs is transmitted to first node N1.First node N1 control second switch pipe T2 conductings, make first
Level signal input terminal V1 is connect with signal output end VOUT, so that first by the first level signal input terminal V1 inputs
Level signal is transmitted to signal output end VOUT, realizes that signal output end VOUT can export the first level signal.
End simultaneously in the first driving period P11, second clock signal input part CLKB control third switch transistor T 3, make
First level signal input terminal V1 and second node N2 is not connected to, so that the 4th switch transistor T 4 is also at cut-off state, it is real
Show the second pull-up module 2 and be in off position.In the 5th switch of the first driving period P11, input control end VIN control
Pipe T5 ends so that signal output end VOUT is not connected to second electrical level signal input part V2.
The second driving period P12, second clock signal input part CLKB control third in the first driving stage P1 is opened
Pipe T3 conductings are closed, the first level signal input terminal V1 is made to be connect with second node N2, are inputted by the first level signal input terminal V1
The first level signal be transmitted to second node N2.Second node N2 controls the 4th switch transistor T 4 to be connected, and makes the first level signal
Input terminal V1 is connect with signal output end VOUT, so that the first level signal inputted by the first level signal input terminal V1
Signal output end VOUT is transmitted to, realizes that signal output end VOUT can export the first level signal.
Simultaneously in second driving period P12, the first clock signal input terminal CLKA control first switch pipe T1 cut-offs, make
First level signal input terminal V1 and first node N1 is not connected to, so that second switch pipe T2 is also at cut-off state, it is real
Show the first pull-up module 1 and be in off position.In the 5th switch of the second driving period P12, input control end VIN control
Pipe T5 ends so that signal output end VOUT is not connected to second electrical level signal input part V2.
Stage P2, first switch pipe T1, second switch pipe T2,3 and the 4th switch transistor T 4 of third switch transistor T are driven second
It is turned off so that the first pull-up module 1 and the second pull-up module 2 are in off position.It is defeated in second driving stage P2
Entering control terminal VIN controls the 5th switch transistor T 5 to be connected so that and signal output end VOUT is connect with second electrical level signal input part V2,
So that by the second electrical level signal transmission that second electrical level signal input part V2 is inputted to signal output end VOUT, signal output is realized
End VOUT can export second electrical level signal.
Please continue to refer to Fig. 4, the first pull-up module 1 that above-described embodiment provides further includes the first capacitance C1, the first capacitance
The first end of C1 is connect with first node N1, and the second end of the first capacitance C1 is connect with signal output end VOUT；It is and/or above-mentioned
Second pull-up module 2 further includes the second capacitance C2, and the first end of the second capacitance C2 is connect with second node N2, the second capacitance C2's
Second end is connect with signal output end VOUT.
Specifically, when above-mentioned first pull-up module 1 includes the first capacitance C1, period P11, first switch are driven first
Pipe T1 and second switch pipe T2 are sequentially turned on, and after first switch pipe T1 conductings, the current potential of first node N1 becomes the first level,
After second switch pipe T2 conductings, the second end current potential raising of the first capacitance C1, and due to the coupling of capacitance so that first
The current potential raising of the first end of capacitance C1, so that the current potential of first node N1 has further been lifted, and the current potential of first node N1
After obtaining lifting, second switch pipe T2 can just be in full open position under the control of first node N1, so as to avoid
The threshold voltage of second switch pipe T2 has an impact the first level signal for being transmitted to signal output end VOUT, makes phase inverter more
Good realizes rail-to-rail output.
Similarly, when above-mentioned second pull-up module 2 includes the second capacitance C2, period P12, third switching tube are driven second
T3 and the 4th switch transistor T 4 sequentially turn on, and after the conducting of third switch transistor T 3, the current potential of second node N2 becomes the first level,
After the conducting of 4th switch transistor T 4, the second end current potential raising of the second capacitance C2, and due to the coupling of capacitance so that the second electricity
Hold the current potential raising of the first end of C2, so as to further be lifted the current potential of second node N2, and the current potential of second node N2 obtains
To after lifting, the 4th switch transistor T 4 can just be in full open position under the control of second node N2, so as to avoid
The threshold voltage of four switch transistor Ts 4 has an impact the first level signal for being transmitted to signal output end VOUT, makes phase inverter more preferable
Realize rail-to-rail output.
As shown in figure 3, the phase inverter that above-described embodiment provides further includes：First node control module 4, respectively with second when
Clock signal input part CLKB, second electrical level signal input part V2 are connected with first node N1, for being inputted in second clock signal
Under the control for holding CLKB, whether control first node N1 connect with second electrical level signal input part V2；And/or second node control
Molding block 5 is connect respectively with the first clock signal input terminal CLKA, second electrical level signal input part V2 and second node N2, is used
Under the control in the first clock signal input terminal CLKA, whether control second node N2 and second electrical level signal input part V2 connects
It connects.
Specifically, the first driving period P11 in the first driving stage P1, second clock signal input part CLKB's
Under control, first node control module 4 controls first node N1 and second electrical level signal input part V2 to be not connected to；Meanwhile
Under the control of one clock signal input terminal CLKA, second node control module 5 controls second node N2 and second electrical level signal defeated
Enter V2 is held to connect.
The second driving period P12 in the first driving stage P1, under the control of second clock signal input part CLKB,
First node control module 4 controls first node N1 to be connect with second electrical level signal input part V2；Meanwhile in the first clock signal
Under the control of input terminal CLKA, second node control module 5 controls second node N2 and second electrical level signal input part V2 not connect
It connects.
The phase inverter that above-described embodiment provides includes first node control module 4 and second node control module 5 so that
First pull-up module 1 is in running order, and when the second pull-up module 2 is in off position, second node control can be passed through
Molding block 5 drags down the current potential of second node N2, so as to which second node N2 be avoided to be in floating state, passes through the second capacitance C2's
Coupling has an impact the signal output end VOUT signals exported.Similarly, it is in the shape that do not work in the first pull-up module 1
State, and when the second pull-up module 2 is in running order, can be by first node control module 4 by the current potential of first node N1
It drags down, so as to which first node N1 be avoided to be in floating state, second switch pipe T2 is made by the coupling of the second capacitance C1
With, and then the signal of signal output end VOUT outputs is had an impact.Therefore, the phase inverter that above-described embodiment provides includes first
When node control module 4 and second node control module 5, can avoid signal output end VOUT export signal in there are noises
Signal.
Further, please continue to refer to Fig. 4, the first node control module 4 that above-described embodiment provides includes the 6th switch
Pipe T6, the grid of the 6th switch transistor T 6 are connect with second clock signal input part CLKB, the first pole of the 6th switch transistor T 6 and the
One node N1 connections, the second pole of the 6th switch transistor T 6 are connect with second electrical level signal input part V2；Second node control module 5
Including the 7th switch transistor T 7, the grid of the 7th switch transistor T 7 is connect with the first clock signal input terminal CLKA, the 7th switch transistor T 7
The first pole connect with second node N2, the second pole of the 7th switch transistor T 7 is connect with second electrical level signal input part V2.
Specifically, the first driving period P11 in the first driving stage P1, second clock signal input part CLKB's
Under control, the 6th switch transistor T 6 is ended so that first node N1 is not connected to second electrical level signal input part V2；Meanwhile
Under the control of one clock signal input terminal CLKA, the 7th switch transistor T 7 is connected so that second node N2 and second electrical level signal are defeated
Enter V2 is held to connect.
The second driving period P12 in the first driving stage P1, under the control of second clock signal input part CLKB,
6th switch transistor T 6 is connected so that first node N1 is connect with second electrical level signal input part V2；Meanwhile in the first clock signal
Under the control of input terminal CLKA, the 7th switch transistor T 7 is ended so that second node N2 does not connect with second electrical level signal input part V2
It connects.
As shown in figure 3, the phase inverter that above-described embodiment provides further includes：First node pull-down module 6 is controlled respectively with input
End VIN processed, first node N1 are connected with second electrical level signal input part V2, under the control of input control end VIN, control
Whether first node N1 connect with second electrical level signal input part V2；And/or second node pull-down module 7, it is controlled respectively with input
End VIN processed, second node N2 are connected with second electrical level signal input part V2, under the control of input control end VIN, control
Whether second node N2 connect with second electrical level signal input part V2.
Specifically, the first driving period P11 in the first driving stage P1 and the second driving period P12, is controlled in input
Under the control of end VIN processed, first node pull-down module 6 controls first node N1 and second electrical level signal input part V2 to be not connected to,
Second node pull-down module 7 controls second node N2 and second electrical level signal input part V2 to be not connected to.Stage P2 is driven second
In, under the control of input control end VIN, first node pull-down module 6 controls first node N1 to be inputted with second electrical level signal
V2 connections are held, second node pull-down module 7 controls second node N2 to be connect with second electrical level signal input part V2.
The phase inverter that above-described embodiment provides includes first node pull-down module 6 and second node pull-down module 7 so that
Second driving stage P2, first node pull-down module 6 can drag down the current potential of first node N1, second node pull-down module 7
The current potential of second node N2 can be dragged down, it is achieved thereby that can be by signal output end in the second driving stage P2 phase inverter
The current potential of VOUT faster drags down, and avoids and only the current potential of signal output end VOUT is dragged down by exporting pull-down module 3, institute
The current potential of signal output end VOUT being easy to cause drags down halfway problem.
Further, please continue to refer to Fig. 4, the first node pull-down module 6 that above-described embodiment provides includes the 8th switch
Pipe T8, the grid of the 8th switch transistor T 8 are connect with input control end VIN, and the first pole and the first node N1 of the 8th switch transistor T 8 connect
It connects, the second pole of the 8th switch transistor T 8 is connect with second electrical level signal input part V2；
Second node pull-down module 7 includes the 9th switch transistor T 9, and grid and the input control end VIN of the 9th switch transistor T 9 connect
It connects, the first pole of the 9th switch transistor T 9 is connect with second node N2, and the second pole of the 9th switch transistor T 9 and second electrical level signal are defeated
Enter V2 is held to connect.
Specifically, the first driving period P11 in the first driving stage P1 and the second driving period P12, is controlled in input
Under the control of end VIN processed, the 8th switch transistor T 8 is ended so that and first node N1 is not connected to second electrical level signal input part V2,
9th switch transistor T 9 is turned off so that second node N2 is not connected to second electrical level signal input part V2.The stage is driven second
In P2, under the control of input control end VIN, the 8th switch transistor T 8 is connected so that first node N1 and second electrical level signal are defeated
Enter V2 is held to connect, the 9th switch transistor T 9 is both turned on so that second node N2 is connect with second electrical level signal input part V2.It needs
It is bright, second driving stage P2 in, although T1 and T3 can alternate conduction, to the electricity of first node N1 and second node N2
Position has an impact, but since the 8th switch transistor T 8 and the 9th switch transistor T 9 are both turned on, remains able to ensure first node N1
Current potential with second node N2 is dragged down well, ensures the stability of inverters work.
Further, the breadth length ratio (W/L) of the 8th switch transistor T 8 and the 9th switch transistor T 9 can be set relative to the 5th switch
Breadth length ratio (W/L) smaller of pipe T5, the 6th switch transistor T 6 and the 7th switch transistor T 7 allow for the 8th switch transistor T 8 and the 9th in this way
Switch transistor T 9 can have smaller leakage current so that first node N1 and second node N2 can more stablize, thus into one
Step improves the stability of inverters work.
It should be noted that thin film transistor (TFT), field-effect tube or other characteristic phases may be used in above-mentioned each switching tube
Same device.In the above-described embodiments, to distinguish the two poles of the earth of each switching tube in addition to grid, wherein first will be known as in a pole
Pole, another pole are known as the second pole.In practical operation, described first can be extremely drain electrode, and described second extremely can be source electrode；Or
Person, described first extremely can be source electrode, and described second extremely can be drain electrode.
In addition, in the above-described embodiments using each switching tube as N-type transistor, and first extremely drains, the second extremely source
Extremely example illustrates.When switching tube each in above-described embodiment selects N-type transistor, mentioned in above-described embodiment
One level signal input terminal V1 is chosen as high level signal input terminal, is high level signal by the first level signal of its input
(VGH), second electrical level signal input part V2 is chosen as low level signal input terminal, is low electricity by the second electrical level signal of its input
Ordinary mail number (VGL).The first level of input control end VIN inputs mentioned in above-described embodiment is chosen as high level, input control
The second electrical level of VIN inputs in end processed is chosen as low level.Moreover, when phase inverter works normally, input control end VIN can be set
First level of input is identical with the high level signal that the first level signal input terminal V1 is inputted, input control end VIN inputs
Second electrical level is identical with the low level signal that second electrical level signal input part V2 is inputted.
In addition, above-mentioned each switching tube may be P-type transistor, and each switching tube is set for the circuit of P-type transistor
Meter is also within the protection domain of the application, when above-mentioned each switching tube is selected as P-type transistor, the electricity that is directed in Fig. 4
Lu Tu, only need to be defeated by the first clock signal input terminal CLKA the first clock signals inputted and second clock signal input part CLKB
The equal reverse phase of second clock signal (can be regarded as exchanging the corresponding waveforms of the CLKA waveform corresponding with CLKB in Fig. 5) entered,
And the first level signal input terminal V1 is exported into low level signal, it is by second electrical level signal input part V2 output high level signals
It can.
The embodiment of the present invention additionally provides a kind of shift register cell, the phase inverter provided including above-described embodiment.
Since the phase inverter that above-described embodiment provides has stable working performance, rail-to-rail output, and energy can be realized
The advantages that enough reducing the noise of the signal of signal output end output, therefore shift register cell provided in an embodiment of the present invention exists
During including above-mentioned phase inverter, equally have the advantages that above-mentioned, details are not described herein again.
The embodiment of the present invention additionally provides a kind of display device, the shift register cell provided including above-described embodiment.
Since above-mentioned shift register cell includes the phase inverter of above-described embodiment offer, the embodiment of the present invention provides
Display device is when including above-mentioned shift register cell, the advantages of being likewise supplied with above-mentioned shift register cell, herein no longer
It repeats.
The embodiment of the present invention additionally provides a kind of driving method of phase inverter, for the reverse phase that above-described embodiment is driven to provide
Device, the driving method include：The first phase inverting step is performed in the first driving stage P1, it is anti-to perform second in the second driving stage P2
Phase step；First driving stage P1 included the be arranged alternately first driving period P11 and the second driving period P12.
Above-mentioned first phase inverting step includes：
Period P11, input control end VIN input second electrical levels are driven first, the first pull-up module 1 is believed in the first clock
Under the control of number input terminal CLKA, the first level signal input terminal V1 of control is connect with signal output end VOUT；
Specifically, in first driving period P11, input control end VIN input second electrical level, output pull-down module 3 exists
Under the control of input control end VIN, control signal output VOUT is not connected to second electrical level signal input part V2.First pull-up
Module 1 controls the first level signal input terminal V1 and signal output end under the control of the first clock signal input terminal CLKA
VOUT connections, so that signal output end VOUT can export the first level signal.Meanwhile this first driving period P11,
Second pull-up module 2 is in idle state under the control of second clock signal input part CLKB, it is achieved thereby that at this
First driving period P11 only exported the first level signal by 1 control signal output VOUT of the first pull-up module.
Period P12, input control end VIN input second electrical levels are driven second, the second pull-up module 2 is believed in second clock
Under the control of number input terminal CLKB, the first level signal input terminal V1 of control is connect with signal output end VOUT.
Specifically, input control end VIN continues to input second electrical level, and output pull-down module 3 is in the control of input control end VIN
Under system, continue control signal output VOUT and second electrical level signal input part V2 and be not connected to.Second pull-up module 2 is at second
Under the control of clock signal input part CLKB, the first level signal input terminal V1 of control is connect with signal output end VOUT, so as to make
The first level signal can be exported by obtaining signal output end VOUT.Meanwhile in second driving period P11, the first pull-up module 1 exists
In idle state under the control of first clock signal input terminal CLKA, it is achieved thereby that in first driving period P11
The first level signal is only exported by 2 control signal output VOUT of the second pull-up module.
Above-mentioned second phase inverting step includes：
Input control end VIN inputs the first level, and output pull-down module 3 is under the control of input control end VIN, control letter
Number output terminal VOUT is connect with second electrical level signal input part V2.
Specifically, the first pull-up module 1 is in idle state under the control of the first clock signal input terminal CLKA,
Second pull-up module 2 is in idle state under the control of second clock signal input part CLKB.Input control end VIN is defeated
Enter the first level, output pull-down module 3 is under the control of input control end VIN, control signal output VOUT and second electrical level
Signal input part V2 connections, so that signal output end VOUT exports second electrical level signal.
When driving above-mentioned phase inverter using the driving method of phase inverter provided in an embodiment of the present invention, when first drives
Section P11, the second pull-up module 2 are in off position, only control the first level signal input terminal V1 by the first pull-up module 1
It is connect with signal output end VOUT so that signal output end VOUT can export the first level signal.And drive the period second
P12, the first pull-up module 1 are in off position, only by the second pull-up module 2 control the first level signal input terminal V1 with
Signal output end VOUT connections, so that signal output end VOUT can export the first level signal.It can be seen that utilizing this hair
When the driving method for the phase inverter that bright embodiment provides drives above-mentioned phase inverter, it can control in the first pull-up module 1 and second
Drawing-die block 2 works alternatively, avoid only by pull-up module it is in running order for a long time caused by mould crystalline substance in the block
Easily there is the problem of threshold voltage shift in body tube capacity so that above-mentioned phase inverter has higher job stability.
In the description of the above embodiment, particular features, structures, materials, or characteristics can be in any one or more
It is combined in an appropriate manner in a embodiment or example.
The above description is merely a specific embodiment, but protection scope of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in change or replacement, should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
1. a kind of phase inverter, which is characterized in that including：
First pull-up module is connect respectively with the first level signal input terminal, the first clock signal input terminal and signal output end,
For under the control of first clock signal input terminal, the first level signal input terminal being controlled to be exported with the signal
Whether end connects；
Second pull-up module, it is defeated with the first level signal input terminal, second clock signal input part and the signal respectively
Outlet connects, under the control of the second clock signal input part, controlling the first level signal input terminal and institute
State whether signal output end connects；
Pull-down module is exported, connect, is used for input control end, the signal output end and second electrical level signal input part respectively
Under the control at the input control end, the signal output end and the no connection of second electrical level signal input part are controlled.
2. phase inverter according to claim 1, which is characterized in that
First pull-up module includes first switch pipe and second switch pipe；Wherein, the grid of the first switch pipe and institute
The connection of the first clock signal input terminal is stated, the first pole of the first switch pipe is connect with the first level signal input terminal,
Second pole of the first switch pipe is connect with first node；The grid of the second switch pipe is connect with the first node,
First pole of the second switch pipe is connect with the first level signal input terminal, the second pole of the second switch pipe and institute
State signal output end connection；
Second pull-up module includes third switching tube and the 4th switching tube；Wherein, the grid of the third switching tube and institute
The connection of second clock signal input part is stated, the first pole of the third switching tube is connect with the first level signal input terminal,
Second pole of the third switching tube is connect with second node；The grid of 4th switching tube is connect with the second node,
First pole of the 4th switching tube is connect with the first level signal input terminal, the second pole of the 4th switching tube and institute
State signal output end connection；
The output pull-down module includes the 5th switching tube, and the grid of the 5th switching tube is connect with the input control end,
First pole of the 5th switching tube is connect with the signal output end, the second pole of the 5th switching tube and the described second electricity
Flat signal input part connection.
3. phase inverter according to claim 2, which is characterized in that
First pull-up module further includes the first capacitance, and the first end of first capacitance is connect with the first node, institute
The second end for stating the first capacitance is connect with the signal output end；And/or
Second pull-up module further includes the second capacitance, and the first end of second capacitance is connect with the second node, institute
The second end for stating the second capacitance is connect with the signal output end.
4. the phase inverter according to Claims 2 or 3, which is characterized in that the phase inverter further includes：
First node control module, respectively with the second clock signal input part, the second electrical level signal input part and institute
First node connection is stated, under the control of the second clock signal input part, controlling the first node and described the
Whether two level signal input terminals connect；And/or
Second node control module, respectively with first clock signal input terminal, the second electrical level signal input part and institute
Second node connection is stated, under the control of first clock signal input terminal, controlling the second node and described the
Whether two level signal input terminals connect.
5. phase inverter according to claim 4, which is characterized in that
The first node control module includes the 6th switching tube, grid and the second clock signal of the 6th switching tube
Input terminal connects, and the first pole of the 6th switching tube connect with the first node, the second pole of the 6th switching tube and
The second electrical level signal input part connection；
The second node control module includes the 7th switching tube, grid and first clock signal of the 7th switching tube
Input terminal connects, and the first pole of the 7th switching tube connect with the second node, the second pole of the 7th switching tube and
The second electrical level signal input part connection.
6. the phase inverter according to Claims 2 or 3, which is characterized in that the phase inverter further includes：
First node pull-down module inputs respectively with the input control end, the first node and the second electrical level signal
End connection, under the control at the input control end, controlling the first node and the second electrical level signal input part
Whether connect；And/or
Second node pull-down module inputs respectively with the input control end, the second node and the second electrical level signal
End connection, under the control at the input control end, controlling the second node and the second electrical level signal input part
Whether connect.
7. phase inverter according to claim 6, which is characterized in that
The first node pull-down module includes the 8th switching tube, and grid and the input control end of the 8th switching tube connect
It connects, the first pole of the 8th switching tube is connect with the first node, the second pole and described second of the 8th switching tube
Level signal input terminal connects；
The second node pull-down module includes the 9th switching tube, and grid and the input control end of the 9th switching tube connect
It connects, the first pole of the 9th switching tube is connect with the second node, the second pole and described second of the 9th switching tube
Level signal input terminal connects.
8. a kind of shift register cell, which is characterized in that including such as claim 1~7 any one of them phase inverter.
9. a kind of display device, which is characterized in that including shift register cell as claimed in claim 8.
10. a kind of driving method of phase inverter, which is characterized in that for driving such as claim 1~7 any one of them reverse phase
Device, the driving method include：The first phase inverting step is performed in the first driving stage, the second reverse phase is performed in the second driving stage
Step；The first driving stage includes the be arranged alternately first driving period and the second driving period；
First phase inverting step includes：
The period is driven described first, input control end input second electrical level, the first pull-up module is in the first clock signal input
Under the control at end, the first level signal input terminal is controlled to be connect with the signal output end；
The period is driven described second, the input control end inputs second electrical level, and the second pull-up module is in second clock signal
Under the control of input terminal, the first level signal input terminal is controlled to be connect with the signal output end；
Second phase inverting step includes：
The input control end inputs the first level, and output pull-down module is under the control at the input control end, described in control
Signal output end is connect with the second electrical level signal input part.
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