CN108231731A - Bonding pad structure and its manufacturing method - Google Patents
Bonding pad structure and its manufacturing method Download PDFInfo
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- CN108231731A CN108231731A CN201611201567.0A CN201611201567A CN108231731A CN 108231731 A CN108231731 A CN 108231731A CN 201611201567 A CN201611201567 A CN 201611201567A CN 108231731 A CN108231731 A CN 108231731A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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Abstract
A kind of bonding pad structure, including multiple materials pair and multiple connection pads.Multiple materials are to being stacked in substrate, to form a hierarchic structure.The single order of hierarchic structure includes a material pair.Each material is to the dielectric layer that includes conductor layer and in conductor layer.Each connection pad is embedded in the single order of hierarchic structure and exposes to the dielectric layer corresponding to the rank and another rank above the rank.The thickness of the one of connection pad is more than the thickness of the one of conductor layer.
Description
Technical field
The invention relates to a kind of bonding pad structure and its manufacturing method, and in particular to one kind for three-dimensional storage
The bonding pad structure and its manufacturing method of element.
Background technology
Increase with the integration of memory element, in order to reach high density and dynamical target, with three-dimensional storage member
Part substitution two-dimensional storage element already becomes a kind of trend.And rectilinear memory element is one kind in three-dimensional memory element.
Although rectilinear memory element can promote the memory capacity in unit area, also increase in rectilinear memory element and connect
The degree of difficulty of line.
In general, three-dimensional memory element is often with the conductor layer with hierarchic structure as connection pad, and utilize connection pad and its
On contact hole as internal connection-wire structure, in favor of the element and other elements of each layer of connection.However, carrying out contact hole quarter
It, can be because of the difference in height between the top surface of the connection pad of different location in hierarchic structure and dielectric layer thereon during etching technique so that
Most apical grafting pad is by overetch in hierarchic structure, and then leads to contact window through most apical grafting pad and extend to leading below
On body layer.Thus, which the contact hole subsequently formed then can be due to being electrically connected two connection pads or conductor layer, and then lead to member
The electrical failure of part.Therefore, how a kind of bonding pad structure and its manufacturing method are provided, there is hierarchic structure to avoid overetch
Bonding pad structure, for subject topic important at present.
Invention content
The present invention provides a kind of bonding pad structure and its manufacturing method with hierarchic structure, can prevent contact window work
Electrical failure problems during skill caused by overetch.
The present invention provides a kind of bonding pad structure and its manufacturing method with hierarchic structure, lifting process nargin and can increase
Add process yields.
The present invention provides a kind of bonding pad structure, including multiple materials pair and multiple connection pads.Multiple materials are to being stacked with
In in substrate, to form a hierarchic structure.The single order of hierarchic structure includes a material pair.Each material is to including conductor layer
And the dielectric layer in conductor layer.Each connection pad is embedded in the single order of hierarchic structure and exposes to corresponding to the rank
Dielectric layer and another rank above the rank.The thickness of the one of connection pad is more than the thickness of the one of conductor layer.
In one embodiment of this invention, the multiple material is to the plane extension along XY directions.The multiple material
To one protrude from the multiple material above it to another one side and expose the corresponding connection pad
Surface.
In one embodiment of this invention, the bonding pad structure further includes multiple plugs and extends along the Z direction and match respectively
It is placed on the connection pad.
In one embodiment of this invention, the width of each connection pad is more than the bottom width of corresponding plug.
In one embodiment of this invention, the material identical of the material of the plug and the connection pad.
In one embodiment of this invention, the material of the plug is different from the material of the connection pad.
In one embodiment of this invention, for upward angle of visibility degree, the shape of the connection pad include rectangular, round, rectangle,
Strip or combination.
In one embodiment of this invention, it is described to connect when the shape of the connection pad is strip for upward angle of visibility degree
Pad is arranged and is extended along the Y direction along the X direction.
In one embodiment of this invention, the bonding pad structure further includes bed course and is located at the hierarchic structure and the substrate
Between.
The present invention provides a kind of manufacturing method of bonding pad structure, and its step are as follows.Stacked structure is formed in substrate.It stacks
Structure includes the multiple materials pair being stacked with.To from top to bottom including the first material to N materials pair, N is multiple materials
Integer more than 1.Each material is to the second layer that includes first layer and on first layer.It is formed in the first material pair
Multiple first openings.First opening exposes the top surface of the second material pair.Patternized technique is carried out, stacked structure is patterned
For hierarchic structure, and the second opening is formed in every single order of hierarchic structure.The upright projection position of second opening corresponds to respectively
In the position of the first opening.Multiple third layer are respectively filled in the second opening, wherein the thickness of the one of third layer is more than the
The thickness of one layer of one.
In one embodiment of this invention, it is further comprising the steps of after third layer is respectively filled in the second opening.
Dielectric layer is formed in substrate.The surface of dielectric layer covering hierarchic structure and the top surface of third layer.Multiple connect is formed in the dielectric layer
Touch window opening.Contact window exposes the top surface of third layer respectively.Multiple plugs are respectively filled in contact window so that
The one of plug is connect with corresponding third layer.
In one embodiment of this invention, the material of the first layer includes silicon nitride, and the material of the second layer includes oxidation
Silicon, the material of third layer include silicon nitride.
In one embodiment of this invention, it is formed after dielectric layer and is formed before contact window in substrate, also wrapped
It includes and carries out tungsten substitution technique, the material of the material of first layer and third layer is substituted by tungsten (W).
In one embodiment of this invention, the tungsten substitution technique includes the following steps.In dielectric layer and hierarchic structure
Form an at least slit (slit).At least a slit extends to the bottom surface of hierarchic structure, to expose the first of multiple materials pair
The partial cross section of layer.Apply etching agent in an at least slit, remove first layer with third layer to form multiple gaps.It is sunk
Product technique, to be respectively formed multiple tungsten layers in gap.
In one embodiment of this invention, the material of the first layer includes polysilicon, and the material of the second layer includes oxidation
Silicon, the material of third layer include polysilicon.
In one embodiment of this invention, the material of the plug includes tungsten (W).
In one embodiment of this invention, the step of carrying out the Patternized technique is as follows.Light is formed on stacked structure
Photoresist layer.Photoresist layer exposes the one of the first opening.The first etching technics is carried out, removes the first material pair of part and part
The shape of the one of first opening is transferred to the second material centering by the second material pair.Photoresist layer is modified, to expose the
The another one of one opening.It carries out the second etching technics, removes the first material of part to, the second material pair of part and part third
The shape of the another one of first opening is transferred to the second material centering and turns the shape of the one of the first opening by material pair
Move on to third material centering.The step of finishing photoresist layer is with carrying out the second etching technics is repeated, until forming hierarchic structure.
In one embodiment of this invention, the manufacturing method of the bonding pad structure is additionally included between hierarchic structure and substrate
Form bed course.
Based on above-mentioned, the present embodiment can be by forming multiple openings in the most topping material pair of stacked structure.Then, by institute
The patterned hierarchic structure of stacked structure is stated, the opening is shifted and is formed in every single order of hierarchic structure.Then,
Conductor material is inserted in the opening, to form connection pad.Therefore, compared to existing connection pad, the thickness of the connection pad of the present embodiment
Degree is thicker, can prevent the electrical failure problems caused by overetch during contact window technique.In addition, with thickness compared with
Thick connection pad can promote process margin and the increase of contact window technique as the etching stop layer for forming contact window
Process yields.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and attached drawing appended by cooperation
It is described in detail below.
Description of the drawings
Fig. 1 is a kind of upper schematic diagram of memory element according to one embodiment of the invention.
Fig. 2 is the diagrammatic cross-section of the A-A ' lines of Fig. 1.
Fig. 3 A to Fig. 3 O are the diagrammatic cross-sections along the manufacturing process of the A-A ' lines of Fig. 1.
Fig. 4 A to Fig. 4 B are that a kind of the upper of the manufacturing process of bonding pad structure according to the first embodiment of the present invention regards signal
Figure.
Fig. 5 A to Fig. 5 B are respectively along the diagrammatic cross-section of the B-B ' lines of Fig. 4 A to Fig. 4 B.
Fig. 6 A to Fig. 6 B are that a kind of the upper of the manufacturing process of bonding pad structure according to the second embodiment of the present invention regards signal
Figure.
Fig. 7 A to Fig. 7 B are respectively along the diagrammatic cross-section of the C-C ' lines of Fig. 6 A to Fig. 6 B.
Fig. 8 A to Fig. 8 B are that a kind of the upper of the manufacturing process of bonding pad structure according to the third embodiment of the present invention regards signal
Figure.
Fig. 9 A to Fig. 9 B are respectively along the diagrammatic cross-section of the D-D ' lines of Fig. 8 A to Fig. 8 B.
【Symbol description】
10:Connection pad area
20:Array area
30:Peripheral region
100:Substrate
101:Bed course
102:Stacked structure
102’:Hierarchic structure
102a、102b、102c、102d、102e、102f、132、132a、132b、132c、132d、132e、132f:Material
It is right
103a、103b、103c、103d、103e、103f:Opening
104a、104b、104c、104d、104e、104f:First layer
105a、105b、105c、105d、105e、105f:Opening
106a、106b、106c、106d、106e、106f:The second layer (dielectric layer)
108、110:Photoresist layer
112:Insulating layer
112a、112b、112c、112d、112e、112f:Third layer
114a、114b、114c、114d、114e、114f:Conductor layer
116、116a:Dielectric layer
120、120a、120b、120c、120d、120e、120f、220、320;Degree pad
122a、122b、122c、122d、122e、122f:Contact window
124、124a、124b、124c、124d、124e、124f:Plug
X、Y、Z:Direction
D1、D2:Distance
H1、H2、H3:Highly
T1、T2、T3:Thickness
S:Normal value
ECDc、ECDs:Width
Specific embodiment
With reference to the attached drawing of the present embodiment more fully to illustrate the present invention.However, the present invention also can be with a variety of different shapes
Formula embodies, and should not necessarily be limited by embodiments described herein.The thickness of layer and region in attached drawing can for the sake of clarity be put
Greatly.The same or similar reference number represents the same or similar element, and paragraphs below will be repeated no longer one by one.
Fig. 1 is a kind of upper schematic diagram of memory element according to one embodiment of the invention.Fig. 2 is the A-A ' lines of Fig. 1
Diagrammatic cross-section.
Fig. 1 and Fig. 2 are please referred to, the first embodiment of the present invention provides a kind of memory element, including substrate 100.From upper
From the point of view of view, substrate 100 includes connection pad area 10, array area 20 and peripheral region 30.Connection pad area 10 is located at array area 20 and periphery
Between area 30.In one embodiment, array area 20 can be for example memory cell array area.Peripheral region 30 may include multiple low pressure half
Conductor element, e.g. low pressure N-type metal-oxide-semiconductor (MOS) (LV-NMOS) transistor, low pressure p-type metal-oxide-semiconductor (MOS) (LV-PMOS) are brilliant
Body pipe or combination.From the point of view of sectional view, as shown in Fig. 2, connection pad area 10 include multiple materials with hierarchic structure to 132,
It is respectively embedded into multiple connection pads 120 of multiple materials to 132 and multiple plugs 124 for being respectively arranged on multiple connection pads 120.
Connection pad 120 can be used to plug 124 as internal connection-wire structure, to be electrically connected the element of every single order in hierarchic structure and other
Element.
Specifically, referring to Fig. 1 and Fig. 2, multiple materials are stretched from array area 20 to 132 and terminate at connection pad area
10.Multiple materials extend along the plane in XY directions to 132 and are stacked with into a hierarchic structure.The single order of the hierarchic structure
Including a material pair.Each material is to including conductor layer (or first layer) and the dielectric layer in the conductor layer
(or second layer).For example, as shown in Fig. 2, conductor layer 114a and dielectric layer 106a can be considered a material to 132a or
The single order of hierarchic structure;And conductor layer 114b and dielectric layer 106b can be considered another material to the another of 132b or hierarchic structure
Single order.The configuration of other materials pair is just repeated no more herein with above-mentioned.In one embodiment, conductor layer 114a and dielectric layer
The combination of 106a can be considered that most bottom material to 132a, protrudes what side thereon was made of conductor layer 114b and dielectric layer 106b
Material is to the side of 132b so that is embedded in the conductor layer 114a and connection pad 120a in dielectric layer 106a and is exposed.Similarly,
132b is protruded by the material that conductor layer 114b and dielectric layer 106b are formed square by conductor layer 114c and dielectric layer thereon
The material that 106c is formed is to the side of 132c so that the connection pad 120b being embedded in conductor layer 114b and dielectric layer 106b exposes
Out.The stack manner of other materials pair is just repeated no more herein with above-mentioned.
On the other hand, as shown in Fig. 2, multiple plugs 124 extend and are respectively arranged on multiple connection pads 120 along the Z direction.
For example, plug 124a is configured and is connected on connection pad 120a so that plug 124a passes through connection pad 120a and conductor layer 114a
It is electrically connected.Similarly, plug 124b is configured and is connected on connection pad 120b so that plug 124b passes through connection pad 120b and conductor
Layer 114b is electrically connected.The configuration of other plugs and connection mode are just repeated no more herein with above-mentioned.
In addition, connection pad area 10 further includes a plurality of slit 130, extend from array area 20 and terminate at connection pad area 10.In detail
Say that a plurality of slit 130 extends, and arrange along the Y direction along the X direction in ground so that each slit 130 is located at adjacent two row
Between the plug 124 of (it extends along the X direction).Although the plug 124 and 3 for being arranged in 7 × 4 arrays is only shown in Fig. 1
Slit 130, however, the present invention is not limited thereto.In other embodiments, plug 124 and slit can be adjusted according to the demand of designer
130 quantity and arrangement.
It is noted that connection pad 120a-120f is not only for electrically connecting to plug 124a-124f and conductor layer 114a-
114f, can also be during contact window technique to as etching stop layer.For example, putting such as the connection pad 120a of Fig. 2
Shown in big figure, since the thickness T1 of connection pad 120a is more than the thickness T2 of conductor layer 114a, the thicker connection pad 120a of thickness can
Overetch effectively during blocking contact window technique.That is, even most tip cutting plug 124f will not run through most
Apical grafting pads 120f and extends to conductor layer 114e below.Therefore, the thicker connection pad 120 of the thickness of the present embodiment can prevent
Electrical failure problems during contact window technique caused by overetch.The thickness T1 of connection pad 120a can be for example 70 and receive
Rice (nm) is to 90nm.
Fig. 3 A to Fig. 3 O are the diagrammatic cross-sections along the manufacturing process of the A-A ' lines of Fig. 1.
Fig. 3 A are please referred to, first, provide substrate 100.In one embodiment, substrate 100 can be for example semiconductor base, half
There is semiconductor base (Semiconductor Over Insulator, SOI) on conductor compound substrate or insulating layer.Partly lead
Body is, for example, the atom of IVA races, such as silicon or germanium.Semiconducting compound is, for example, the semiconductor transformation that the atom of IVA races is formed
Conjunction object, the semiconducting compound that e.g. silicon carbide or germanium silicide or Group IIIA atom are formed with VA races atom, such as
It is GaAs.
Then, bed course 101 is formed in substrate 100.In one embodiment, bed course 101 can be silicon oxide layer, can be used
With the surface at protecting group bottom 100.
Later, stacked structure 102 is formed on bed course 101.In detail, stacked structure 102 includes being stacked with more
A material is to 102a-102f.As shown in Figure 3A, material can be considered 102a most bottom material pair;And material can be considered most 102f
Topping material pair.Material includes the first layer 104a and second layer 106a on first layer 104a to 102a.Similarly, material
The first layer 104b and second layer 106b on first layer 104b is included to 102b.Other materials matches 102c-102f
It puts as above-mentioned, just repeats no more herein.In one embodiment, first layer 104a-104f can be silicon nitride layer, and the second layer
106a-106f can be silicon oxide layer.In one embodiment, the thickness of the one of silicon nitride layer 104a-104f for 20nm extremely
40nm can be for example 28nm.The thickness of the one of silicon oxide layer 106a-106f is 40nm to 60nm, can be for example 52nm.
In alternative embodiments, first layer 104a-104f can be polysilicon layer, and second layer 106a-106f can be silicon oxide layer.
Although being only painted 6 materials pair in Fig. 3 A, the present invention is not limited.In other embodiments, the quantity of material pair can wrap
Include 8,15,21,27,33,39 or more.
Then, photoresist layer 108 is formed on stacked structure 102.Photoresist layer 108 has multiple opening 103a-103f.
Opening 103a-103f exposes the top surface of stacked structure 102 (or second layer 106f).The position of opening 103a-103f is right respectively
The position of connection pad 120a-120f that should be subsequently formed (as shown in Fig. 3 O).That is, the vertical throwing of opening 103a-103f
Shadow position is Chong Die with the position of connection pad 120a-120f subsequently formed respectively.
Fig. 3 A and Fig. 3 B are please referred to, is mask with photoresist layer 108, perform etching technique and removes portion of material pair
102f, in material to 102f in form multiple opening 105a-105f.Opening 105a-105f exposes material to 102e (or the
Two layers of 106e) top surface.In one embodiment, the etching technics may include dry etch process, e.g. reactive ion
Etching method (Reactive Ion Etching, RIE).
Fig. 3 B and Fig. 3 C are please referred to, removes photoresist layer 108.In one embodiment, the method for removing photoresist layer 108 can
To be elder generation with high-density plasma ashing photoresist layer 108 and then carry out wet cleaning processes.
Fig. 3 C to Fig. 3 I are please referred to, Patternized technique are carried out, by 102 patterned hierarchic structure 102 ' of stacked structure.
In detail, please also refer to Fig. 3 C and Fig. 3 D, photoresist layer 110 is formed on stacked structure 102.Photoresist layer 110 exposes
Be open 105a, and covers other openings 105b-105f.In one embodiment, the thickness of photoresist layer 110 or height H1 can be such as
It is 4000nm to 6000nm.
Fig. 3 D and Fig. 3 E are please referred to, is mask with photoresist layer 110, carries out the first etching technics, removal exposes to photoetching
The portion of material of glue-line 110 is to 102f and exposes to the portion of material of opening 105a to 102e so that the shape for the 105a that is open
Material is transferred to in 102e.Therefore, it is transferred to material and material is exposed to the opening 105a in 102e to 102d (or the second layers
Top surface 106d).At this point, as shown in FIGURE 3 E, photoresist layer 110 is also etched, and cause the thickness or height of photoresist layer 110
H2 is reduced to 3950nm to 5950nm.In one embodiment, first etching technics may include dry etch process, e.g.
Reactive ion etching method.In one embodiment, first etching technics can be twice etch step.For example, institute
The material of the second layer can be removed with first layer as etching stop layer by stating the first etching technics.And then with the second layer as quarter
Stop-layer is lost, removes the material of first layer.Thus, during first etching technics, material pair will be removed
Thickness.But the present invention is not limited, and in other embodiments, also can adjust the technological parameter of first etching technics, with
The thickness or quantity of material pair needed for removing.
Fig. 3 E and Fig. 3 F are please referred to, modifies (trim) photoresist layer 110, to expose opening 105b.The finishing refers to
Photoresist layer 110 is bounced back (pull back) distance D1.In the case, as illustrated in Figure 3 F, photoresist layer 110 exposes
Be open 105a, 105b.In one embodiment, the distance D1 can be for example 400nm to 600nm.It is modifying and the photoresist that bounces back
While layer 110, the thickness of photoresist layer 110 can also consume.(i.e. thickness H2 is subtracted the thickness of photoresist layer 110 through consumption
The value of thickness H3) it is bigger than distance D1.In one embodiment, distance D1 can be for example 500nm, and the photoresist layer through consumption
110 thickness can be for example 625nm.After modifying photoresist layer 110, the thickness or height H3 of photoresist layer 110 are reduced to
3325nm to 5325nm.That is, the thickness or height H1 when photoresist layer 110 are thicker, can more frequently be schemed
Case and photoetching glue correcting technique, to form more multistage hierarchic structure.Therefore, the thickness of photoresist layer 110 or height H1 can
It is adjusted on demand.
Fig. 3 F and Fig. 3 G are please referred to, is mask with photoresist layer 110, carries out the second etching technics, removes portion of material pair
The shape for the 105a that is open to 102d, is transferred to material in 102d by 102f, portion of material to 102e and portion of material, and
The shape for the 105b that is open is transferred to material in 102e.In the case, as shown in Figure 3 G, material is transferred to in 102d
Opening 105a exposes top surface of the material to 102c (or second layer 106c);And it is sudden and violent to the opening 105b in 102e to be transferred to material
Expose top surface of the material to 102d (or second layer 106d).At this point, as shown in Figure 3 G, photoresist layer 110 is also etched, and causes
The thickness or height H4 of photoresist layer 110 are reduced to 3275nm to 5275nm.
Fig. 3 G and Fig. 3 H are please referred to, modifies photoresist layer 110 so that the one distance D2 of retraction of photoresist layer 110, to expose
Be open 105c.In one embodiment, the distance D2 can be for example 400nm to 600nm.
Fig. 3 H and Fig. 3 I are please referred to, repeats above-mentioned the step of carrying out second etching technics and finishing photoresist layer 110, directly
To the hierarchic structure 102 ' formed as shown in fig. 31.In the case, as shown in fig. 31, multiple opening 105a-105f difference positions
In every single order of hierarchic structure 102 '.
Fig. 3 I and Fig. 3 J are please referred to, insulating layer 112 is formed in substrate 100.Insulating layer 112 covers hierarchic structure 102 '
Surface is simultaneously inserted in opening 105a-105f.In one embodiment, the thickness T3 of insulating layer 112 can be more than two points of opening 105a
One of width ECDs, with ensure be open 105a~105f can be filled.For another aspect, as shown in figure 3j, insulating layer 112
Thickness T3, which is at least greater than a material, can fill up the thickness of 102a opening 105a.In one embodiment, insulating layer 112
Material include silicon nitride, forming method can be chemical vapour deposition technique.
It please refers to Fig. 3 J and Fig. 3 K, removes partial insulative layer 112, to be respectively formed third layer being open in 105a-105f
112a-112f.In one embodiment, as shown in Fig. 3 K, the top surface of third layer 112a and material are coplanar to the top surface of 102a.Phase
As, the top surface of third layer 112b and material are coplanar to the top surface of 102b.The top surface of other third layer also with corresponding material
The top surface of material pair is coplanar, just repeats no more herein.
Fig. 3 K and Fig. 3 L are please referred to, dielectric layer 116 is formed in substrate 100.Dielectric layer 116 covers hierarchic structure 102 '
Surface and the top surface of third layer 112a-112f.In one embodiment, the material of dielectric layer 116 includes silica, forming method
It can be the deposition of dielectric materials layer in substrate 100 using chemical vapour deposition technique.Then flatening process is carried out again, such as
Chemical mechanical grinding CMP, to planarize the top surface of dielectric materials layer.
Fig. 3 L and Fig. 3 M are please referred to, tungsten substitution technique is carried out, by the material and third layer of first layer 104a-104f
The material of 112a-112f is substituted by tungsten (W).In detail, the step of tungsten substitution technique is as follows.First, in dielectric layer 116
With forming slit 130 in hierarchic structure 102 '.It is noted that although the section of Fig. 3 M does not show slit 130, from Fig. 1
In it is found that the extending direction of slit 130 is parallel to A-A ' lines direction.Slit 130 extends to the bottom surface of hierarchic structure 102 ', with sudden and violent
Expose partial cross section of the material to the first layer 104a-104f of 102a-102f.Apply etching agent in slit 130, remove first
Layer 104a-104f and third layer 112a-112f is to form multiple gaps (not being painted).Then, depositing operation is carried out, with described
Multiple tungsten layers are respectively formed in gap.In the case, as shown in fig.3m, after tungsten replaces technique, first layer 104a-104f
It is substituted by conductor layer 114a-114f;And third layer 112a-112f is substituted by connection pad 120a-120f.In the present embodiment,
The material of conductor layer 114a-114f and the material identical of connection pad 120a-120f, are all tungsten.In one embodiment, the etching
Agent can be the combination of hydrofluoric acid and hot phosphoric acid.In one embodiment, it can first apply hydrofluoric acid, apply hot phosphoric acid again later.
In alternative embodiments, when first layer 104a-104f be polysilicon layer, and second layer 106a-106f be silica
It, also can be without the tungsten substitution technique during layer.At this point, the material of connection pad 120a-120f can be for example polysilicon.
Fig. 3 M and Fig. 3 N are please referred to, multiple contact window 122a-122f are formed in dielectric layer 116a.Contact window
122a-122f exposes the surface of connection pad 120a-120f respectively.It is found that connection pad 120a-120f can be used to as shape from Fig. 3 N
Into the etching stop layer of contact window 122a-122f.Top surface compared to connection pad 120a and between the top surface of dielectric layer 116a
Distance, the top surface and the distance between the top surface of dielectric layer 116a of connection pad 120f is shorter, therefore, carry out contact window work
During skill, contact window 122f can first touch the top surface of most apical grafting pad 120f, and cause the etching consume of most apical grafting pad 120f
It is more.Compared to the thickness of existing connection pad, the connection pad 120a-120f that the thickness of the present embodiment is thicker can prevent contact window work
Overetch (especially for the overetch of most apical grafting pad 120f) during skill promotes the work of contact window technique whereby
Skill nargin simultaneously increases process yields.Incidentally, before contact window 122a-122f is formed, it is still necessary to carry out it
His technique, therefore, the thickness of the dielectric layer 116 of dielectric layer 116a thickness ratio Fig. 3 M of Fig. 3 N are thick.
Fig. 3 N and Fig. 3 O are please referred to, multiple plug 124a-124f are respectively filled in contact window 122a-122f, are made
Plug 124a-124f is obtained to connect with connection pad 120a-120f respectively.Therefore, plug 124a-124f can pass through connection pad 120a-120f
It is electrically connected respectively with conductor layer 114a-114f.Plug 124a-124f and connection pad 120a-120f can be used to as intraconnections knot
Structure, to be electrically connected element and other elements of the material with hierarchic structure to every single order in 132.In detail, will be more
The step that a plug 124a-124f is respectively filled in contact window 122a-122f includes carrying out depositing operation, by metal material
The top surface of dielectric layer 116a is inserted in contact window 122a-122f and covered to material.Then, flatening process is carried out, removes and is situated between
Metal material on the top surface of electric layer 116a.At this point, as shown in Fig. 3 O, the top surface of plug 124a-124f is with dielectric layer 116a's
Top surface is coplanar.In one embodiment, the metal material include tungsten, forming method can be physical vaporous deposition or
Chemical vapour deposition technique.The flatening process can be chemical mechanical grinding (CMP) technique.In one embodiment, plug
The material of 124a-124f and the material identical of connection pad 120a-120f.In alternative embodiments, the material of plug 124a-124f can
It is different from the material of connection pad 120a-120f.
Fig. 4 A to Fig. 4 B are that a kind of the upper of the manufacturing process of bonding pad structure according to the first embodiment of the present invention regards signal
Figure.Fig. 5 A to Fig. 5 B are respectively along the diagrammatic cross-section of the B-B ' lines of Fig. 4 A to Fig. 4 B.Fig. 6 A to Fig. 6 B are according to the present invention
Second embodiment a kind of bonding pad structure manufacturing process upper schematic diagram.Fig. 7 A to Fig. 7 B are respectively along Fig. 6 A to figure
The diagrammatic cross-section of the C-C ' lines of 6B.Fig. 8 A to Fig. 8 B are a kind of manufactures of bonding pad structure according to the third embodiment of the present invention
The upper schematic diagram of flow.Fig. 9 A to Fig. 9 B are respectively along the diagrammatic cross-section of the D-D ' lines of Fig. 8 A to Fig. 8 B.
It is noted that for upward angle of visibility degree, the shape of the connection pad includes rectangular (as shown in Figure 4 A), rectangle
(as shown in Figure 6A), strip (as shown in Figure 8 A) or combination.The width of the one of the connection pad is more than corresponding plug
The bottom width of (or contact window).
Please refer to Fig. 4 A, Fig. 4 B, Fig. 5 A and Fig. 5 B.In the first embodiment, the shape of connection pad 120 is rectangular, and its
The shape of corresponding contact window 122 is also rectangular.In one embodiment, the width ECDs of connection pad 120 is more than contact hole
The width ECDc of opening 122 adds 2 normal value S (it is, ECDs > ECDc+2S).So-called normal value S refers to repeatedly to specification
It is worth (overlay specification value) or repeatedly to tolerable value, depends on carrying out contact window technique
Exposure bench.For example, when argon fluoride (ArF) excimer laser that the exposure bench for forming contact window 122 is 193nm
During stepper (manufacturer ASML, board model 1450H), normal value S can be for example 10nm to 20nm.It is noted that
It, can be rounded in the connection pad 120 being actually formed although the shape of the connection pad 120 depicted in Fig. 4 A is rectangular.
Please refer to Fig. 6 A, Fig. 6 B, Fig. 7 A and Fig. 7 B.In a second embodiment, the shape of connection pad 220 is rectangle, and its
The shape of corresponding contact window 122 is rectangular.In one embodiment, the width ECDs of connection pad 220 is opened more than contact hole
The width ECDc of mouth 122 adds 2 normal value S (it is, ECDs > ECDc+2S).
Please refer to Fig. 8 A, Fig. 8 B, Fig. 9 A and Fig. 9 B.In the third embodiment, the shape of connection pad 320 is strip, and
The shape of contact window 122 corresponding to it is rectangular.Elongated connection pad 320 arranges and along the Y direction along the X direction
Extension.In one embodiment, the width ECDs of connection pad 320 is more than the width ECDc of contact window 122 plus 2 normal value S
(it is, ECDs > ECDc+2S).
In conclusion the present embodiment can be by forming multiple openings in the most topping material pair of stacked structure.Then, by institute
The patterned hierarchic structure of stacked structure is stated, the opening is shifted and is formed in every single order of hierarchic structure.Then,
Conductor material is inserted in the opening, to form connection pad.Therefore, compared to existing connection pad, the thickness of the connection pad of the present embodiment
Degree is thicker, can prevent the electrical failure problems caused by overetch during contact window technique.In addition, with thickness compared with
Thick connection pad can promote process margin and the increase of contact window technique as the etching stop layer for forming contact window
Process yields.
Although the present invention has been disclosed by way of example above, it is not intended to limit the present invention., any technical field
Middle those of ordinary skill, without departing from the spirit and scope of the present invention, when the change and modification that can make part, therefore the present invention
Protection domain is when subject to as defined in claim.
Claims (10)
1. a kind of bonding pad structure, which is characterized in that including:
Multiple materials pair are stacked in, to form a hierarchic structure, the single order of the hierarchic structure includes a material in a substrate
Material pair, each material is to the dielectric layer that includes conductor layer and in the conductor layer;And
Multiple connection pads, each connection pad are embedded in the single order of the hierarchic structure and expose to the dielectric layer corresponding to the rank with being somebody's turn to do
Another rank above rank, the wherein thickness of the one of those connection pads are more than the thickness of the one of those conductor layers.
2. bonding pad structure according to claim 1, wherein multiple material is to the plane extension along XY directions, it is multiple
Material to one protrude from multiple material above it to another one side and expose the corresponding connection pad
Surface.
3. bonding pad structure according to claim 2, which is characterized in that further include multiple plugs and extend along the Z direction and divide
It is not configured on those connection pads, wherein the width of those each connection pads is more than the bottom width of the corresponding plug.
4. bonding pad structure according to claim 1, wherein for upward angle of visibility degree, when the shape of those connection pads is strip
When, those connection pads are arranged and are extended along the Y direction along the X direction.
5. bonding pad structure according to claim 1, which is characterized in that further include a bed course and be located at the hierarchic structure and the base
Between bottom.
6. a kind of manufacturing method of bonding pad structure, which is characterized in that including:
Stacked arrangement is formed in a substrate, which includes the multiple materials pair being stacked with, multiple material pair
From top to bottom include the first material to N materials pair, N is the integer more than 1, and wherein each material is to including a first layer
And the second layer on the first layer;
Multiple first openings are formed in first material pair, those the first openings expose the top surface of second material pair;
A Patternized technique is carried out, by the patterned hierarchic structure of the stacked structure, and in every single order of the hierarchic structure
Middle to form one second opening, the upright projection position of wherein those the second openings corresponds respectively to the position of those the first openings;
And
By multiple third layer be respectively filled in those second opening in, wherein the thickness of the one of those third layer be more than those first
The thickness of the one of layer.
7. the manufacturing method of bonding pad structure according to claim 6, which is characterized in that those third layer are respectively filled in this
After in a little second openings, further include:
A dielectric layer is formed on this substrate, which covers the surface of the hierarchic structure and the top surface of those third layer;
Multiple contact windows are formed in the dielectric layer, those contact windows expose the top surface of those third layer respectively;
And
Multiple plugs are respectively filled in those contact windows so that the one of those plugs connects with the corresponding third layer
It connects.
8. the manufacturing method of bonding pad structure according to claim 7, which is characterized in that the material of those first layers includes nitrogen
SiClx or polysilicon, the material of those second layers include silica, and the material of those third layer includes silicon nitride or polysilicon.
9. the manufacturing method of bonding pad structure according to claim 8, which is characterized in that form the dielectric layer on this substrate
It later and is formed before those contact windows, further includes and carry out a tungsten substitution technique, by the material of those first layers with being somebody's turn to do
The material of a little third layer is substituted by tungsten (W).
10. the manufacturing method of bonding pad structure according to claim 6, which is characterized in that be additionally included in the hierarchic structure with
A bed course is formed between the substrate.
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7847334B2 (en) * | 2008-03-14 | 2010-12-07 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device and method of manufacturing the same |
US20130234232A1 (en) * | 2012-03-05 | 2013-09-12 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device and semiconductor device |
US8569829B2 (en) * | 2009-12-28 | 2013-10-29 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US8822285B2 (en) * | 2011-12-22 | 2014-09-02 | SK Hynix Inc. | Nonvolatile memory device and method of manufacturing the same |
US20150255385A1 (en) * | 2014-03-06 | 2015-09-10 | SK Hynix Inc. | Semiconductor device and method of fabricating the same |
US20160020169A1 (en) * | 2014-07-17 | 2016-01-21 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
-
2016
- 2016-12-22 CN CN201611201567.0A patent/CN108231731B/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7847334B2 (en) * | 2008-03-14 | 2010-12-07 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device and method of manufacturing the same |
US8569829B2 (en) * | 2009-12-28 | 2013-10-29 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US8822285B2 (en) * | 2011-12-22 | 2014-09-02 | SK Hynix Inc. | Nonvolatile memory device and method of manufacturing the same |
US20130234232A1 (en) * | 2012-03-05 | 2013-09-12 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device and semiconductor device |
US20150255385A1 (en) * | 2014-03-06 | 2015-09-10 | SK Hynix Inc. | Semiconductor device and method of fabricating the same |
US20160020169A1 (en) * | 2014-07-17 | 2016-01-21 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115084090A (en) * | 2021-03-16 | 2022-09-20 | 旺宏电子股份有限公司 | Semiconductor structure |
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