CN108231679B - Method for manufacturing chip - Google Patents
Method for manufacturing chip Download PDFInfo
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- CN108231679B CN108231679B CN201711499148.4A CN201711499148A CN108231679B CN 108231679 B CN108231679 B CN 108231679B CN 201711499148 A CN201711499148 A CN 201711499148A CN 108231679 B CN108231679 B CN 108231679B
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- photoresist layer
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- chip
- positive photoresist
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/30—Imagewise removal using liquid means
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70008—Production of exposure light, i.e. light sources
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a manufacturing method of a chip. The method comprises the following steps: providing a substrate base plate; forming a forward photoresist layer and chip assemblies wrapped on the forward photoresist layer on the substrate base plate, wherein the chip assemblies are wrapped on the forward photoresist layer in a matrix arrangement mode; carrying out exposure treatment on the positive photoresist layer; and developing the exposed positive photoresist layer to remove the part of the positive photoresist layer between two adjacent chip components. Therefore, the invention only needs to carry out exposure treatment and development treatment on the positive photoresist layer, the connecting parts between the adjacent chips can be removed, the separation between the chips can be realized without a cutting process, and the product yield is improved.
Description
Technical Field
The invention relates to the field of circuit manufacturing, in particular to the field of chip manufacturing, and particularly relates to a chip manufacturing method.
Background
As electronic products such as mobile phones, notebook computers, etc. are developed toward miniaturization, portability, ultra-thinning, multimedia and low cost meeting the public demands, high density, high performance, high reliability and low cost packaging forms and assembling techniques thereof are rapidly developed.
In the flip chip and packaging process, a substrate bearing a chip is of an integrated structure, small units which are arranged in an array mode are divided on the substrate, and each small unit is an area where one chip is located. Referring to fig. 1 to 3, in a conventional flip chip process, a chip assembly 121 having chips 12 is formed on each small unit 11 of a substrate 10 through drilling, plating, and other processes, and then, the chip assembly is washed with water, baked, and the like, and then, green paint 122 is plastic-encapsulated, baked, and the like until one chip 12 is arranged on the substrate 10 in a matrix, and then, the substrate 10 is fixed on a platform 31 by adsorption, and the substrate 10 is cut by a cutter 20, so that one chip 12 is separated.
In the actual cutting process, the cutting process often encounters a lot of quality problems, such as cutting deviation and cutting burrs, which easily affects the product yield, and the high-pressure water is needed to be used for washing during cutting, so that the product failure problem is easily generated, and the product yield is not easy to be improved.
Disclosure of Invention
In view of the above, the present invention provides a method for manufacturing chips, which can separate chips without a cutting process, thereby avoiding yield loss caused by cutting offset and cutting burrs, and facilitating improvement of product yield.
The method for manufacturing the chip of the embodiment of the invention comprises the following steps:
providing a substrate base plate;
forming a forward photoresist layer and chip assemblies wrapped on the forward photoresist layer on the substrate base plate, wherein the chip assemblies are wrapped on the forward photoresist layer in a matrix arrangement mode;
carrying out exposure treatment on the forward photoresist layer;
and developing the exposed positive photoresist layer to remove the part of the positive photoresist layer between two adjacent chip components.
Optionally, the chip assembly includes a second sub-circuit and a first sub-circuit connected up and down, and the chip assembly that forms the forward photoresist layer on the substrate and wraps up on the forward photoresist layer includes:
forming first sub-circuits arranged in a matrix on the substrate base plate;
forming a first positive photoresist layer wrapping the first sub-circuit on the substrate base plate;
forming second sub-circuits which are arranged in a matrix mode on the first forward photoresist layer, wherein the second sub-circuits are connected with the first sub-circuits in a one-to-one corresponding mode;
and forming a second positive photoresist layer wrapping the second sub-circuit on the first positive photoresist layer.
Optionally, the first positive photoresist layer exposes an electrical contact region at an upper end of the first sub-circuit, and a lower end of the second sub-circuit is connected to the first sub-circuit through the electrical contact region.
Optionally, before the first forward photoresist layer wraps the upper end of the first sub-circuit and the second sub-circuit arranged in a matrix is formed on the first forward photoresist layer, the method further includes:
drilling the first positive photoresist layer to expose an electrical contact area at the upper end of the first sub-circuit.
Optionally, the second sub-circuit is a chip having a pin, the first sub-circuit is a lead frame, and the first sub-circuit and the second sub-circuit are connected through the pin.
Optionally, a lamp source emitting ultraviolet light is used to perform exposure treatment on the forward photoresist layer.
Optionally, before performing the exposure treatment on the forward photoresist layer, the method further includes:
and arranging a plurality of light sources in a matrix arrangement above the forward photoresist layer, wherein the light sources and the chips are arranged in a one-to-one correspondence manner.
Optionally, before performing the exposure treatment on the forward photoresist layer, the method further includes:
separating the substrate from the positive photoresist layer and the chip assembly;
and adsorbing and fixing the separated positive photoresist layer and the chip assembly on a platform.
Optionally, the developing process is performed on the forward photoresist layer subjected to the exposure process, and includes:
and the positive photoresist layer carrying the chip assembly is carried and fixed in a developing solution through a clamp.
Optionally, after the developing treatment is performed on the forward photoresist layer subjected to the exposure treatment, the method further includes:
and cleaning and drying the chip assembly obtained after the development treatment.
Has the advantages that: the invention bears the chips on the positive photoresist layer, replaces the traditional substrate by the positive photoresist layer, only needs to carry out exposure treatment and development treatment on the positive photoresist layer, the connecting parts between the adjacent chips can be correspondingly removed, namely, the separation between the chips can be realized without a cutting process, thereby avoiding the yield loss caused by cutting offset and cutting burrs, being beneficial to improving the product yield, and avoiding the problem of product break loss without a high-pressure water washing process adopted by the cutting process, thereby being further beneficial to improving the product yield.
Drawings
FIG. 1 is a schematic diagram of a chip arrangement on a substrate according to an embodiment of the prior art;
FIG. 2 is a cross-sectional view of the structure of the substrate shown in FIG. 1;
FIG. 3 is a schematic diagram of the arrangement of chips on a substrate according to another embodiment of the prior art;
FIG. 4 is a flow chart illustrating a method for manufacturing a chip according to an embodiment of the invention;
FIG. 5 is a schematic diagram of a scenario for manufacturing a chip based on the method of FIG. 4;
FIG. 6 is a schematic diagram of an exposure process performed on a forward photoresist layer carrying a chip;
FIG. 7 is a schematic illustration of a developing process performed on a forward photoresist layer carrying a chip;
FIG. 8 is a schematic view of a chip carried on a jig after a development process;
fig. 9 is a schematic structural diagram of a chip package according to an embodiment of the invention.
Detailed Description
The main purposes of the invention are: one chip is loaded and formed on the positive photoresist layer, the traditional substrate is replaced by the positive photoresist layer, only the exposure treatment and the development treatment are carried out on the positive photoresist layer, the connecting part between the adjacent chips can be correspondingly removed, namely, the separation between the chips can be realized without a cutting process, so that the yield loss caused by cutting deviation and cutting burrs is avoided, the product yield is favorably improved, and the cutting process is not adopted, so that the process of washing the substrate bearing the chips by high-pressure water is not needed, the product break problem caused by the impact of the high-pressure water on the chips is avoided, and the product yield is further favorably improved.
The electronic devices to which the chip is applied include, but are not limited to, mobile terminals such as smart phones, PDAs (Personal digital assistants) and tablet computers, and wearable devices worn on limbs or embedded in clothes, ornaments and accessories.
The technical solution of the embodiment of the present invention is clearly and completely described below with reference to the accompanying drawings. The following embodiments and their technical features may be combined with each other without conflict. Also, directional terms used throughout the present invention, such as "upper" and "lower", are used for better description and are not used to limit the scope of the present invention.
Fig. 4 is a flowchart illustrating a method for manufacturing a chip according to an embodiment of the invention. As shown in fig. 4, the manufacturing method of the present embodiment includes steps S41 to S44.
S41: a substrate is provided.
As shown in fig. 5, the substrate 51 may be a plate structure, and the upper surface of the substrate is a plane. The upper surface of the substrate base plate 51 may be divided into a plurality of small units 511 arranged in a matrix, wherein each small unit 511 is used for wrapping a chip assembly and thereby defining the area of one chip.
S42: and forming a forward photoresist layer and chip components wrapped on the forward photoresist layer on the substrate, wherein the chip components are wrapped on the forward photoresist layer in a matrix arrangement mode.
Taking the chip assembly 50 shown in fig. 5 having two sub-circuits connected up and down as an example, the second sub-circuit 522 may be a chip having pins, correspondingly, the first sub-circuit 521 is a lead frame, the number of the lead frames 521 may be two as shown in fig. 5, and the two lead frames are spaced from each other, the number of the pins is the same as that of the lead frames 521, and the pins and the lead frames 521 are arranged in one-to-one correspondence. Of course, the chip assembly 50 of the present embodiment may also include only a chip with pins, i.e., only the second sub-circuit 522 is provided.
With reference to fig. 5, first, the first sub-circuits 521 are formed on the substrate 51 in a matrix arrangement, each first sub-circuit 521 is formed in one small unit 511, and adjacent first sub-circuits 521 are separately disposed. Then, a layer of liquid photoresist is uniformly coated on the substrate base plate 51 by a photoresist coating device, the liquid photoresist can cover the first sub-circuit 521, and after baking and forming, the liquid photoresist is solidified into a first forward photoresist layer 531 arranged in the same layer as the first sub-circuit 521. Then, second sub-circuits 522 arranged in a matrix are formed on the first forward photoresist layer 531, and the second sub-circuits 522 are connected to the first sub-circuits 521 in a one-to-one correspondence, which is equivalent to a conventional flip chip process, so as to form the chip assembly 50. Further, a layer of liquid photoresist is uniformly coated on the first forward photoresist layer 531 by a photoresist coating apparatus, the liquid photoresist can wrap the second sub-circuit 522, and after baking and forming, the liquid photoresist is cured into a second forward photoresist layer 532 wrapping the second sub-circuit 522, and the second forward photoresist layer 532 and the first forward photoresist layer 531 together form the forward photoresist layer 53 of this embodiment.
In order to connect the second sub-circuit 522 and the first sub-circuit 521, the first forward photoresist layer 531 may expose an upper surface (an electrical contact area at an upper end) of the first sub-circuit 521, so that a lower surface (or a lower end) of the second sub-circuit 522 is connected to the first sub-circuit 521 through the electrical contact area. Specifically, the first forward photoresist layer 531 and the first sub-circuit 521 are disposed at the same layer, the upper surface and the lower surface of the first forward photoresist layer 531 and the first sub-circuit 521 are flush, and the second forward photoresist layer 532 wraps the second sub-circuit 522.
Of course, the upper surface of the first forward photoresist layer 531 may be lower than the upper surface of the first sub-circuit 521, and the lower surface of the first forward photoresist layer 531 is flush with the lower surface of the first sub-circuit 521, so as to expose the upper surface of the first sub-circuit 521.
Further, the first forward photoresist layer 531 may also completely cover the upper end of the first sub-circuit 521, without exposing the upper surface thereof, but before the second sub-circuit 522 arranged in a matrix is formed, the first forward photoresist layer 531 is drilled, wherein a bridging hole is formed in the first forward photoresist layer 531, and the bridging hole exposes an electrical contact region located at the upper end of the first sub-circuit 521, so as to implement the connection between the second sub-circuit 522 and the first sub-circuit 521.
It should be understood that the chip assembly 50 is merely an exemplary illustration, and the present embodiment can also be applied to other configurations and shapes of the lead and lead frame according to the requirements of the practical application scenario.
S43: and exposing the positive photoresist layer.
As shown in fig. 5, the substrate base material 51 is separated from the forward photoresist layer 53. Further, referring to fig. 6, the forward photoresist layer 53 carrying the chip assemblies 50 is fixed on the platform 60 by an absorption manner, a plurality of light sources 61 arranged in a matrix are disposed above the forward photoresist layer 53, the light sources 61 can be used for emitting ultraviolet light, the light sources 61 are located between two adjacent chip assemblies 50, and then the light sources 61 emit ultraviolet light to expose the forward photoresist layer 53 located right below. Wherein the portion of the positive photoresist layer 53 between two adjacent chip components 50 is exposed, and the region where each chip component 50 is located is shielded from exposure.
S44: and developing the exposed positive photoresist layer to remove the part of the positive photoresist layer between two adjacent chip assemblies.
As shown in fig. 7, the positive photoresist layer 53 carrying the chip components 50 is carried and fixed in the developing tank 72 by the fixture 71, the structural design of the fixture 71 is not limited in this embodiment, the developing solution 73 in the developing tank 72 floods the positive photoresist layer 53, the exposed part of the positive photoresist layer 53 can be removed by the developing solution, and the unexposed part can not be removed by the developing solution, here, the part of the positive photoresist layer 53 between two adjacent chip components 50 is dissolved in the developing solution 73, as shown in fig. 8, and each chip component 50 is separated and carried on the fixture 71. Finally, the jig 71 is taken out of the developing tank 72, and the chip module 50 is cleaned and dried.
It can be seen from the above that, in the embodiment, the forward photoresist layer 53 replaces the conventional substrate, and only the forward photoresist layer 53 needs to be exposed and developed, the connecting portion between the adjacent chip assemblies 50 can be removed correspondingly, i.e., the separation between the chip assemblies 50 can be realized without the need of the cutting process, thereby avoiding the yield loss caused by the cutting offset and the cutting burr, and being beneficial to improving the product yield, and because the cutting process is not adopted, the substrate carrying the chip assemblies 50 does not need to be washed by high pressure water, thereby avoiding the product failure problem caused by the impact of the high pressure water on the chip assemblies 50, and further being beneficial to improving the product yield.
The invention also provides a photoresistance substrate for manufacturing the chip. The photoresist substrate may be a forward photoresist layer formed by using a forward photoresist, and of course, the forward photoresist layer may also be only used as a main body portion of the photoresist substrate, for example, the photoresist substrate may further include a green paint plastic package disposed on an outer side of the forward photoresist layer. The positive photoresist layer is divided into a plurality of small units which are arranged in an array mode, each small unit is used for wrapping one chip assembly, and the area, located between the adjacent chip assemblies, of the positive photoresist layer is an exposure and development area.
The forward photoresist layer may have different structures in order to accommodate chip components of different structures. Take a chip assembly having two sub-circuits connected up and down as an example, wherein the second sub-circuit may be a chip having pins, correspondingly, the first sub-circuit is a lead frame, the number of the lead frames may be two and the two are arranged at intervals, the number of the pins is the same as the number of the lead frames, and the pins and the lead frames are arranged in one-to-one correspondence. The forward photoresist layer comprises a first forward photoresist layer and a second forward photoresist layer, the second forward photoresist layer and the first forward photoresist layer are arranged in a vertically stacked mode, the first forward photoresist layer and the first sub-circuit are arranged in the same layer, the upper surface and the lower surface of the first sub-circuit are exposed, and the second forward photoresist layer wraps the second sub-circuit.
Wherein, in order to realize the connection between the second sub-circuit and the first sub-circuit, the first positive photoresist layer can expose the upper surface of the first sub-circuit, thereby the lower surface of the second sub-circuit is connected with the first sub-circuit. Specifically, the first forward photoresist layer and the first sub-circuit are arranged on the same layer, the upper surface and the lower surface of the first forward photoresist layer and the upper surface and the lower surface of the first sub-circuit are flush, and the second forward photoresist layer wraps the second sub-circuit. Of course, the upper surface of the first forward photoresist layer may be lower than the upper surface of the first sub-circuit, and the lower surface of the first forward photoresist layer is flush with the lower surface of the first sub-circuit, so as to expose the upper surface of the first sub-circuit.
Furthermore, the first forward photoresist layer may also completely cover the upper end of the first sub-circuit, and a hole is drilled in the upper surface of the first forward photoresist layer, where the first forward photoresist layer is provided with a bridging hole exposing the electrical contact region at the upper end of the first sub-circuit, and the connection between the second sub-circuit and the first sub-circuit is realized.
For the area of the forward photoresist layer between adjacent chip components, the method described in the embodiments of fig. 6 to 7 may be adopted to perform the exposure process and the development process, respectively, and will not be described herein again.
The invention further provides a chip package. Referring to fig. 9, the chip package 90 includes a chip assembly 91 and a package layer 92. The chip assembly 91 is wrapped in the encapsulation layer 92, the encapsulation layer 92 exposes the lower surface of the chip assembly 91 to expose the electrode contact area of the chip assembly 91, and the two sides of the encapsulation layer 92 are provided with positive photoresist.
Taking the chip assembly 91 having two sub-circuits connected up and down as an example, the second sub-circuit 912 may be a chip 912a having pins 912b, correspondingly, the first sub-circuit 911 may be a lead frame, the number of the lead frames 911 may be two as shown in fig. 9, and the two lead frames are arranged at intervals, the number of the pins is the same as that of the lead frames 911, and the pins and the lead frames 911 are arranged in one-to-one correspondence. The encapsulation layer 92 includes a first forward photoresist layer 921 and a second forward photoresist layer 922, the second forward photoresist layer 922 and the first forward photoresist layer 921 are stacked up and down, the first forward photoresist layer 921 and the first sub-circuit 911 are disposed on the same layer and expose the upper surface and the lower surface of the first sub-circuit 911, and the second forward photoresist layer 922 wraps the second sub-circuit 912.
In order to connect the second sub-circuit 912 and the first sub-circuit 911, the first positive photoresist layer 921 exposes the upper surface of the first sub-circuit 911, so that the lower surface of the second sub-circuit 912 is connected to the first sub-circuit 911. Specifically, the first forward photoresist layer 921 and the first sub-circuit 911 are disposed at the same layer, and the upper surface and the lower surface of the first forward photoresist layer 921 and the first sub-circuit 911 are flush with each other, and the second forward photoresist layer 922 covers the second sub-circuit 912.
Of course, the upper surface of the first forward photoresist layer 921 is lower than the upper surface of the first sub-circuit 911, and the lower surface of the first forward photoresist layer 921 is flush with the lower surface of the first sub-circuit 911, so as to expose the upper surface of the first sub-circuit 911.
Further, the first forward photoresist layer 921 may also completely cover the upper end of the first sub-circuit 911, and a hole is drilled in a portion of the first forward photoresist layer 921 located on the upper surface of the first sub-circuit 911, wherein a cross-over hole is formed in the first forward photoresist layer 921, and the cross-over hole exposes an electrical contact region located on the upper end of the first sub-circuit 911, so as to achieve the connection between the second sub-circuit 912 and the first sub-circuit 911.
In this embodiment, the exposable and developable area may be disposed only on both sides, that is, only the material of both sides is positive photoresist, and the interior of the positive photoresist may be made of conventional packaging material, such as resin. Here, at least one of the first forward photoresist layer 921 and the second forward photoresist layer 922 may adopt this structure design.
It should be understood that the above-mentioned embodiments are only examples of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures or equivalent flow changes made by using the contents of the present specification and the drawings, such as the combination of technical features between the embodiments, or the direct or indirect application to other related technical fields, are also included in the scope of the present invention.
Claims (9)
1. A method of manufacturing a chip, the method comprising:
providing a substrate base plate;
forming a forward photoresist layer and chip components wrapped on the forward photoresist layer on the substrate base plate, wherein the chip components are wrapped on the forward photoresist layer in a matrix arrangement mode and comprise a second sub-circuit and a first sub-circuit which are connected up and down;
carrying out exposure treatment on the forward photoresist layer;
developing the exposed positive photoresist layer to remove the part of the positive photoresist layer between two adjacent chip assemblies;
wherein, form forward light resistance layer and wrap up the chip subassembly on the forward light resistance layer on the substrate base plate, include:
forming first sub-circuits arranged in a matrix on the substrate base plate;
forming a first positive photoresist layer wrapping the first sub-circuit on the substrate base plate;
forming second sub-circuits which are arranged in a matrix mode on the first forward photoresist layer, wherein the second sub-circuits are connected with the first sub-circuits in a one-to-one corresponding mode;
and forming a second positive photoresist layer wrapping the second sub-circuit on the first positive photoresist layer.
2. The method of claim 1, wherein the first positive photoresist layer exposes an electrical contact area at an upper end of the first sub-circuit, and a lower end of the second sub-circuit is connected to the first sub-circuit through the electrical contact area.
3. The method of claim 1, wherein the first forward photoresist layer wraps an upper end of the first sub-circuit, and before forming the second sub-circuit in a matrix arrangement on the first forward photoresist layer, the method further comprises:
drilling the first positive photoresist layer to expose an electrical contact area at the upper end of the first sub-circuit.
4. The method of claim 1, wherein the second sub-circuit is a chip having pins, the first sub-circuit is a lead frame, and the first and second sub-circuits are connected by the pins.
5. The method of claim 1, wherein the positive photoresist layer is exposed to light using a lamp that emits ultraviolet light.
6. The method of claim 5, wherein prior to exposing the forward photoresist layer, the method further comprises:
and arranging a plurality of light sources in a matrix arrangement above the forward photoresist layer, wherein the light sources and the chips are arranged in a one-to-one correspondence manner.
7. The method of claim 1, wherein prior to exposing the forward photoresist layer, the method further comprises:
separating the substrate from the positive photoresist layer and the chip assembly;
and adsorbing and fixing the separated positive photoresist layer and the chip assembly on a platform.
8. The method according to claim 1, wherein the developing process of the exposed forward photoresist layer comprises:
and the positive photoresist layer carrying the chip assembly is carried and fixed in a developing solution through a clamp.
9. The method according to claim 1, wherein after the developing process is performed on the exposed forward photoresist layer, the method further comprises:
and cleaning and drying the chip assembly obtained after the development treatment.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711499148.4A CN108231679B (en) | 2017-12-29 | 2017-12-29 | Method for manufacturing chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711499148.4A CN108231679B (en) | 2017-12-29 | 2017-12-29 | Method for manufacturing chip |
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| CN108231679B true CN108231679B (en) | 2020-03-27 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101677070A (en) * | 2008-09-18 | 2010-03-24 | 玉晶光电股份有限公司 | Method for producing light-emitting diode and packaging adhesive material thereof by utilizing lithography process |
| CN101702401A (en) * | 2009-11-03 | 2010-05-05 | 中山大学 | Preparation and batch processed encapsulation method of GaN-based LED thin film device |
| CN103325731A (en) * | 2013-05-20 | 2013-09-25 | Tcl集团股份有限公司 | Manufacturing method of flexible display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020168590A1 (en) * | 2001-05-10 | 2002-11-14 | Jiunn-Ren Hwang | Method of forming storage nodes in a DRAM |
| DE102005053274A1 (en) * | 2005-09-30 | 2007-04-12 | Osram Opto Semiconductors Gmbh | Making semiconductor chips involves building up semiconductor layers, applying metal plating to epitaxial growth substrate and depositing metal layer galvanically before structuring and separating layers into individual chips |
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2017
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101677070A (en) * | 2008-09-18 | 2010-03-24 | 玉晶光电股份有限公司 | Method for producing light-emitting diode and packaging adhesive material thereof by utilizing lithography process |
| CN101702401A (en) * | 2009-11-03 | 2010-05-05 | 中山大学 | Preparation and batch processed encapsulation method of GaN-based LED thin film device |
| CN103325731A (en) * | 2013-05-20 | 2013-09-25 | Tcl集团股份有限公司 | Manufacturing method of flexible display device |
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