CN108226740A - The extension circuit plate for expanding joint test working group interface is provided - Google Patents
The extension circuit plate for expanding joint test working group interface is provided Download PDFInfo
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- CN108226740A CN108226740A CN201611127661.6A CN201611127661A CN108226740A CN 108226740 A CN108226740 A CN 108226740A CN 201611127661 A CN201611127661 A CN 201611127661A CN 108226740 A CN108226740 A CN 108226740A
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- group interface
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
- G01R31/2844—Fault-finding or characterising using test interfaces, e.g. adapters, test boxes, switches, PIN drivers
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- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The present invention discloses a kind of extension circuit plate for providing and expanding joint test working group interface, test data input pin, test data output pin, test clock pin and test pattern are selected into combination and control of the pin by the configuration of circuit, multiplexer and buffer, it provides expansion joint test working group interface to control with the joint test working group interface to expansion, can thereby reach offer extension joint test working group connecting interface to improve the technical effect of joint test working group testing requirement.
Description
Technical field
The present invention relates to a kind of extension circuit plates, refer in particular to a kind of by test data input pin, test data output
Pin, test clock pin and test pattern selection pin by the combination of the configuration of circuit, multiplexer and buffer with
Control provides and expands joint test working group interface and the joint test working group interface of expansion is controlled to provide expansion
The extension circuit plate of joint test working group interface.
Background technology
The boundary scan testing (boundary scan test) of general circuit or utilization boundary scan (boundary
Scan the test for) carrying out slot is typically to be tested by test access port controller, however test access port control
Device processed normally only provides a limited number of test access ports, if the boundary scan testing of circuit is to need a large amount of joint test works
Make group interface, then need using multiple test access port controllers, but so testing cost is higher, if usage quantity
It during limited test access port controller, and needs to expend the extra testing time, it is also possible to test signal be caused to cover
The problem of shortcoming.
In summary, it is known that always exist existing test access port controller for a long time in the prior art and test is provided
Access port limited amount and the problem of a large amount of tests can not be met or meet a large amount of test needs higher testing cost,
It is therefore desirable to propose improved technological means, come solve the problems, such as this one.
Invention content
In view of the prior art, there are existing test access port controllers to provide test access port limited amount and nothing
The a large amount of tests of method satisfaction or satisfaction largely test the problem of but needs higher testing cost, and the present invention discloses a kind of offer then
Expand the extension circuit plate of joint test working group interface, wherein：
Disclosed herein offer expand joint test working group interface extension circuit plate, it includes：Joint test
Working group (Joint Test Action Group, JTAG) extension circuit plate, joint test working group extension circuit plate more wrap
Contain：Joint test working group interface and eight expansion joint test working group interfaces.
Wherein, joint test working group interface further includes the first test data input (Test Data Input, TDI) and draws
Foot, the first test data output (Test Data Output, TDO) pin, the first test clock (Test Clock, TCK) draw
Foot and the first test pattern selection (Test Mode Select, TMS) pin；Joint test working group interface is electrically connected at
The test access port of test access port (Test Access Port, TAP) controller.
Expand joint test working group interface, each expands joint test working group interface and further includes the second test data
Input pin, the second test data output pin, the second test clock pin and the selection of the second test pattern.
First test data input pin is respectively and electrically connected to each expansion by the first multiplexer (Multiplexer)
Fill the second test data input pin of joint test working group interface；First test data output pin passes through the second multiplexer
It is respectively and electrically connected to each second test data output pin for expanding joint test working group interface；Each expands connection
The the second test data output pin for closing test job group interface passes through protective resistance and another expansion joint test working group
Second test data input pin of interface is electrically connected, and using, which makes each expand joint test working group interface, forms string
Connection；First test clock pin is electrically connected by the first buffer (Buffer) in expansion joint test working group interface
The second test clock pin；And first test pattern selection pin by the second buffer be electrically connected in expand combine
The second test pattern selection pin of test job group interface.
Disclosed herein circuit board as above, the difference between the prior art is the first test data input pin
Each second test data for expanding joint test working group connector is respectively and electrically connected to by the first multiplexer to input
Pin, the first test data output pin are respectively and electrically connected to each by the second multiplexer and expand joint test working group
Second test data output pin of interface, each expands the second test data output pin of joint test working group interface
It is electrically connected by the second test data input pin of protective resistance and another expansion joint test working group interface, first
Test clock pin is electrically connected by the first buffer in the second test clock for expanding joint test working group interface
Pin and the first test pattern selection pin are electrically connected by the second buffer to be connect in expansion joint test working group
Mouthful the second test pattern selection pin, use by test access port controller carry out the first multiplexer, the second multiplexer,
The expansion joint test working group interface that the control of first buffer and the second buffer is controlled with selected needs, after progress
The continuous various tests to joint test working group.
By above-mentioned technological means, the present invention can reach offer extension joint test working group interface to improve joint
The technical effect of test job group testing requirement.
Description of the drawings
Fig. 1 and Fig. 2 is schematically shown as the test number that the present invention provides the extension circuit plate for expanding joint test working group interface
According to input pin and test data output pin circuit connection schematic diagram.
Fig. 3 is schematically shown as the test clock pin electricity that the present invention provides the extension circuit plate for expanding joint test working group interface
Road line schematic diagram.
The test pattern selection that Fig. 4 is schematically shown as the extension circuit plate that the present invention provides expansion joint test working group interface is drawn
Foot circuit connection schematic diagram.
Fig. 5 is schematically shown as the present invention and provides the extension circuit plate for the extension circuit plate for expanding joint test working group interface with surveying
Try access port controller connection diagram.
【Symbol description】
10 joint test working group extension circuit plates
11 joint test working group interfaces
121 first expand joint test working group interface
122 second expand joint test working group interface
123 thirds expand joint test working group interface
124 the 4th expand joint test working group interface
125 the 5th expand joint test working group interface
126 the 6th expand joint test working group interface
127 the 7th expand joint test working group interface
128 the 8th expand joint test working group interface
13 first multiplexers
14 second multiplexers
151 first protective resistances
152 second protective resistances
153 third protective resistances
154 the 4th protective resistances
155 the 5th protective resistances
156 the 6th protective resistances
157 the 7th protective resistances
16 first buffers
171 first build-out resistors
172 first build-out resistors
173 first build-out resistors
174 first build-out resistors
175 first build-out resistors
176 first build-out resistors
177 first build-out resistors
178 first build-out resistors
181 second build-out resistors
182 second build-out resistors
183 second build-out resistors
184 second build-out resistors
185 second build-out resistors
186 second build-out resistors
187 second build-out resistors
188 second build-out resistors
19 second buffers
20 test access port controllers
21 test access ports
22 control input and output pins
TDI the first test data input pins
TDO the first test data output pins
TCK the first test clock pins
The first test patterns of TMS select pin
TDI_1 the second test data input pins
TDO_1 the second test data output pins
TCK_1 the second test clock pins
The second test patterns of TMS_1 select
TDI_2 the second test data input pins
TDO_2 the second test data output pins
TCK_2 the second test clock pins
The second test patterns of TMS_2 select
TDI_3 the second test data input pins
TDO_3 the second test data output pins
TCK_3 the second test clock pins
The second test patterns of TMS_3 select
TDI_4 the second test data input pins
TDO_4 the second test data output pins
TCK_4 the second test clock pins
The second test patterns of TMS_4 select
TDI_5 the second test data input pins
TDO_5 the second test data output pins
TCK_5 the second test clock pins
The second test patterns of TMS_5 select
TDI_6 the second test data input pins
TDO_6 the second test data output pins
TCK_6 the second test clock pins
The second test patterns of TMS_6 select
TDI_7 the second test data input pins
TDO_7 the second test data output pins
TCK_7 the second test clock pins
The second test patterns of TMS_7 select
TDI_8 the second test data input pins
TDO_8 the second test data output pins
TCK_8 the second test clock pins
The second test patterns of TMS_8 select
Specific embodiment
Carry out the embodiment that the present invention will be described in detail below in conjunction with schema and embodiment, thereby how the present invention is applied
Technological means can fully understand and implement according to this to solve technical problem and reach the realization process of technical effect.
First have to illustrate below disclosed herein offer expand the extension circuit plate of joint test working group interface.
Disclosed herein offer expand joint test working group interface extension circuit plate, it includes：Joint test
Working group (Joint Test Action Group, JTAG) extension circuit plate 10, joint test working group extension circuit plate 10 is more
Comprising：Joint test working group interface 11 and first expands joint test working group interface 121 to the 8th and expands joint test
Work group interface 128.
It is defeated that the joint test working group interface 11 of joint test working group extension circuit plate 10 further includes the first test data
Enter pin TDI, the first test data output pin TDO, the first test clock pin TCK and the first test pattern selection pin
TMS, the joint test working group interface 11 of joint test working group extension circuit plate 10 are to be used for being electrically connected to test to access
The test access port 21 of port (Test Access Port, TAP) controller 20.
First expansion joint test working group interface 121 further includes the second test data input pin TDI_1, the second test
Data output pins TDO_1, the second test clock pin TCK_1 and the second test pattern selection TMS_1.
Second expansion joint test working group interface 122 further includes the second test data input pin TDI_2, the second test
Data output pins TDO_2, the second test clock pin TCK_2 and the second test pattern selection TMS_2.
Third expands joint test working group interface 123 and further includes the second test data input pin TDI_3, the second test
Data output pins TDO_3, the second test clock pin TCK_3 and the second test pattern selection TMS_3.
4th expansion joint test working group interface 124 further includes the second test data input pin TDI_4, the second test
Data output pins TDO_4, the second test clock pin TCK_4 and the second test pattern selection TMS_4.
5th expansion joint test working group interface 125 further includes the second test data input pin TDI_5, the second test
Data output pins TDO_5, the second test clock pin TCK_5 and the second test pattern selection TMS_5.
6th expansion joint test working group interface 126 further includes the second test data input pin TDI_6, the second test
Data output pins TDO_6, the second test clock pin TCK_6 and the second test pattern selection TMS_6.
7th expansion joint test working group interface 127 further includes the second test data input pin TDI_7, the second test
Data output pins TDO_7, the second test clock pin TCK_7 and the second test pattern selection TMS_7.
8th expansion joint test working group interface 128 further includes the second test data input pin TDI_8, the second test
Data output pins TDO_8, the second test clock pin TCK_8 and the second test pattern selection TMS_8.
It please refers to shown in " Fig. 1 " and " Fig. 2 ", " Fig. 1 " and " Fig. 2 " is schematically shown as the present invention and provides expansion joint test work
Make the test data input pin of the extension circuit plate of group interface and test data output pin circuit connection schematic diagram.
First test data input pin TDI is electrically connected to the first expansion by the first multiplexer (Multiplexer) 13
Fill the second test data input pin TDI_1 of joint test working group interface 121；First test data input pin TDI leads to
Cross the second test data input pin that the first multiplexer 13 is electrically connected to the second expansion joint test working group interface 122
TDI_2；First test data input pin TDI is electrically connected to third by the first multiplexer 13 and expands joint test working group
Second test data input pin TDI_3 of interface 123；First test data input pin TDI passes through 13 electricity of the first multiplexer
Property be connected to the second test data input pin TDI_4 of the 4th expansion joint test working group interface 124；First test data
Input pin TDI is electrically connected to the second test of the 5th expansion joint test working group interface 125 by the first multiplexer 13
Data-out pin TDI_5；First test data input pin TDI is electrically connected to the 6th expansion by the first multiplexer 13 and joins
Close the second test data input pin TDI_6 of test job group interface 126；First test data input pin TDI passes through
One multiplexer 13 is electrically connected to the second test data input pin TDI_7 of the 7th expansion joint test working group interface 127；
And first test data input pin TDI by the first multiplexer 13 be electrically connected to the 8th expansion joint test working group connect
Second test data input pin TDI_8 of mouth 128.
First test data output pin TDO is electrically connected to the first expansion joint test by the second multiplexer 14 and works
Second test data output pin TDO_1 of group interface 121；First test data output pin TDO passes through the second multiplexer 14
It is electrically connected to the second test data output pin TDO_2 of the second expansion joint test working group interface 122；First test number
The second survey of third expansion joint test working group interface 123 is electrically connected to by the second multiplexer 14 according to output pin TDO
Try data output pins TDO_3；First test data output pin TDO is electrically connected to the 4th expansion by the second multiplexer 14
Second test data output pin TDO_4 of joint test working group interface 124；First test data output pin TDO passes through
Second multiplexer 14 is electrically connected to the second test data output pin TDO_ of the 5th expansion joint test working group interface 125
5；First test data output pin TDO is electrically connected to the 6th expansion joint test working group interface by the second multiplexer 14
126 the second test data output pin TDO_6；First test data output pin TDO is electrically connected by the second multiplexer 14
It is connected to the second test data output pin TDO_7 of the first expansion joint test working group interface 127；And first test data
Output pin TDO is electrically connected to the second test of the 8th expansion joint test working group interface 128 by the second multiplexer 14
Data output pins TDO_8.
First the second test data output pin TDO_1 for expanding joint test working group interface 121 passes through the first protection
The second test data input pin TDI_2 that resistance 151 and second expands joint test working group interface 122 is electrically connected.
Second the second test data output pin TDO_2 for expanding joint test working group interface 122 passes through the second protection
The second test data input pin TDI_3 that resistance 152 expands joint test working group interface 123 with third is electrically connected.
The second test data output pin TDO_3 that third expands joint test working group interface 123 is protected by third
The second test data input pin TDI_4 that resistance 153 and the 4th expands joint test working group interface 124 is electrically connected.
4th the second test data output pin TDO_4 for expanding joint test working group interface 124 passes through the 4th protection
The second test data input pin TDI_5 that resistance 154 and the 5th expands joint test working group interface 125 is electrically connected.
5th the second test data output pin TDO_5 for expanding joint test working group interface 125 passes through the 5th protection
The second test data input pin TDI_6 that resistance 155 and the 6th expands joint test working group interface 126 is electrically connected.
6th the second test data output pin TDO_6 for expanding joint test working group interface 126 passes through the 6th protection
The second test data input pin TDI_7 that resistance 156 and the 7th expands joint test working group interface 127 is electrically connected.
7th the second test data output pin TDO_7 for expanding joint test working group interface 127 passes through the 7th protection
The second test data input pin TDI_8 that resistance 157 and the 8th expands joint test working group interface 128 is electrically connected.
It uses so that first expands 121 to the 8th expansion joint test working group interface 128 of joint test working group interface
Series connection is formed, and the resistance value of 151 to the 7th protective resistance 157 of above-mentioned first protective resistance is between 10 ohm to 100 ohm,
This does not limit to the application category of the present invention with this by way of example only.
Then, it please refers to shown in " Fig. 3 ", " Fig. 3 " is schematically shown as the present invention and provides the expansion for expanding joint test working group interface
The test clock pin circuitry line schematic diagram of charging circuit plate.
First test clock pin TCK is electrically connected by the first buffer 16 expands joint test work in first
Second test clock pin TCK_1 to the 8th of group interface 121 expands the second test clock of joint test working group interface 128
Pin TCK_8.
And respectively by the first build-out resistor 171, first between the first test clock pin TCK and the first buffer 16
With resistance 172, the first build-out resistor 173, the first build-out resistor 174, the first build-out resistor 175, the first build-out resistor 176,
One build-out resistor 177 and the first build-out resistor 178 are electrically connected, above-mentioned first build-out resistor 171, the first build-out resistor 172,
First build-out resistor 173, the first build-out resistor 174, the first build-out resistor 175, the first build-out resistor 176, the first build-out resistor
177 and first build-out resistor 178 resistance value be 50 ohm.
First buffer 16 and first expand joint test working group interface 121 the second test clock pin TCK_1 it
Between be electrically connected respectively by the second build-out resistor 181；First buffer 16 and second expands joint test working group interface 122
The second test clock pin TCK_2 between be electrically connected respectively by the second build-out resistor 182；First buffer 16 and third
Expand between the second test clock pin TCK_3 of joint test working group interface 123 respectively by 183 electricity of the second build-out resistor
Property connection；First buffer 16 and the 4th expands between the second test clock pin TCK_4 of joint test working group interface 124
It is electrically connected respectively by the second build-out resistor 184；First buffer 16 and the 5th expands joint test working group interface 125
It is electrically connected respectively by the second build-out resistor 185 between second test clock pin TCK_5；First buffer 16 and the 6th expands
It fills electrical by the second build-out resistor 186 respectively between the second test clock pin TCK_6 of joint test working group interface 126
Connection；Divide between second test clock pin TCK_7 of the first buffer 16 and the 7th expansion joint test working group interface 127
It is not electrically connected by the second build-out resistor 187；And first buffer 16 and the 8th expand joint test working group interface 128
The second test clock pin TCK_8 between be electrically connected respectively by the second build-out resistor 188, above-mentioned second build-out resistor
181st, the second build-out resistor 182, the second build-out resistor 183, the second build-out resistor 184, the matching of the second build-out resistor 185, second
The resistance value of resistance 186, the second build-out resistor 187 and the second build-out resistor 188 is 100 ohm.
Pass through above-mentioned first build-out resistor 171, the first build-out resistor 172, the first build-out resistor 173, the first build-out resistor
174th, the first build-out resistor 175, the first build-out resistor 176, the first build-out resistor 177 and the first build-out resistor 178 and
Two build-out resistors 181, the second build-out resistor 182, the second build-out resistor 183, the second build-out resistor 184, the second build-out resistor
185th, the second build-out resistor 186, the second build-out resistor 187 and the second build-out resistor 188 can be improved when signal transmits
Stability.
First buffer 16 more it is standby simultaneously, selection or single enable (enable) expand with forbidden energy (disable) first
The the second test clock pin TCK_1 to the 8th for filling joint test working group interface 121 expands joint test working group interface 128
The second test clock pin TCK_8 control function.
Specifically, the first buffer 16 only enable first can expand the second of joint test working group interface 121 and survey
The of joint test working group interface 121 can be expanded by forbidden energy second simultaneously by trying clock pins TCK_1 and the first buffer 16
Two test clock pin TCK_2 to the 8th expand the second test clock pin TCK_8 of joint test working group interface 128,
This does not limit to the application category of the present invention with this by way of example only.
Specifically, the first buffer 16 can select enable first to expand the second of joint test working group interface 121
Test clock pin TCK_1 and third expand the second test clock pin TCK_3 of joint test working group interface 123, with
And first buffer 16 can expand the second test clock pin TCK_ of joint test working group interface 121 by forbidden energy second simultaneously
2nd, the 4th the second test clock pin TCK_4 to the 8th for expanding joint test working group interface 124 expands joint test work
Second test clock pin TCK_8 of group interface 128 herein by way of example only, does not limit to the application model of the present invention with this
Farmland.
Then, it please refers to shown in " Fig. 4 ", " Fig. 4 " is schematically shown as the present invention and provides the expansion for expanding joint test working group interface
The test pattern selection pin circuitry line schematic diagram of charging circuit plate.
First test pattern selects pin TMS to be electrically connected at the work of the first expansion joint test by the second buffer 19
The second test pattern selection pin TMS_1 of group interface 121；First test pattern selection pin TMS passes through the second buffer 19
It is electrically connected at the second test pattern selection pin TMS_2 of the second expansion joint test working group interface 122；First test mould
Formula selection pin TMS is electrically connected at the second survey of third expansion joint test working group interface 123 by the second buffer 19
Try mode selection pin TMS_3；First test pattern selects pin TMS to be electrically connected at the 4th expansion by the second buffer 19
The second test pattern selection pin TMS_4 of joint test working group interface 124；First test pattern selection pin TMS passes through
Second buffer 19 is electrically connected at the second test pattern selection pin TMS_ of the 5th expansion joint test working group interface 125
5；First test pattern selects pin TMS to be electrically connected at the 6th expansion joint test working group interface by the second buffer 19
126 the second test pattern selection pin TMS_6；First test pattern selection pin TMS is electrically connected by the second buffer 19
It is connected to the second test pattern selection pin TMS_7 of the 7th expansion joint test working group interface 127；And first test pattern
Selection pin TMS is electrically connected at the second test of the 8th expansion joint test working group interface 128 by the second buffer 19
Mode selection pin TMS_8.
Then, it please refers to shown in " Fig. 5 ", " Fig. 5 " is schematically shown as the present invention and provides the expansion for expanding joint test working group interface
The extension circuit plate of charging circuit plate and test access port controller connection diagram.
Pass through the first test number in the joint test working group interface 11 of above-mentioned joint test working group extension circuit plate 10
It is selected according to input pin TDI, the first test data output pin TDO, the first test clock pin TCK and the first test pattern
Pin TMS and first expands the second test data input pin TDI_1 in joint test working group interface 121, the second test number
Expand joint according to output pin TDO_1, the second test clock pin TCK_1 and the second test pattern selection TMS_1 to the 8th
Second test data input pin TDI_8, the second test data output pin TDO_8, second are surveyed in test job group interface 128
Try the electric connection configuration of clock pins TCK_8 and the second test pattern selection TMS_8.
The input of control signal can be carried out by the control input and output pin 22 of test access port controller 20, and
First multiplexer 13, the second multiplexer 14, first are buffered by the test access port 21 of test access port controller 20
16 and second buffer 19 of device is respectively controlled, and uses the first expansion joint test working group interface that selected needs control
121 to the 8th expand joint test working group interface 128, to carry out subsequently to the various tests of joint test working group.
In summary, it is known that the difference between the present invention and the prior art is the first test data input pin by the
One multiplexer be respectively and electrically connected to each expand joint test working group interface second test data input pin, first
Test data output pin by the second multiplexer be respectively and electrically connected to each expand joint test working group interface the
Two test data output pins, each second test data output pin for expanding joint test working group interface pass through protection
Second test data input pin of resistance and another expansion joint test working group interface is electrically connected, the first test clock
Pin by the first buffer be electrically connected in expand joint test working group interface the second test clock pin and
First test pattern selects pin to be electrically connected second in expansion joint test working group interface by the second buffer
Test pattern selects pin, uses and carries out the first multiplexer, the second multiplexer, the first buffering by test access port controller
The expansion joint test working group interface that the control of device and the second buffer is controlled with selected needs, to carry out subsequently to joint
The various tests of test job group.
Survey can be provided by this technological means to solve existing test access port controller present in the prior art
Examination access port limited amount and a large amount of tests can not be met or meet asking for the higher testing cost of a large amount of test needs
Topic, and then reach offer extension joint test working group interface to improve the technical effect of joint test working group testing requirement.
Although disclosed herein embodiment as above, only the content be not to directly limit the present invention it is special
Sharp protection domain.Any the technical staff in the technical field of the invention, do not depart from disclosed herein spirit and model
Under the premise of enclosing, a little change can be made in the formal and details of implementation.The scope of patent protection of the present invention, still must be with
Subject to appended claims institute defender.
Claims (9)
1. a kind of provide the extension circuit plate for expanding joint test working group interface, which is characterized in that includes：
One joint test working group extension circuit plate, the joint test working group extension circuit plate further include：
One joint test working group interface is used for being electrically connected to a test access port of a test access port controller,
The joint test working group interface further includes one first test data input pin, one first test data output pin, one
First test clock pin and one first test pattern selection pin；And
Eight expansion joint test working group interfaces, each expands joint test working group interface and further includes one second test number
It is selected according to input pin, one second test data output pin, one second test clock pin and one second test pattern；
Wherein, the first test data input pin is respectively and electrically connected to each expansion joint by one first multiplexer
The second test data input pin of test job group interface；
The first test data output pin is respectively and electrically connected to each by one second multiplexer and expands joint test
The second test data output pin of work group interface；
The second test data output pin of each expansion joint test working group interface is by a protective resistance and separately
The second test data input pin of one expansion joint test working group interface is electrically connected, and using makes each expansion
Joint test working group interface forms series connection；
The first test clock pin is electrically connected by one first buffer in the expansion joint test working group
The second test clock pin of interface；And
The first test pattern selection pin is electrically connected by one second buffer in the expansion joint test work
Make second test pattern selection pin of group interface.
2. as described in claim 1 provide the extension circuit plate for expanding joint test working group interface, which is characterized in that described
It is electrically connected between first buffer and the first test clock pin by one first build-out resistor.
3. as claimed in claim 2 provide the extension circuit plate for expanding joint test working group interface, which is characterized in that described
The resistance value of first build-out resistor is 50 ohm.
4. as described in claim 1 provide the extension circuit plate for expanding joint test working group interface, which is characterized in that described
It is electrically connected between first buffer and the second test clock pin by one second build-out resistor.
5. as claimed in claim 4 provide the extension circuit plate for expanding joint test working group interface, which is characterized in that described
The resistance value of second build-out resistor is 100 ohm.
6. as described in claim 1 provide the extension circuit plate for expanding joint test working group interface, which is characterized in that described
First buffer have simultaneously, the control function of the second test clock pin described in selection or single enable and forbidden energy.
7. as described in claim 1 provide the extension circuit plate for expanding joint test working group interface, which is characterized in that described
The resistance value of protective resistance is between 10 ohm to 100 ohm.
8. as described in claim 1 provide the extension circuit plate for expanding joint test working group interface, which is characterized in that described
Test access port controller further includes a control input and output pin.
9. as claimed in claim 8 provide the extension circuit plate for expanding joint test working group interface, which is characterized in that described
Control input and output pin is controlling first multiplexer, second multiplexer, first buffer and described
The expansion joint test working group interface that second buffer is controlled with selected needs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611127661.6A CN108226740B (en) | 2016-12-09 | 2016-12-09 | Expansion circuit board for providing interface of expansion joint test working group |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611127661.6A CN108226740B (en) | 2016-12-09 | 2016-12-09 | Expansion circuit board for providing interface of expansion joint test working group |
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| Publication Number | Publication Date |
|---|---|
| CN108226740A true CN108226740A (en) | 2018-06-29 |
| CN108226740B CN108226740B (en) | 2020-06-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201611127661.6A Active CN108226740B (en) | 2016-12-09 | 2016-12-09 | Expansion circuit board for providing interface of expansion joint test working group |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN114077564B (en) * | 2020-08-17 | 2024-03-29 | 英业达科技有限公司 | C-type universal serial bus adapter plate |
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