CN108205517B - FFT multiplexing method - Google Patents

Abstract

The invention provides an FFT multiplexing method, which comprises the following steps: step 1, performing D-time extraction according to externally input high-speed sampling data, and performing digital filtering on each item of extracted data; step 2, in continuous K/D clock cycles, respectively carrying out e on the filtered output data^‑2πk/KFrequency shift processing; step 3, in continuous K/D clock cycles, carrying out serial-to-parallel conversion on the obtained data, and updating the data once in K/D clock cycles; step 4, performing D-point parallel FFT processing on the D-point data respectively, and multiplexing FFT results in each clock cycle in K/D cycles; and 5, rearranging the results of the K-point FFT composed of the D-point FFT results obtained in each period, and outputting the results according to the engineering requirement sequence.

Description

FFT multiplexing method

Technical Field

The invention relates to a signal processing technology, in particular to an FFT multiplexing method.

Background

Fast Fourier Transform (FFT) is a fast algorithm of Discrete Fourier Transform (DFT), is an important mathematical tool for describing the relation between time domain and frequency domain of discrete signals, and is widely applied in the aspect of digital signal processing. The conventional FFT algorithm can be implemented by software, DSP, dedicated FFT processing chip or FPGA, etc. The software and DSP are implemented at a low speed, so that the requirement of real-time processing of high-speed signals in a digital receiver cannot be met; although the speed of the special FFT processing chip is high, the special FFT processing chip is expensive and is not easy to widely popularize. The FPGA has the advantages of rich resources, high speed and flexible design, and is widely applied in recent years.

The design scheme of the FFT processor realized by the FPGA at present can be divided into serial processing and parallel processing according to data flow. The serial processing only uses one butterfly unit for each butterfly operation, so that the processing mode is simple and the operation speed is relatively slow. The parallel processing has high operation speed and occupies more resources, which is particularly difficult for systems with less space and hardware resources. Therefore, the FFT multiplexing method is provided, the contradiction between the internal processing speed of the FPGA and the resource consumption is effectively balanced by multiplexing the butterfly operation unit and adopting semi-parallel pipeline operation, the requirement on logic resources is effectively reduced, and the requirement on engineering application is met.

Disclosure of Invention

The invention aims to provide an FFT multiplexing method, which comprises the following steps:

step 1, performing D-time extraction according to externally input high-speed sampling data, and performing digital filtering on each item of extracted data;

step 2, in continuous K/D clock cycles, respectively carrying out e on the filtered output data^-j2πk/KFrequency shift processing, wherein K is 0 to K/D-1;

step 3, in continuous K/D clock cycles, carrying out serial-to-parallel conversion on the obtained data, and updating the data once in K/D clock cycles;

step 4, performing D-point parallel FFT processing on the D-point data respectively, and multiplexing FFT results in each clock cycle in K/D cycles;

and 5, rearranging the results of the K-point FFT composed of the D-point FFT results obtained in each period, and outputting the results according to the engineering requirement sequence.

Compared with the prior art, the invention has the following remarkable advantages: (1) optimizing logic resource occupation of an FFT module by multiplexing a butterfly operation unit; (2) semi-parallel pipeline operation is adopted, so that the high-speed data processing capacity is improved; (3) the contradiction between the internal processing speed of the FPGA and the resource consumption is effectively balanced; (4) and the output data is sequenced, so that the system processing complexity is reduced.

The invention is further described below with reference to the accompanying drawings.

Drawings

FIG. 1 is a flow chart of the method of the present invention.

Fig. 2 is a data flow diagram of a 32-point parallel FFT algorithm.

Detailed Description

With reference to fig. 1 and fig. 2, an FFT multiplexing method is characterized by comprising the following steps:

step 1, performing D-time extraction according to externally input high-speed sampling data, and performing digital filtering on each item of extracted data;

step 2, in continuous K/D clock cycles, respectively carrying out e on the filtered output data^-j2πk/KFrequency shift processing, wherein K is 0 to K/D-1;

step 3, in continuous K/D clock cycles, carrying out serial-to-parallel conversion on the obtained data, and updating the data once in K/D clock cycles;

step 4, performing D-point parallel FFT processing on the D-point data respectively, and multiplexing FFT results in each clock cycle in K/D cycles;

and 5, rearranging the results of the K-point FFT composed of the D-point FFT results obtained in each period, and outputting the results according to the engineering requirement sequence.

Step 1, performing D-time extraction and filtering on high-speed sampling data, and comprising the following steps of:

step 11, firstly, carrying out phase-splitting acquisition and latching on input high-speed sampling data;

step 12, extracting data of each phase according to the D times;

step 13, performing equivalent extraction preparation on the coefficients of the FIR low-pass filter according to the D times of extraction sampling data;

and step 14, matching the coefficient of the D-time extraction FIR low-pass filter according to the D-time extraction sampling data for filtering.

The step 2 specifically comprises the following steps:

step 21, according to e in each K/D period^-j2πk/KA frequency shift process in which K is 0 to K/D-1, and a frequency shift coefficient is prepared;

and step 22, performing complex multiplication on the output filtering data and the frequency shift coefficient according to each K/D period to realize frequency shifting.

Step 4, multiplexing the FFT result of the D-point parallel data in each clock cycle of the K/D cycles, which specifically comprises the following steps:

step 41, preparing input frequency shift data, wherein the input data in K/D periods are x (m), x (m + D), x (m + D2), x (m + + D3), … and x (m + (K/D-1) × D) data;

and step 42, realizing the K-point FFT by using the D-point FFT in K/D periods by using the frequency shift characteristic of the FFT.

The step 5 specifically comprises the following steps:

step 51, converting to the result sequence of the FFT of the K points according to the FFT output result of each D point in the K/D periods;

step 52, changing the frequency shift direction of the FFT at the D point of each period in the K/D periods, and further changing the result sequence of the FFT output in each period;

and 53, performing adjacent channel conversion on the FFT result at the odd-even time in the result, and realizing the sequential arrangement and output of the FFT result.

Examples

Setting a 64-channel filter bank (K is 64), wherein the sampling rate fs of high-speed signals is 2.6GHz, an external AD is divided into 8 phases (8 times of extraction is carried out, D is 8) to enter an FPGA, and the data rate of each phase is 325MHz, namely the running rate of the FPGA is 325 MHz; the filter bank output rate fo is fs/64 is 40.625MHz, the multiplexing multiple of each phase data is fpga operation rate/output rate 325/40.625 is 8, i.e. 8 times multiplexing; the method comprises the following specific steps:

step 1, performing D-time extraction according to externally input high-speed sampling data, and performing digital filtering on each item of extracted data;

step 11, firstly, dividing input 2.6GHz high-speed sampling data into 8 phases to carry out FPGA acquisition and latching;

step 12, extracting data of each phase according to 8 times;

step 13, performing equivalent extraction preparation on the coefficients of the FIR low-pass filter according to the 8 times of extraction sampling data;

and step 14, matching 8 times of extraction FIR low-pass filter coefficients according to 8 times of extraction sampling data for filtering.

Step 2, in 8 continuous clock cycles, respectively carrying out e on the filtered output data^-j2πk/8Frequency shifting, wherein k is 0-7;

step 21, according to e in each K/D period^-j2πk/KA frequency shift process in which K is 0 to K/D-1, and a frequency shift coefficient is prepared;

and step 22, performing complex multiplication on the output filtering data and the frequency shift coefficient according to each K/D period to realize frequency shifting.

Step 3, in 8 continuous clock cycles, carrying out serial-to-parallel conversion on the obtained data, and updating the data once in 8 clock cycles;

step 4, performing parallel FFT processing on the D point data respectively, and multiplexing FFT results in each clock cycle in K/D cycles respectively;

step 41, preparing input frequency shift data, wherein the input data in 8 periods are x (m), x (m +8), x (m +16), x (m +24), … and x (m + 63);

step 42, using 8-point FFT to realize 64-point FFT in 8 periods by using the frequency shift characteristic of FFT;

the 8-point FFT data b (m) in each 8 cycles is:

and c, performing 8-point FFT operation on the b (m), and sequentially ordering the obtained FFT results as shown in table 1.

Table 1 sequence table for realizing 64-point FFT output result by 8-point FFT

En8	1	0	0	0	0	0	0	0
									Q0	0	63	62	61	60	59	58	57
Q1	32	31	30	29	28	27	26	25
									Q2	16	15	14	13	12	11	10	9
Q3	48	47	46	45	44	43	42	41
									Q4	8	7	6	5	4	3	2	1
Q5	40	39	38	37	36	35	34	33
									Q6	24	23	22	21	20	19	18	17
Q7	56	55	54	53	52	51	50	49

Wherein, the sequence of every 8 periods is distinguished according to En8, and the output result of each branch is obtained.

And 5, rearranging the 64-point FFT results which are jointly formed by the 8-point FFT results obtained in each period, and outputting the results according to the engineering requirement sequence.

Step 51, according to the output result of each 8-point FFT in 8 periods, converting to the result sequence of 64-point FFT, as shown in Table 1;

step 52, changing the frequency shift direction of the 8-point FFT in each period within 8 periods, and further changing the result sequence of the FFT output in each period;

the conventional frequency shift direction is subjected to frequency shift according to the sequence of 0-7, and due to the symmetry of the frequency shift, the frequency shift processing is performed according to the sequence of [01-12-23-34], and the result is shown in table 2.

TABLE 2 sequence chart of 64-point FFT output results after frequency conversion and frequency shift

En8	1	0	0	0	0	0	0	0
									Q0	0	63	1	62	2	61	3	60
Q1	32	31	33	30	34	29	35	28
									Q2	16	15	17	14	18	13	19	12
Q3	48	47	49	46	50	45	51	44
									Q4	8	7	9	6	10	5	11	4
Q5	40	39	41	38	42	37	43	36
									Q6	24	23	25	22	26	21	27	20
Q7	56	55	57	54	58	53	59	52

And 53, performing adjacent channel conversion on the FFT result at the odd-even time in the result, and realizing the sequential arrangement and output of the FFT result.

First, for table 2, two adjacent rows at odd time are subjected to data interchange, and the obtained results are shown in table 3.

TABLE 3 64-point FFT output result sequence table after odd time conversion

En8		1	0	0	0	0	0	0	0
										Q0		63	62	61	60	59	58	57	56
Q1		0	1	2	3	4	5	6	7
										Q2		31	33	29	35	27	37	25	39
Q3		32	30	34	28	36	26	38	24
										Q4		47	49	45	51	43	53	41	55
Q5		16	14	18	12	20	10	22	8
										Q6		15	17	13	19	11	21	9	23
Q7		48	46	50	44	52	42	54	40

Again, the different rows are sorted in increasing order as shown in Table 4.

Table 4 sequence table of 64-point FFT output results after changing row sequence

Finally, the middle six rows are simply exchanged with adjacent rows at odd-numbered time, so that the final sequentially ordered FFT result output can be obtained, as shown in table 5.

TABLE 5 64-point FFT output result sequence table after sequencing

En8	1	0	0	0	0	0	0	0
									Q1	0	1	2	3	4	5	6	7
Q6	15	14	13	12	11	10	9	8
									Q5	16	17	18	19	20	21	22	23
Q2	31	30	29	28	27	26	25	24
									Q3	32	33	34	35	36	37	38	39
Q4	47	46	45	44	43	42	41	40
									Q7	48	49	50	51	52	53	54	55
Q0	63	62	61	60	59	58	57	56

Claims (3)

1. An FFT multiplexing method, comprising the steps of:

step 1, performing D-time extraction according to externally input high-speed sampling data, and performing digital filtering on each item of extracted data;

step 2, in continuous K/D clock cycles, respectively carrying out e on the filtered output data^-j2πk/KFrequency shift processing, wherein K is 0-K/D-1, and K is the number of filter channels;

step 3, in continuous K/D clock cycles, carrying out serial-to-parallel conversion on the obtained data, and updating the data once in K/D clock cycles;

step 4, performing D-point parallel FFT processing on the D-point data respectively, and multiplexing FFT results in each clock cycle in K/D cycles;

step 5, rearranging the K-point FFT results formed by the D-point FFT results obtained in each period, and outputting the K-point FFT results according to the engineering requirement sequence;

step 4, multiplexing the FFT result of the D-point parallel data in each clock cycle of the K/D cycles, specifically including the following steps:

step 41, preparing input frequency shift data, wherein the input data in K/D periods are x (m), x (m + D), x (m + D2), x (m + D3), … and x (m + (K/D-1) D) data;

step 42, using D-point FFT to realize K-point FFT in K/D periods by using the frequency shift characteristic of FFT;

wherein, the step 5 specifically comprises the following steps:

step 51, converting to the result sequence of the FFT of the K points according to the FFT output result of each D point in the K/D periods;

step 52, changing the frequency shift direction of the FFT at the D point of each period in the K/D periods, and further changing the result sequence of the FFT output in each period;

and 53, performing adjacent channel conversion on the FFT result at the odd-even time in the result, and realizing the sequential arrangement and output of the FFT result.

2. The method of claim 1, wherein the D-fold decimation and filtering of the high speed sampled data in step 1 comprises the steps of:

step 11, firstly, carrying out phase-splitting acquisition and latching on input high-speed sampling data;

step 12, extracting data of each phase according to the D times;

step 13, performing equivalent extraction preparation on the coefficients of the FIR low-pass filter according to the D times of extraction sampling data;

and step 14, matching the coefficient of the D-time extraction FIR low-pass filter according to the D-time extraction sampling data for filtering.

3. The method according to claim 1, characterized in that step 2 comprises in particular the steps of:

step 21, according to e in each K/D period^-j2πk/KA frequency shift process in which K is 0 to K/D-1, and a frequency shift coefficient is prepared;

and step 22, performing complex multiplication on the output filtering data and the frequency shift coefficient according to each K/D period to realize frequency shifting.

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